1 /* 2 * Copyright 2016 - Vikas Manocha <vikas.manocha (at) st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 /dts-v1/; 44 #include "stm32f746.dtsi" 45 #include <dt-bindings/memory/stm32-sdram.h> 46 47 / { 48 model = "STMicroelectronics STM32F769-DISCO board"; 49 compatible = "st,stm32f769-disco", "st,stm32f7"; 50 51 chosen { 52 bootargs = "root=/dev/ram rdinit=/linuxrc"; 53 stdout-path = "serial0:115200n8"; 54 }; 55 56 memory { 57 reg = <0xC0000000 0x1000000>; 58 }; 59 60 aliases { 61 serial0 = &usart1; 62 spi0 = &qspi; 63 mmc0 = &sdio2; 64 /* Aliases for gpios so as to use sequence */ 65 gpio0 = &gpioa; 66 gpio1 = &gpiob; 67 gpio2 = &gpioc; 68 gpio3 = &gpiod; 69 gpio4 = &gpioe; 70 gpio5 = &gpiof; 71 gpio6 = &gpiog; 72 gpio7 = &gpioh; 73 gpio8 = &gpioi; 74 gpio9 = &gpioj; 75 gpio10 = &gpiok; 76 }; 77 78 led1 { 79 compatible = "st,led1"; 80 led-gpio = <&gpioj 5 0>; 81 }; 82 83 button1 { 84 compatible = "st,button1"; 85 button-gpio = <&gpioa 0 0>; 86 }; 87 }; 88 89 &clk_hse { 90 clock-frequency = <25000000>; 91 }; 92 93 &pinctrl { 94 usart1_pins_a: usart1@0 { 95 pins1 { 96 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 97 bias-disable; 98 drive-push-pull; 99 slew-rate = <2>; 100 }; 101 pins2 { 102 pinmux = <STM32F746_PA10_FUNC_USART1_RX>; 103 bias-disable; 104 }; 105 }; 106 107 ethernet_mii: mii@0 { 108 pins { 109 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, 110 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, 111 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, 112 <STM32F746_PA2_FUNC_ETH_MDIO>, 113 <STM32F746_PC1_FUNC_ETH_MDC>, 114 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, 115 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, 116 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, 117 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; 118 slew-rate = <2>; 119 }; 120 }; 121 122 qspi_pins: qspi@0 { 123 pins { 124 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, 125 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, 126 <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>, 127 <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>, 128 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, 129 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; 130 slew-rate = <2>; 131 }; 132 }; 133 134 fmc_pins: fmc@0 { 135 pins { 136 pinmux = <STM32F746_PI10_FUNC_FMC_D31>, 137 <STM32F746_PI9_FUNC_FMC_D30>, 138 <STM32F746_PI7_FUNC_FMC_D29>, 139 <STM32F746_PI6_FUNC_FMC_D28>, 140 <STM32F746_PI3_FUNC_FMC_D27>, 141 <STM32F746_PI2_FUNC_FMC_D26>, 142 <STM32F746_PI1_FUNC_FMC_D25>, 143 <STM32F746_PI0_FUNC_FMC_D24>, 144 <STM32F746_PH15_FUNC_FMC_D23>, 145 <STM32F746_PH14_FUNC_FMC_D22>, 146 <STM32F746_PH13_FUNC_FMC_D21>, 147 <STM32F746_PH12_FUNC_FMC_D20>, 148 <STM32F746_PH11_FUNC_FMC_D19>, 149 <STM32F746_PH10_FUNC_FMC_D18>, 150 <STM32F746_PH9_FUNC_FMC_D17>, 151 <STM32F746_PH8_FUNC_FMC_D16>, 152 153 <STM32F746_PD10_FUNC_FMC_D15>, 154 <STM32F746_PD9_FUNC_FMC_D14>, 155 <STM32F746_PD8_FUNC_FMC_D13>, 156 <STM32F746_PE15_FUNC_FMC_D12>, 157 <STM32F746_PE14_FUNC_FMC_D11>, 158 <STM32F746_PE13_FUNC_FMC_D10>, 159 <STM32F746_PE12_FUNC_FMC_D9>, 160 <STM32F746_PE11_FUNC_FMC_D8>, 161 <STM32F746_PE10_FUNC_FMC_D7>, 162 <STM32F746_PE9_FUNC_FMC_D6>, 163 <STM32F746_PE8_FUNC_FMC_D5>, 164 <STM32F746_PE7_FUNC_FMC_D4>, 165 <STM32F746_PD1_FUNC_FMC_D3>, 166 <STM32F746_PD0_FUNC_FMC_D2>, 167 <STM32F746_PD15_FUNC_FMC_D1>, 168 <STM32F746_PD14_FUNC_FMC_D0>, 169 170 <STM32F746_PI5_FUNC_FMC_NBL3>, 171 <STM32F746_PI4_FUNC_FMC_NBL2>, 172 <STM32F746_PE1_FUNC_FMC_NBL1>, 173 <STM32F746_PE0_FUNC_FMC_NBL0>, 174 175 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, 176 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, 177 178 <STM32F746_PG1_FUNC_FMC_A11>, 179 <STM32F746_PG0_FUNC_FMC_A10>, 180 <STM32F746_PF15_FUNC_FMC_A9>, 181 <STM32F746_PF14_FUNC_FMC_A8>, 182 <STM32F746_PF13_FUNC_FMC_A7>, 183 <STM32F746_PF12_FUNC_FMC_A6>, 184 <STM32F746_PF5_FUNC_FMC_A5>, 185 <STM32F746_PF4_FUNC_FMC_A4>, 186 <STM32F746_PF3_FUNC_FMC_A3>, 187 <STM32F746_PF2_FUNC_FMC_A2>, 188 <STM32F746_PF1_FUNC_FMC_A1>, 189 <STM32F746_PF0_FUNC_FMC_A0>, 190 191 <STM32F746_PH3_FUNC_FMC_SDNE0>, 192 <STM32F746_PH5_FUNC_FMC_SDNWE>, 193 <STM32F746_PF11_FUNC_FMC_SDNRAS>, 194 <STM32F746_PG15_FUNC_FMC_SDNCAS>, 195 <STM32F746_PH2_FUNC_FMC_SDCKE0>, 196 <STM32F746_PG8_FUNC_FMC_SDCLK>; 197 slew-rate = <2>; 198 }; 199 }; 200 }; 201 202 &usart1 { 203 pinctrl-0 = <&usart1_pins_a>; 204 pinctrl-names = "default"; 205 status = "okay"; 206 }; 207 208 &fmc { 209 pinctrl-0 = <&fmc_pins>; 210 pinctrl-names = "default"; 211 status = "okay"; 212 213 /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ 214 bank1: bank@0 { 215 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4 216 CAS_3 SDCLK_2 RD_BURST_EN 217 RD_PIPE_DL_0>; 218 st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 219 TRP_2 TRCD_2>; 220 /* refcount = (64msec/total_row_sdram)*freq - 20 */ 221 st,sdram-refcount = < 1542 >; 222 }; 223 }; 224 225 &mac { 226 status = "okay"; 227 pinctrl-0 = <ðernet_mii>; 228 phy-mode = "rmii"; 229 phy-handle = <&phy0>; 230 231 mdio0 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 compatible = "snps,dwmac-mdio"; 235 phy0: ethernet-phy@0 { 236 reg = <0>; 237 }; 238 }; 239 }; 240 241 &qspi { 242 pinctrl-0 = <&qspi_pins>; 243 status = "okay"; 244 245 qflash0: n25q128a { 246 #address-cells = <1>; 247 #size-cells = <1>; 248 compatible = "micron,n25q128a13", "spi-flash"; 249 spi-max-frequency = <108000000>; 250 spi-tx-bus-width = <1>; 251 spi-rx-bus-width = <1>; 252 memory-map = <0x90000000 0x1000000>; 253 reg = <0>; 254 }; 255 }; 256 257 &sdio2 { 258 status = "okay"; 259 cd-gpios = <&gpioi 15 0>; 260 cd-inverted; 261 pinctrl-names = "default", "opendrain"; 262 pinctrl-0 = <&sdio_pins_b>; 263 pinctrl-1 = <&sdio_pins_od_b>; 264 bus-width = <4>; 265 max-frequency = <25000000>; 266 }; 267
