1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 5 */ 6 7 #include <common.h> 8 #include <asm/arch/bootrom.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/grf_rk3399.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/periph.h> 13 #include <asm/io.h> 14 #include <debug_uart.h> 15 #include <dm.h> 16 #include <dm/pinctrl.h> 17 #include <ram.h> 18 #include <spl.h> 19 #include <syscon.h> 20 21 void board_return_to_bootrom(void) 22 { 23 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 24 } 25 26 static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 27 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", 28 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", 29 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", 30 }; 31 32 const char *board_spl_was_booted_from(void) 33 { 34 u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR); 35 const char *bootdevice_ofpath = NULL; 36 37 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 38 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 39 40 if (bootdevice_ofpath) 41 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 42 __func__, bootdevice_brom_id, bootdevice_ofpath); 43 else 44 debug("%s: failed to resolve brom_bootdevice_id %x\n", 45 __func__, bootdevice_brom_id); 46 47 return bootdevice_ofpath; 48 } 49 50 u32 spl_boot_device(void) 51 { 52 u32 boot_device = BOOT_DEVICE_MMC1; 53 54 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 55 return BOOT_DEVICE_BOOTROM; 56 57 return boot_device; 58 } 59 60 #define TIMER_CHN10_BASE 0xff8680a0 61 #define TIMER_END_COUNT_L 0x00 62 #define TIMER_END_COUNT_H 0x04 63 #define TIMER_INIT_COUNT_L 0x10 64 #define TIMER_INIT_COUNT_H 0x14 65 #define TIMER_CONTROL_REG 0x1c 66 67 #define TIMER_EN 0x1 68 #define TIMER_FMODE (0 << 1) 69 #define TIMER_RMODE (1 << 1) 70 71 void secure_timer_init(void) 72 { 73 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); 74 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); 75 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); 76 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); 77 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); 78 } 79 80 void board_debug_uart_init(void) 81 { 82 #define GRF_BASE 0xff770000 83 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; 84 85 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) 86 /* Enable early UART0 on the RK3399 */ 87 rk_clrsetreg(&grf->gpio2c_iomux, 88 GRF_GPIO2C0_SEL_MASK, 89 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); 90 rk_clrsetreg(&grf->gpio2c_iomux, 91 GRF_GPIO2C1_SEL_MASK, 92 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); 93 #else 94 /* Enable early UART2 channel C on the RK3399 */ 95 rk_clrsetreg(&grf->gpio4c_iomux, 96 GRF_GPIO4C3_SEL_MASK, 97 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); 98 rk_clrsetreg(&grf->gpio4c_iomux, 99 GRF_GPIO4C4_SEL_MASK, 100 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); 101 /* Set channel C as UART2 input */ 102 rk_clrsetreg(&grf->soc_con7, 103 GRF_UART_DBG_SEL_MASK, 104 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); 105 #endif 106 } 107 108 void board_init_f(ulong dummy) 109 { 110 struct udevice *pinctrl; 111 struct udevice *dev; 112 struct rk3399_pmusgrf_regs *sgrf; 113 struct rk3399_grf_regs *grf; 114 int ret; 115 116 #define EARLY_UART 117 #ifdef EARLY_UART 118 /* 119 * Debug UART can be used from here if required: 120 * 121 * debug_uart_init(); 122 * printch('a'); 123 * printhex8(0x1234); 124 * printascii("string"); 125 */ 126 debug_uart_init(); 127 printascii("U-Boot SPL board init"); 128 #endif 129 130 ret = spl_early_init(); 131 if (ret) { 132 debug("spl_early_init() failed: %d\n", ret); 133 hang(); 134 } 135 136 /* 137 * Disable DDR and SRAM security regions. 138 * 139 * As we are entered from the BootROM, the region from 140 * 0x0 through 0xfffff (i.e. the first MB of memory) will 141 * be protected. This will cause issues with the DW_MMC 142 * driver, which tries to DMA from/to the stack (likely) 143 * located in this range. 144 */ 145 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); 146 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); 147 rk_clrreg(&sgrf->slv_secure_con4, 0x2000); 148 149 /* eMMC clock generator: disable the clock multipilier */ 150 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 151 rk_clrreg(&grf->emmccore_con[11], 0x0ff); 152 153 secure_timer_init(); 154 155 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 156 if (ret) { 157 debug("Pinctrl init failed: %d\n", ret); 158 return; 159 } 160 161 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 162 if (ret) { 163 debug("DRAM init failed: %d\n", ret); 164 return; 165 } 166 } 167 168 #ifdef CONFIG_SPL_LOAD_FIT 169 int board_fit_config_name_match(const char *name) 170 { 171 /* Just empty function now - can't decide what to choose */ 172 debug("%s: %s\n", __func__, name); 173 174 return 0; 175 } 176 #endif 177
