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      1 // SPDX-License-Identifier: GPL-2.0
      2 /*
      3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
      4  *
      5  */
      6 
      7 #include <common.h>
      8 #include <asm/io.h>
      9 #include <asm/arch/reset_manager.h>
     10 #include <asm/arch/system_manager.h>
     11 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
     12 
     13 DECLARE_GLOBAL_DATA_PTR;
     14 
     15 static const struct socfpga_reset_manager *reset_manager_base =
     16 		(void *)SOCFPGA_RSTMGR_ADDRESS;
     17 static const struct socfpga_system_manager *system_manager_base =
     18 		(void *)SOCFPGA_SYSMGR_ADDRESS;
     19 
     20 /* Assert or de-assert SoCFPGA reset manager reset. */
     21 void socfpga_per_reset(u32 reset, int set)
     22 {
     23 	const void *reg;
     24 
     25 	if (RSTMGR_BANK(reset) == 0)
     26 		reg = &reset_manager_base->mpumodrst;
     27 	else if (RSTMGR_BANK(reset) == 1)
     28 		reg = &reset_manager_base->per0modrst;
     29 	else if (RSTMGR_BANK(reset) == 2)
     30 		reg = &reset_manager_base->per1modrst;
     31 	else if (RSTMGR_BANK(reset) == 3)
     32 		reg = &reset_manager_base->brgmodrst;
     33 	else	/* Invalid reset register, do nothing */
     34 		return;
     35 
     36 	if (set)
     37 		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
     38 	else
     39 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
     40 }
     41 
     42 /*
     43  * Assert reset on every peripheral but L4WD0.
     44  * Watchdog must be kept intact to prevent glitches
     45  * and/or hangs.
     46  */
     47 void socfpga_per_reset_all(void)
     48 {
     49 	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
     50 
     51 	/* disable all except OCP and l4wd0. OCP disable later */
     52 	writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
     53 	       &reset_manager_base->per0modrst);
     54 	writel(~l4wd0, &reset_manager_base->per0modrst);
     55 	writel(0xffffffff, &reset_manager_base->per1modrst);
     56 }
     57 
     58 void socfpga_bridges_reset(int enable)
     59 {
     60 	if (enable) {
     61 		/* clear idle request to all bridges */
     62 		setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
     63 
     64 		/* Release bridges from reset state per handoff value */
     65 		clrbits_le32(&reset_manager_base->brgmodrst, ~0);
     66 
     67 		/* Poll until all idleack to 0 */
     68 		while (readl(&system_manager_base->noc_idleack))
     69 			;
     70 	} else {
     71 		/* set idle request to all bridges */
     72 		writel(~0, &system_manager_base->noc_idlereq_set);
     73 
     74 		/* Enable the NOC timeout */
     75 		writel(1, &system_manager_base->noc_timeout);
     76 
     77 		/* Poll until all idleack to 1 */
     78 		while ((readl(&system_manager_base->noc_idleack) ^
     79 			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
     80 			;
     81 
     82 		/* Poll until all idlestatus to 1 */
     83 		while ((readl(&system_manager_base->noc_idlestatus) ^
     84 			(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
     85 			;
     86 
     87 		/* Put all bridges (except NOR DDR scheduler) into reset */
     88 		setbits_le32(&reset_manager_base->brgmodrst,
     89 			     ~RSTMGR_BRGMODRST_DDRSCH_MASK);
     90 
     91 		/* Disable NOC timeout */
     92 		writel(0, &system_manager_base->noc_timeout);
     93 	}
     94 }
     95 
     96 /* of_reset_id: emac reset id
     97  * state: 0 - disable reset, !0 - enable reset
     98  */
     99 void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
    100 {
    101 	u32 reset_emac;
    102 	u32 reset_emacocp;
    103 
    104 	/* hardcode this now */
    105 	switch (of_reset_id) {
    106 	case EMAC0_RESET:
    107 		reset_emac = SOCFPGA_RESET(EMAC0);
    108 		reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
    109 		break;
    110 	case EMAC1_RESET:
    111 		reset_emac = SOCFPGA_RESET(EMAC1);
    112 		reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
    113 		break;
    114 	case EMAC2_RESET:
    115 		reset_emac = SOCFPGA_RESET(EMAC2);
    116 		reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
    117 		break;
    118 	default:
    119 		printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
    120 		hang();
    121 		break;
    122 	}
    123 
    124 	/* Reset ECC OCP first */
    125 	socfpga_per_reset(reset_emacocp, state);
    126 
    127 	/* Release the EMAC controller from reset */
    128 	socfpga_per_reset(reset_emac, state);
    129 }
    130 
    131 /*
    132  * Release peripherals from reset based on handoff
    133  */
    134 void reset_deassert_peripherals_handoff(void)
    135 {
    136 	writel(0, &reset_manager_base->per1modrst);
    137 	/* Enable OCP first */
    138 	writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
    139 	writel(0, &reset_manager_base->per0modrst);
    140 }
    141