1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/mmu.h> 8 9 struct fsl_e_tlb_entry tlb_table[] = { 10 /* TLB 0 - for temp stack in cache */ 11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 12 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 14 0, 0, BOOKE_PAGESZ_4K, 0), 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 /* *I*** - Covers boot page */ 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 32 0, 0, BOOKE_PAGESZ_4K, 1), 33 34 /* *I*G* - CCSRBAR */ 35 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 36 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 37 0, 1, BOOKE_PAGESZ_1M, 1), 38 39 #ifndef CONFIG_SPL_BUILD 40 /* W**G* - Flash, localbus */ 41 /* This will be changed to *I*G* after relocation to RAM. */ 42 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 43 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 44 0, 2, BOOKE_PAGESZ_64M, 1), 45 46 /* W**G* - Flash, localbus */ 47 /* This will be changed to *I*G* after relocation to RAM. */ 48 SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, 49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50 0, 5, BOOKE_PAGESZ_1M, 1), 51 52 #ifdef CONFIG_PCI 53 /* *I*G* - PCI memory 1.5G */ 54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 55 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 56 0, 3, BOOKE_PAGESZ_1G, 1), 57 58 /* *I*G* - PCI I/O effective: 192K */ 59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 60 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 61 0, 4, BOOKE_PAGESZ_256K, 1), 62 #endif 63 64 #endif 65 66 #ifdef CONFIG_SYS_RAMBOOT 67 /* *I*G - eSDHC boot */ 68 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 70 0, 8, BOOKE_PAGESZ_1G, 1), 71 #endif 72 73 }; 74 75 int num_tlb_entries = ARRAY_SIZE(tlb_table); 76
