1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Author: Priyanka Jain <Priyanka.Jain (at) freescale.com> 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <linux/ctype.h> 10 #include <asm/io.h> 11 #include <stdio_dev.h> 12 #include <video_fb.h> 13 #include <fsl_diu_fb.h> 14 #include "../common/qixis.h" 15 #include "../common/diu_ch7301.h" 16 #include "t1040qds.h" 17 #include "t1040qds_qixis.h" 18 19 /* 20 * DIU Area Descriptor 21 * 22 * Note that we need to byte-swap the value before it's written to the AD 23 * register. So even though the registers don't look like they're in the same 24 * bit positions as they are on the MPC8610, the same value is written to the 25 * AD register on the MPC8610 and on the P1022. 26 */ 27 #define AD_BYTE_F 0x10000000 28 #define AD_ALPHA_C_SHIFT 25 29 #define AD_BLUE_C_SHIFT 23 30 #define AD_GREEN_C_SHIFT 21 31 #define AD_RED_C_SHIFT 19 32 #define AD_PIXEL_S_SHIFT 16 33 #define AD_COMP_3_SHIFT 12 34 #define AD_COMP_2_SHIFT 8 35 #define AD_COMP_1_SHIFT 4 36 #define AD_COMP_0_SHIFT 0 37 38 void diu_set_pixel_clock(unsigned int pixclock) 39 { 40 unsigned long speed_ccb, temp; 41 u32 pixval; 42 int ret = 0; 43 speed_ccb = get_bus_freq(0); 44 temp = 1000000000 / pixclock; 45 temp *= 1000; 46 pixval = speed_ccb / temp; 47 48 /* Program HDMI encoder */ 49 /* Switch channel to DIU */ 50 select_i2c_ch_pca9547(I2C_MUX_CH_DIU); 51 52 /* Set dispaly encoder */ 53 ret = diu_set_dvi_encoder(temp); 54 if (ret) { 55 puts("Failed to set DVI encoder\n"); 56 return; 57 } 58 59 /* Switch channel to default */ 60 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 61 62 /* Program pixel clock */ 63 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, 64 ((pixval << PXCK_BITS_START) & PXCK_MASK)); 65 /* enable clock*/ 66 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | 67 ((pixval << PXCK_BITS_START) & PXCK_MASK)); 68 } 69 70 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) 71 { 72 u32 pixel_format; 73 u8 sw; 74 75 /*Route I2C4 to DIU system as HSYNC/VSYNC*/ 76 sw = QIXIS_READ(brdcfg[5]); 77 QIXIS_WRITE(brdcfg[5], 78 ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); 79 80 /*Configure Display ouput port as HDMI*/ 81 sw = QIXIS_READ(brdcfg[15]); 82 QIXIS_WRITE(brdcfg[15], 83 ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) 84 | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); 85 86 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | 87 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | 88 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | 89 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | 90 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); 91 92 printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); 93 94 95 return fsl_diu_init(xres, yres, pixel_format, 0); 96 } 97
