1 /* 2 * rtl8139.c : U-Boot driver for the RealTek RTL8139 3 * 4 * Masami Komiya (mkomiya (at) sonare.it) 5 * 6 * Most part is taken from rtl8139.c of etherboot 7 * 8 */ 9 10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset 11 12 ported from the linux driver written by Donald Becker 13 by Rainer Bawidamann (Rainer.Bawidamann (at) informatik.uni-ulm.de) 1999 14 15 This software may be used and distributed according to the terms 16 of the GNU Public License, incorporated herein by reference. 17 18 changes to the original driver: 19 - removed support for interrupts, switching to polling mode (yuck!) 20 - removed support for the 8129 chip (external MII) 21 22 */ 23 24 /*********************************************************************/ 25 /* Revision History */ 26 /*********************************************************************/ 27 28 /* 29 28 Dec 2002 ken_yap (at) users.sourceforge.net (Ken Yap) 30 Put in virt_to_bus calls to allow Etherboot relocation. 31 32 06 Apr 2001 ken_yap (at) users.sourceforge.net (Ken Yap) 33 Following email from Hyun-Joon Cha, added a disable routine, otherwise 34 NIC remains live and can crash the kernel later. 35 36 4 Feb 2000 espenlaub (at) informatik.uni-ulm.de (Klaus Espenlaub) 37 Shuffled things around, removed the leftovers from the 8129 support 38 that was in the Linux driver and added a bit more 8139 definitions. 39 Moved the 8K receive buffer to a fixed, available address outside the 40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only 41 way to make room for the Etherboot features that need substantial amounts 42 of code like the ANSI console support. Currently the buffer is just below 43 0x10000, so this even conforms to the tagged boot image specification, 44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My 45 interpretation of this "reserved" is that Etherboot may do whatever it 46 likes, as long as its environment is kept intact (like the BIOS 47 variables). Hopefully fixed rtl_poll() once and for all. The symptoms 48 were that if Etherboot was left at the boot menu for several minutes, the 49 first eth_poll failed. Seems like I am the only person who does this. 50 First of all I fixed the debugging code and then set out for a long bug 51 hunting session. It took me about a week full time work - poking around 52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux 53 driver and even the FreeBSD driver (what a piece of crap!) - and 54 eventually spotted the nasty thing: the transmit routine was acknowledging 55 each and every interrupt pending, including the RxOverrun and RxFIFIOver 56 interrupts. This confused the RTL8139 thoroughly. It destroyed the 57 Rx ring contents by dumping the 2K FIFO contents right where we wanted to 58 get the next packet. Oh well, what fun. 59 60 18 Jan 2000 mdc (at) thinguin.org (Marty Connor) 61 Drastically simplified error handling. Basically, if any error 62 in transmission or reception occurs, the card is reset. 63 Also, pointed all transmit descriptors to the same buffer to 64 save buffer space. This should decrease driver size and avoid 65 corruption because of exceeding 32K during runtime. 66 67 28 Jul 1999 (Matthias Meixner - meixner (at) rbg.informatik.tu-darmstadt.de) 68 rtl_poll was quite broken: it used the RxOK interrupt flag instead 69 of the RxBufferEmpty flag which often resulted in very bad 70 transmission performace - below 1kBytes/s. 71 72 */ 73 74 #include <common.h> 75 #include <malloc.h> 76 #include <net.h> 77 #include <netdev.h> 78 #include <asm/io.h> 79 #include <pci.h> 80 81 #define RTL_TIMEOUT 100000 82 83 #define ETH_FRAME_LEN 1514 84 #define ETH_ALEN 6 85 #define ETH_ZLEN 60 86 87 /* PCI Tuning Parameters 88 Threshold is bytes transferred to chip before transmission starts. */ 89 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 90 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ 91 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ 92 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */ 93 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ 94 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */ 95 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ 96 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 97 98 #define DEBUG_TX 0 /* set to 1 to enable debug code */ 99 #define DEBUG_RX 0 /* set to 1 to enable debug code */ 100 101 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 102 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 103 104 /* Symbolic offsets to registers. */ 105 enum RTL8139_registers { 106 MAC0=0, /* Ethernet hardware address. */ 107 MAR0=8, /* Multicast filter. */ 108 TxStatus0=0x10, /* Transmit status (four 32bit registers). */ 109 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ 110 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, 111 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, 112 IntrMask=0x3C, IntrStatus=0x3E, 113 TxConfig=0x40, RxConfig=0x44, 114 Timer=0x48, /* general-purpose counter. */ 115 RxMissed=0x4C, /* 24 bits valid, write clears. */ 116 Cfg9346=0x50, Config0=0x51, Config1=0x52, 117 TimerIntrReg=0x54, /* intr if gp counter reaches this value */ 118 MediaStatus=0x58, 119 Config3=0x59, 120 MultiIntr=0x5C, 121 RevisionID=0x5E, /* revision of the RTL8139 chip */ 122 TxSummary=0x60, 123 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, 124 NWayExpansion=0x6A, 125 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, 126 NWayTestReg=0x70, 127 RxCnt=0x72, /* packet received counter */ 128 CSCR=0x74, /* chip status and configuration register */ 129 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ 130 /* from 0x84 onwards are a number of power management/wakeup frame 131 * definitions we will probably never need to know about. */ 132 }; 133 134 enum ChipCmdBits { 135 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; 136 137 /* Interrupt register bits, using my own meaningful names. */ 138 enum IntrStatusBits { 139 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, 140 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, 141 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, 142 }; 143 enum TxStatusBits { 144 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, 145 TxOutOfWindow=0x20000000, TxAborted=0x40000000, 146 TxCarrierLost=0x80000000, 147 }; 148 enum RxStatusBits { 149 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, 150 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, 151 RxBadAlign=0x0002, RxStatusOK=0x0001, 152 }; 153 154 enum MediaStatusBits { 155 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, 156 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, 157 }; 158 159 enum MIIBMCRBits { 160 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, 161 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, 162 }; 163 164 enum CSCRBits { 165 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, 166 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, 167 CSCR_LinkDownCmd=0x0f3c0, 168 }; 169 170 /* Bits in RxConfig. */ 171 enum rx_mode_bits { 172 RxCfgWrap=0x80, 173 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, 174 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, 175 }; 176 177 static int ioaddr; 178 static unsigned int cur_rx,cur_tx; 179 180 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */ 181 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); 182 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); 183 184 static int rtl8139_probe(struct eth_device *dev, bd_t *bis); 185 static int read_eeprom(int location, int addr_len); 186 static void rtl_reset(struct eth_device *dev); 187 static int rtl_transmit(struct eth_device *dev, void *packet, int length); 188 static int rtl_poll(struct eth_device *dev); 189 static void rtl_disable(struct eth_device *dev); 190 #ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ 191 static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set) 192 { 193 return (0); 194 } 195 #endif 196 197 static struct pci_device_id supported[] = { 198 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, 199 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, 200 {} 201 }; 202 203 int rtl8139_initialize(bd_t *bis) 204 { 205 pci_dev_t devno; 206 int card_number = 0; 207 struct eth_device *dev; 208 u32 iobase; 209 int idx=0; 210 211 while(1){ 212 /* Find RTL8139 */ 213 if ((devno = pci_find_devices(supported, idx++)) < 0) 214 break; 215 216 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 217 iobase &= ~0xf; 218 219 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); 220 221 dev = (struct eth_device *)malloc(sizeof *dev); 222 if (!dev) { 223 printf("Can not allocate memory of rtl8139\n"); 224 break; 225 } 226 memset(dev, 0, sizeof(*dev)); 227 228 sprintf (dev->name, "RTL8139#%d", card_number); 229 230 dev->priv = (void *) devno; 231 dev->iobase = (int)bus_to_phys(iobase); 232 dev->init = rtl8139_probe; 233 dev->halt = rtl_disable; 234 dev->send = rtl_transmit; 235 dev->recv = rtl_poll; 236 #ifdef CONFIG_MCAST_TFTP 237 dev->mcast = rtl_bcast_addr; 238 #endif 239 240 eth_register (dev); 241 242 card_number++; 243 244 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 245 246 udelay (10 * 1000); 247 } 248 249 return card_number; 250 } 251 252 static int rtl8139_probe(struct eth_device *dev, bd_t *bis) 253 { 254 int i; 255 int addr_len; 256 unsigned short *ap = (unsigned short *)dev->enetaddr; 257 258 ioaddr = dev->iobase; 259 260 /* Bring the chip out of low-power mode. */ 261 outb(0x00, ioaddr + Config1); 262 263 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; 264 for (i = 0; i < 3; i++) 265 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len)); 266 267 rtl_reset(dev); 268 269 if (inb(ioaddr + MediaStatus) & MSRLinkFail) { 270 printf("Cable not connected or other link failure\n"); 271 return -1 ; 272 } 273 274 return 0; 275 } 276 277 /* Serial EEPROM section. */ 278 279 /* EEPROM_Ctrl bits. */ 280 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 281 #define EE_CS 0x08 /* EEPROM chip select. */ 282 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 283 #define EE_WRITE_0 0x00 284 #define EE_WRITE_1 0x02 285 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 286 #define EE_ENB (0x80 | EE_CS) 287 288 /* 289 Delay between EEPROM clock transitions. 290 No extra delay is needed with 33MHz PCI, but 66MHz may change this. 291 */ 292 293 #define eeprom_delay() inl(ee_addr) 294 295 /* The EEPROM commands include the alway-set leading bit. */ 296 #define EE_WRITE_CMD (5) 297 #define EE_READ_CMD (6) 298 #define EE_ERASE_CMD (7) 299 300 static int read_eeprom(int location, int addr_len) 301 { 302 int i; 303 unsigned int retval = 0; 304 long ee_addr = ioaddr + Cfg9346; 305 int read_cmd = location | (EE_READ_CMD << addr_len); 306 307 outb(EE_ENB & ~EE_CS, ee_addr); 308 outb(EE_ENB, ee_addr); 309 eeprom_delay(); 310 311 /* Shift the read command bits out. */ 312 for (i = 4 + addr_len; i >= 0; i--) { 313 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 314 outb(EE_ENB | dataval, ee_addr); 315 eeprom_delay(); 316 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 317 eeprom_delay(); 318 } 319 outb(EE_ENB, ee_addr); 320 eeprom_delay(); 321 322 for (i = 16; i > 0; i--) { 323 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); 324 eeprom_delay(); 325 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); 326 outb(EE_ENB, ee_addr); 327 eeprom_delay(); 328 } 329 330 /* Terminate the EEPROM access. */ 331 outb(~EE_CS, ee_addr); 332 eeprom_delay(); 333 return retval; 334 } 335 336 static const unsigned int rtl8139_rx_config = 337 (RX_BUF_LEN_IDX << 11) | 338 (RX_FIFO_THRESH << 13) | 339 (RX_DMA_BURST << 8); 340 341 static void set_rx_mode(struct eth_device *dev) { 342 unsigned int mc_filter[2]; 343 int rx_mode; 344 /* !IFF_PROMISC */ 345 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 346 mc_filter[1] = mc_filter[0] = 0xffffffff; 347 348 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); 349 350 outl(mc_filter[0], ioaddr + MAR0 + 0); 351 outl(mc_filter[1], ioaddr + MAR0 + 4); 352 } 353 354 static void rtl_reset(struct eth_device *dev) 355 { 356 int i; 357 358 outb(CmdReset, ioaddr + ChipCmd); 359 360 cur_rx = 0; 361 cur_tx = 0; 362 363 /* Give the chip 10ms to finish the reset. */ 364 for (i=0; i<100; ++i){ 365 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; 366 udelay (100); /* wait 100us */ 367 } 368 369 370 for (i = 0; i < ETH_ALEN; i++) 371 outb(dev->enetaddr[i], ioaddr + MAC0 + i); 372 373 /* Must enable Tx/Rx before setting transfer thresholds! */ 374 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); 375 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), 376 ioaddr + RxConfig); /* accept no frames yet! */ 377 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); 378 379 /* The Linux driver changes Config1 here to use a different LED pattern 380 * for half duplex or full/autodetect duplex (for full/autodetect, the 381 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses 382 * TX/RX, Link100, Link10). This is messy, because it doesn't match 383 * the inscription on the mounting bracket. It should not be changed 384 * from the configuration EEPROM default, because the card manufacturer 385 * should have set that to match the card. */ 386 387 debug_cond(DEBUG_RX, 388 "rx ring address is %lX\n",(unsigned long)rx_ring); 389 flush_cache((unsigned long)rx_ring, RX_BUF_LEN); 390 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); 391 392 /* If we add multicast support, the MAR0 register would have to be 393 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot 394 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ 395 396 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); 397 398 outl(rtl8139_rx_config, ioaddr + RxConfig); 399 400 /* Start the chip's Tx and Rx process. */ 401 outl(0, ioaddr + RxMissed); 402 403 /* set_rx_mode */ 404 set_rx_mode(dev); 405 406 /* Disable all known interrupts by setting the interrupt mask. */ 407 outw(0, ioaddr + IntrMask); 408 } 409 410 static int rtl_transmit(struct eth_device *dev, void *packet, int length) 411 { 412 unsigned int status; 413 unsigned long txstatus; 414 unsigned int len = length; 415 int i = 0; 416 417 ioaddr = dev->iobase; 418 419 memcpy((char *)tx_buffer, (char *)packet, (int)length); 420 421 debug_cond(DEBUG_TX, "sending %d bytes\n", len); 422 423 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 424 * bytes are sent automatically for the FCS, totalling to 64 bytes). */ 425 while (len < ETH_ZLEN) { 426 tx_buffer[len++] = '\0'; 427 } 428 429 flush_cache((unsigned long)tx_buffer, length); 430 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); 431 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, 432 ioaddr + TxStatus0 + cur_tx*4); 433 434 do { 435 status = inw(ioaddr + IntrStatus); 436 /* Only acknlowledge interrupt sources we can properly handle 437 * here - the RxOverflow/RxFIFOOver MUST be handled in the 438 * rtl_poll() function. */ 439 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); 440 if ((status & (TxOK | TxErr | PCIErr)) != 0) break; 441 udelay(10); 442 } while (i++ < RTL_TIMEOUT); 443 444 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); 445 446 if (status & TxOK) { 447 cur_tx = (cur_tx + 1) % NUM_TX_DESC; 448 449 debug_cond(DEBUG_TX, 450 "tx done, status %hX txstatus %lX\n", 451 status, txstatus); 452 453 return length; 454 } else { 455 456 debug_cond(DEBUG_TX, 457 "tx timeout/error (%d usecs), status %hX txstatus %lX\n", 458 10*i, status, txstatus); 459 460 rtl_reset(dev); 461 462 return 0; 463 } 464 } 465 466 static int rtl_poll(struct eth_device *dev) 467 { 468 unsigned int status; 469 unsigned int ring_offs; 470 unsigned int rx_size, rx_status; 471 int length=0; 472 473 ioaddr = dev->iobase; 474 475 if (inb(ioaddr + ChipCmd) & RxBufEmpty) { 476 return 0; 477 } 478 479 status = inw(ioaddr + IntrStatus); 480 /* See below for the rest of the interrupt acknowledges. */ 481 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); 482 483 debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status); 484 485 ring_offs = cur_rx % RX_BUF_LEN; 486 /* ring_offs is guaranteed being 4-byte aligned */ 487 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs)); 488 rx_size = rx_status >> 16; 489 rx_status &= 0xffff; 490 491 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || 492 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { 493 printf("rx error %hX\n", rx_status); 494 rtl_reset(dev); /* this clears all interrupts still pending */ 495 return 0; 496 } 497 498 /* Received a good packet */ 499 length = rx_size - 4; /* no one cares about the FCS */ 500 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { 501 int semi_count = RX_BUF_LEN - ring_offs - 4; 502 unsigned char rxdata[RX_BUF_LEN]; 503 504 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); 505 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count); 506 507 net_process_received_packet(rxdata, length); 508 debug_cond(DEBUG_RX, "rx packet %d+%d bytes", 509 semi_count, rx_size-4-semi_count); 510 } else { 511 net_process_received_packet(rx_ring + ring_offs + 4, length); 512 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4); 513 } 514 flush_cache((unsigned long)rx_ring, RX_BUF_LEN); 515 516 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 517 outw(cur_rx - 16, ioaddr + RxBufPtr); 518 /* See RTL8139 Programming Guide V0.1 for the official handling of 519 * Rx overflow situations. The document itself contains basically no 520 * usable information, except for a few exception handling rules. */ 521 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); 522 return length; 523 } 524 525 static void rtl_disable(struct eth_device *dev) 526 { 527 int i; 528 529 ioaddr = dev->iobase; 530 531 /* reset the chip */ 532 outb(CmdReset, ioaddr + ChipCmd); 533 534 /* Give the chip 10ms to finish the reset. */ 535 for (i=0; i<100; ++i){ 536 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; 537 udelay (100); /* wait 100us */ 538 } 539 } 540
