1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * sunxi_emac.c -- Allwinner A10 ethernet driver 4 * 5 * (C) Copyright 2012, Stefan Roese <sr (at) denx.de> 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <linux/err.h> 11 #include <malloc.h> 12 #include <miiphy.h> 13 #include <net.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/gpio.h> 17 18 /* EMAC register */ 19 struct emac_regs { 20 u32 ctl; /* 0x00 */ 21 u32 tx_mode; /* 0x04 */ 22 u32 tx_flow; /* 0x08 */ 23 u32 tx_ctl0; /* 0x0c */ 24 u32 tx_ctl1; /* 0x10 */ 25 u32 tx_ins; /* 0x14 */ 26 u32 tx_pl0; /* 0x18 */ 27 u32 tx_pl1; /* 0x1c */ 28 u32 tx_sta; /* 0x20 */ 29 u32 tx_io_data; /* 0x24 */ 30 u32 tx_io_data1;/* 0x28 */ 31 u32 tx_tsvl0; /* 0x2c */ 32 u32 tx_tsvh0; /* 0x30 */ 33 u32 tx_tsvl1; /* 0x34 */ 34 u32 tx_tsvh1; /* 0x38 */ 35 u32 rx_ctl; /* 0x3c */ 36 u32 rx_hash0; /* 0x40 */ 37 u32 rx_hash1; /* 0x44 */ 38 u32 rx_sta; /* 0x48 */ 39 u32 rx_io_data; /* 0x4c */ 40 u32 rx_fbc; /* 0x50 */ 41 u32 int_ctl; /* 0x54 */ 42 u32 int_sta; /* 0x58 */ 43 u32 mac_ctl0; /* 0x5c */ 44 u32 mac_ctl1; /* 0x60 */ 45 u32 mac_ipgt; /* 0x64 */ 46 u32 mac_ipgr; /* 0x68 */ 47 u32 mac_clrt; /* 0x6c */ 48 u32 mac_maxf; /* 0x70 */ 49 u32 mac_supp; /* 0x74 */ 50 u32 mac_test; /* 0x78 */ 51 u32 mac_mcfg; /* 0x7c */ 52 u32 mac_mcmd; /* 0x80 */ 53 u32 mac_madr; /* 0x84 */ 54 u32 mac_mwtd; /* 0x88 */ 55 u32 mac_mrdd; /* 0x8c */ 56 u32 mac_mind; /* 0x90 */ 57 u32 mac_ssrr; /* 0x94 */ 58 u32 mac_a0; /* 0x98 */ 59 u32 mac_a1; /* 0x9c */ 60 }; 61 62 /* SRAMC register */ 63 struct sunxi_sramc_regs { 64 u32 ctrl0; 65 u32 ctrl1; 66 }; 67 68 /* 0: Disable 1: Aborted frame enable(default) */ 69 #define EMAC_TX_AB_M (0x1 << 0) 70 /* 0: CPU 1: DMA(default) */ 71 #define EMAC_TX_TM (0x1 << 1) 72 73 #define EMAC_TX_SETUP (0) 74 75 /* 0: DRQ asserted 1: DRQ automatically(default) */ 76 #define EMAC_RX_DRQ_MODE (0x1 << 1) 77 /* 0: CPU 1: DMA(default) */ 78 #define EMAC_RX_TM (0x1 << 2) 79 /* 0: Normal(default) 1: Pass all Frames */ 80 #define EMAC_RX_PA (0x1 << 4) 81 /* 0: Normal(default) 1: Pass Control Frames */ 82 #define EMAC_RX_PCF (0x1 << 5) 83 /* 0: Normal(default) 1: Pass Frames with CRC Error */ 84 #define EMAC_RX_PCRCE (0x1 << 6) 85 /* 0: Normal(default) 1: Pass Frames with Length Error */ 86 #define EMAC_RX_PLE (0x1 << 7) 87 /* 0: Normal 1: Pass Frames length out of range(default) */ 88 #define EMAC_RX_POR (0x1 << 8) 89 /* 0: Not accept 1: Accept unicast Packets(default) */ 90 #define EMAC_RX_UCAD (0x1 << 16) 91 /* 0: Normal(default) 1: DA Filtering */ 92 #define EMAC_RX_DAF (0x1 << 17) 93 /* 0: Not accept 1: Accept multicast Packets(default) */ 94 #define EMAC_RX_MCO (0x1 << 20) 95 /* 0: Disable(default) 1: Enable Hash filter */ 96 #define EMAC_RX_MHF (0x1 << 21) 97 /* 0: Not accept 1: Accept Broadcast Packets(default) */ 98 #define EMAC_RX_BCO (0x1 << 22) 99 /* 0: Disable(default) 1: Enable SA Filtering */ 100 #define EMAC_RX_SAF (0x1 << 24) 101 /* 0: Normal(default) 1: Inverse Filtering */ 102 #define EMAC_RX_SAIF (0x1 << 25) 103 104 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ 105 EMAC_RX_MCO | EMAC_RX_BCO) 106 107 /* 0: Disable 1: Enable Receive Flow Control(default) */ 108 #define EMAC_MAC_CTL0_RFC (0x1 << 2) 109 /* 0: Disable 1: Enable Transmit Flow Control(default) */ 110 #define EMAC_MAC_CTL0_TFC (0x1 << 3) 111 112 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) 113 114 /* 0: Disable 1: Enable MAC Frame Length Checking(default) */ 115 #define EMAC_MAC_CTL1_FLC (0x1 << 1) 116 /* 0: Disable(default) 1: Enable Huge Frame */ 117 #define EMAC_MAC_CTL1_HF (0x1 << 2) 118 /* 0: Disable(default) 1: Enable MAC Delayed CRC */ 119 #define EMAC_MAC_CTL1_DCRC (0x1 << 3) 120 /* 0: Disable 1: Enable MAC CRC(default) */ 121 #define EMAC_MAC_CTL1_CRC (0x1 << 4) 122 /* 0: Disable 1: Enable MAC PAD Short frames(default) */ 123 #define EMAC_MAC_CTL1_PC (0x1 << 5) 124 /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ 125 #define EMAC_MAC_CTL1_VC (0x1 << 6) 126 /* 0: Disable(default) 1: Enable MAC auto detect Short frames */ 127 #define EMAC_MAC_CTL1_ADP (0x1 << 7) 128 /* 0: Disable(default) 1: Enable */ 129 #define EMAC_MAC_CTL1_PRE (0x1 << 8) 130 /* 0: Disable(default) 1: Enable */ 131 #define EMAC_MAC_CTL1_LPE (0x1 << 9) 132 /* 0: Disable(default) 1: Enable no back off */ 133 #define EMAC_MAC_CTL1_NB (0x1 << 12) 134 /* 0: Disable(default) 1: Enable */ 135 #define EMAC_MAC_CTL1_BNB (0x1 << 13) 136 /* 0: Disable(default) 1: Enable */ 137 #define EMAC_MAC_CTL1_ED (0x1 << 14) 138 139 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ 140 EMAC_MAC_CTL1_PC) 141 142 #define EMAC_MAC_IPGT 0x15 143 144 #define EMAC_MAC_NBTB_IPG1 0xc 145 #define EMAC_MAC_NBTB_IPG2 0x12 146 147 #define EMAC_MAC_CW 0x37 148 #define EMAC_MAC_RM 0xf 149 150 #define EMAC_MAC_MFL 0x0600 151 152 /* Receive status */ 153 #define EMAC_CRCERR (0x1 << 4) 154 #define EMAC_LENERR (0x3 << 5) 155 156 #define EMAC_RX_BUFSIZE 2000 157 158 struct emac_eth_dev { 159 struct emac_regs *regs; 160 struct mii_dev *bus; 161 struct phy_device *phydev; 162 int link_printed; 163 #ifdef CONFIG_DM_ETH 164 uchar rx_buf[EMAC_RX_BUFSIZE]; 165 #endif 166 }; 167 168 struct emac_rxhdr { 169 s16 rx_len; 170 u16 rx_status; 171 }; 172 173 static void emac_inblk_32bit(void *reg, void *data, int count) 174 { 175 int cnt = (count + 3) >> 2; 176 177 if (cnt) { 178 u32 *buf = data; 179 180 do { 181 u32 x = readl(reg); 182 *buf++ = x; 183 } while (--cnt); 184 } 185 } 186 187 static void emac_outblk_32bit(void *reg, void *data, int count) 188 { 189 int cnt = (count + 3) >> 2; 190 191 if (cnt) { 192 const u32 *buf = data; 193 194 do { 195 writel(*buf++, reg); 196 } while (--cnt); 197 } 198 } 199 200 /* Read a word from phyxcer */ 201 static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 202 { 203 struct emac_eth_dev *priv = bus->priv; 204 struct emac_regs *regs = priv->regs; 205 206 /* issue the phy address and reg */ 207 writel(addr << 8 | reg, ®s->mac_madr); 208 209 /* pull up the phy io line */ 210 writel(0x1, ®s->mac_mcmd); 211 212 /* Wait read complete */ 213 mdelay(1); 214 215 /* push down the phy io line */ 216 writel(0x0, ®s->mac_mcmd); 217 218 /* And read data */ 219 return readl(®s->mac_mrdd); 220 } 221 222 /* Write a word to phyxcer */ 223 static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 224 u16 value) 225 { 226 struct emac_eth_dev *priv = bus->priv; 227 struct emac_regs *regs = priv->regs; 228 229 /* issue the phy address and reg */ 230 writel(addr << 8 | reg, ®s->mac_madr); 231 232 /* pull up the phy io line */ 233 writel(0x1, ®s->mac_mcmd); 234 235 /* Wait write complete */ 236 mdelay(1); 237 238 /* push down the phy io line */ 239 writel(0x0, ®s->mac_mcmd); 240 241 /* and write data */ 242 writel(value, ®s->mac_mwtd); 243 244 return 0; 245 } 246 247 static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) 248 { 249 int ret, mask = 0xffffffff; 250 251 #ifdef CONFIG_PHY_ADDR 252 mask = 1 << CONFIG_PHY_ADDR; 253 #endif 254 255 priv->bus = mdio_alloc(); 256 if (!priv->bus) { 257 printf("Failed to allocate MDIO bus\n"); 258 return -ENOMEM; 259 } 260 261 priv->bus->read = emac_mdio_read; 262 priv->bus->write = emac_mdio_write; 263 priv->bus->priv = priv; 264 strcpy(priv->bus->name, "emac"); 265 266 ret = mdio_register(priv->bus); 267 if (ret) 268 return ret; 269 270 priv->phydev = phy_find_by_mask(priv->bus, mask, 271 PHY_INTERFACE_MODE_MII); 272 if (!priv->phydev) 273 return -ENODEV; 274 275 phy_connect_dev(priv->phydev, dev); 276 phy_config(priv->phydev); 277 278 return 0; 279 } 280 281 static void emac_setup(struct emac_eth_dev *priv) 282 { 283 struct emac_regs *regs = priv->regs; 284 u32 reg_val; 285 286 /* Set up TX */ 287 writel(EMAC_TX_SETUP, ®s->tx_mode); 288 289 /* Set up RX */ 290 writel(EMAC_RX_SETUP, ®s->rx_ctl); 291 292 /* Set MAC */ 293 /* Set MAC CTL0 */ 294 writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); 295 296 /* Set MAC CTL1 */ 297 reg_val = 0; 298 if (priv->phydev->duplex == DUPLEX_FULL) 299 reg_val = (0x1 << 0); 300 writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); 301 302 /* Set up IPGT */ 303 writel(EMAC_MAC_IPGT, ®s->mac_ipgt); 304 305 /* Set up IPGR */ 306 writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); 307 308 /* Set up Collison window */ 309 writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); 310 311 /* Set up Max Frame Length */ 312 writel(EMAC_MAC_MFL, ®s->mac_maxf); 313 } 314 315 static void emac_reset(struct emac_eth_dev *priv) 316 { 317 struct emac_regs *regs = priv->regs; 318 319 debug("resetting device\n"); 320 321 /* RESET device */ 322 writel(0, ®s->ctl); 323 udelay(200); 324 325 writel(1, ®s->ctl); 326 udelay(200); 327 } 328 329 static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr) 330 { 331 struct emac_regs *regs = priv->regs; 332 u32 enetaddr_lo, enetaddr_hi; 333 334 enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16); 335 enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16); 336 337 writel(enetaddr_hi, ®s->mac_a0); 338 writel(enetaddr_lo, ®s->mac_a1); 339 340 return 0; 341 } 342 343 static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) 344 { 345 struct emac_regs *regs = priv->regs; 346 int ret; 347 348 /* Init EMAC */ 349 350 /* Flush RX FIFO */ 351 setbits_le32(®s->rx_ctl, 0x8); 352 udelay(1); 353 354 /* Init MAC */ 355 356 /* Soft reset MAC */ 357 clrbits_le32(®s->mac_ctl0, 0x1 << 15); 358 359 /* Clear RX counter */ 360 writel(0x0, ®s->rx_fbc); 361 udelay(1); 362 363 /* Set up EMAC */ 364 emac_setup(priv); 365 366 _sunxi_write_hwaddr(priv, enetaddr); 367 368 mdelay(1); 369 370 emac_reset(priv); 371 372 /* PHY POWER UP */ 373 ret = phy_startup(priv->phydev); 374 if (ret) { 375 printf("Could not initialize PHY %s\n", 376 priv->phydev->dev->name); 377 return ret; 378 } 379 380 /* Print link status only once */ 381 if (!priv->link_printed) { 382 printf("ENET Speed is %d Mbps - %s duplex connection\n", 383 priv->phydev->speed, 384 priv->phydev->duplex ? "FULL" : "HALF"); 385 priv->link_printed = 1; 386 } 387 388 /* Set EMAC SPEED depend on PHY */ 389 if (priv->phydev->speed == SPEED_100) 390 setbits_le32(®s->mac_supp, 1 << 8); 391 else 392 clrbits_le32(®s->mac_supp, 1 << 8); 393 394 /* Set duplex depend on phy */ 395 if (priv->phydev->duplex == DUPLEX_FULL) 396 setbits_le32(®s->mac_ctl1, 1 << 0); 397 else 398 clrbits_le32(®s->mac_ctl1, 1 << 0); 399 400 /* Enable RX/TX */ 401 setbits_le32(®s->ctl, 0x7); 402 403 return 0; 404 } 405 406 static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet) 407 { 408 struct emac_regs *regs = priv->regs; 409 struct emac_rxhdr rxhdr; 410 u32 rxcount; 411 u32 reg_val; 412 int rx_len; 413 int rx_status; 414 int good_packet; 415 416 /* Check packet ready or not */ 417 418 /* Race warning: The first packet might arrive with 419 * the interrupts disabled, but the second will fix 420 */ 421 rxcount = readl(®s->rx_fbc); 422 if (!rxcount) { 423 /* Had one stuck? */ 424 rxcount = readl(®s->rx_fbc); 425 if (!rxcount) 426 return -EAGAIN; 427 } 428 429 reg_val = readl(®s->rx_io_data); 430 if (reg_val != 0x0143414d) { 431 /* Disable RX */ 432 clrbits_le32(®s->ctl, 0x1 << 2); 433 434 /* Flush RX FIFO */ 435 setbits_le32(®s->rx_ctl, 0x1 << 3); 436 while (readl(®s->rx_ctl) & (0x1 << 3)) 437 ; 438 439 /* Enable RX */ 440 setbits_le32(®s->ctl, 0x1 << 2); 441 442 return -EAGAIN; 443 } 444 445 /* A packet ready now 446 * Get status/length 447 */ 448 good_packet = 1; 449 450 emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); 451 452 rx_len = rxhdr.rx_len; 453 rx_status = rxhdr.rx_status; 454 455 /* Packet Status check */ 456 if (rx_len < 0x40) { 457 good_packet = 0; 458 debug("RX: Bad Packet (runt)\n"); 459 } 460 461 /* rx_status is identical to RSR register. */ 462 if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { 463 good_packet = 0; 464 if (rx_status & EMAC_CRCERR) 465 printf("crc error\n"); 466 if (rx_status & EMAC_LENERR) 467 printf("length error\n"); 468 } 469 470 /* Move data from EMAC */ 471 if (good_packet) { 472 if (rx_len > EMAC_RX_BUFSIZE) { 473 printf("Received packet is too big (len=%d)\n", rx_len); 474 return -EMSGSIZE; 475 } 476 emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len); 477 return rx_len; 478 } 479 480 return -EIO; /* Bad packet */ 481 } 482 483 static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet, 484 int len) 485 { 486 struct emac_regs *regs = priv->regs; 487 488 /* Select channel 0 */ 489 writel(0, ®s->tx_ins); 490 491 /* Write packet */ 492 emac_outblk_32bit((void *)®s->tx_io_data, packet, len); 493 494 /* Set TX len */ 495 writel(len, ®s->tx_pl0); 496 497 /* Start translate from fifo to phy */ 498 setbits_le32(®s->tx_ctl0, 1); 499 500 return 0; 501 } 502 503 static void sunxi_emac_board_setup(struct emac_eth_dev *priv) 504 { 505 struct sunxi_ccm_reg *const ccm = 506 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 507 struct sunxi_sramc_regs *sram = 508 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; 509 struct emac_regs *regs = priv->regs; 510 int pin; 511 512 /* Map SRAM to EMAC */ 513 setbits_le32(&sram->ctrl1, 0x5 << 2); 514 515 /* Configure pin mux settings for MII Ethernet */ 516 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) 517 sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); 518 519 /* Set up clock gating */ 520 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); 521 522 /* Set MII clock */ 523 clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); 524 } 525 526 static int sunxi_emac_eth_start(struct udevice *dev) 527 { 528 struct eth_pdata *pdata = dev_get_platdata(dev); 529 530 return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr); 531 } 532 533 static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length) 534 { 535 struct emac_eth_dev *priv = dev_get_priv(dev); 536 537 return _sunxi_emac_eth_send(priv, packet, length); 538 } 539 540 static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) 541 { 542 struct emac_eth_dev *priv = dev_get_priv(dev); 543 int rx_len; 544 545 rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf); 546 *packetp = priv->rx_buf; 547 548 return rx_len; 549 } 550 551 static void sunxi_emac_eth_stop(struct udevice *dev) 552 { 553 /* Nothing to do here */ 554 } 555 556 static int sunxi_emac_eth_probe(struct udevice *dev) 557 { 558 struct eth_pdata *pdata = dev_get_platdata(dev); 559 struct emac_eth_dev *priv = dev_get_priv(dev); 560 561 priv->regs = (struct emac_regs *)pdata->iobase; 562 sunxi_emac_board_setup(priv); 563 564 return sunxi_emac_init_phy(priv, dev); 565 } 566 567 static const struct eth_ops sunxi_emac_eth_ops = { 568 .start = sunxi_emac_eth_start, 569 .send = sunxi_emac_eth_send, 570 .recv = sunxi_emac_eth_recv, 571 .stop = sunxi_emac_eth_stop, 572 }; 573 574 static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev) 575 { 576 struct eth_pdata *pdata = dev_get_platdata(dev); 577 578 pdata->iobase = devfdt_get_addr(dev); 579 580 return 0; 581 } 582 583 static const struct udevice_id sunxi_emac_eth_ids[] = { 584 { .compatible = "allwinner,sun4i-a10-emac" }, 585 { } 586 }; 587 588 U_BOOT_DRIVER(eth_sunxi_emac) = { 589 .name = "eth_sunxi_emac", 590 .id = UCLASS_ETH, 591 .of_match = sunxi_emac_eth_ids, 592 .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata, 593 .probe = sunxi_emac_eth_probe, 594 .ops = &sunxi_emac_eth_ops, 595 .priv_auto_alloc_size = sizeof(struct emac_eth_dev), 596 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 597 }; 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