1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2009 Daniel Mack <daniel (at) caiaq.de> 4 */ 5 6 7 #include <common.h> 8 #include <usb.h> 9 #include <asm/io.h> 10 #include <asm/arch/imx-regs.h> 11 #include <usb/ehci-ci.h> 12 #include <errno.h> 13 14 #include "ehci.h" 15 16 #define USBCTRL_OTGBASE_OFFSET 0x600 17 18 #define MX25_OTG_SIC_SHIFT 29 19 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) 20 #define MX25_OTG_PM_BIT (1 << 24) 21 #define MX25_OTG_PP_BIT (1 << 11) 22 #define MX25_OTG_OCPOL_BIT (1 << 3) 23 24 #define MX25_H1_SIC_SHIFT 21 25 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) 26 #define MX25_H1_PP_BIT (1 << 18) 27 #define MX25_H1_PM_BIT (1 << 16) 28 #define MX25_H1_IPPUE_UP_BIT (1 << 7) 29 #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) 30 #define MX25_H1_TLL_BIT (1 << 5) 31 #define MX25_H1_USBTE_BIT (1 << 4) 32 #define MX25_H1_OCPOL_BIT (1 << 2) 33 34 #define MX31_OTG_SIC_SHIFT 29 35 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) 36 #define MX31_OTG_PM_BIT (1 << 24) 37 38 #define MX31_H2_SIC_SHIFT 21 39 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) 40 #define MX31_H2_PM_BIT (1 << 16) 41 #define MX31_H2_DT_BIT (1 << 5) 42 43 #define MX31_H1_SIC_SHIFT 13 44 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) 45 #define MX31_H1_PM_BIT (1 << 8) 46 #define MX31_H1_DT_BIT (1 << 4) 47 48 #define MX35_OTG_SIC_SHIFT 29 49 #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) 50 #define MX35_OTG_PM_BIT (1 << 24) 51 #define MX35_OTG_PP_BIT (1 << 11) 52 #define MX35_OTG_OCPOL_BIT (1 << 3) 53 54 #define MX35_H1_SIC_SHIFT 21 55 #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) 56 #define MX35_H1_PP_BIT (1 << 18) 57 #define MX35_H1_PM_BIT (1 << 16) 58 #define MX35_H1_IPPUE_UP_BIT (1 << 7) 59 #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) 60 #define MX35_H1_TLL_BIT (1 << 5) 61 #define MX35_H1_USBTE_BIT (1 << 4) 62 #define MX35_H1_OCPOL_BIT (1 << 2) 63 64 static int mxc_set_usbcontrol(int port, unsigned int flags) 65 { 66 unsigned int v; 67 68 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 69 #if defined(CONFIG_MX25) 70 switch (port) { 71 case 0: /* OTG port */ 72 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | 73 MX25_OTG_OCPOL_BIT); 74 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; 75 76 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 77 v |= MX25_OTG_PM_BIT; 78 79 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 80 v |= MX25_OTG_PP_BIT; 81 82 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 83 v |= MX25_OTG_OCPOL_BIT; 84 85 break; 86 case 1: /* H1 port */ 87 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | 88 MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | 89 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | 90 MX25_H1_IPPUE_UP_BIT); 91 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; 92 93 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 94 v |= MX25_H1_PM_BIT; 95 96 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 97 v |= MX25_H1_PP_BIT; 98 99 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 100 v |= MX25_H1_OCPOL_BIT; 101 102 if (!(flags & MXC_EHCI_TTL_ENABLED)) 103 v |= MX25_H1_TLL_BIT; 104 105 if (flags & MXC_EHCI_INTERNAL_PHY) 106 v |= MX25_H1_USBTE_BIT; 107 108 if (flags & MXC_EHCI_IPPUE_DOWN) 109 v |= MX25_H1_IPPUE_DOWN_BIT; 110 111 if (flags & MXC_EHCI_IPPUE_UP) 112 v |= MX25_H1_IPPUE_UP_BIT; 113 114 break; 115 default: 116 return -EINVAL; 117 } 118 #elif defined(CONFIG_MX31) 119 switch (port) { 120 case 0: /* OTG port */ 121 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 122 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; 123 124 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 125 v |= MX31_OTG_PM_BIT; 126 127 break; 128 case 1: /* H1 port */ 129 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); 130 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; 131 132 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 133 v |= MX31_H1_PM_BIT; 134 135 if (!(flags & MXC_EHCI_TTL_ENABLED)) 136 v |= MX31_H1_DT_BIT; 137 138 break; 139 case 2: /* H2 port */ 140 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); 141 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; 142 143 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 144 v |= MX31_H2_PM_BIT; 145 146 if (!(flags & MXC_EHCI_TTL_ENABLED)) 147 v |= MX31_H2_DT_BIT; 148 149 break; 150 default: 151 return -EINVAL; 152 } 153 #elif defined(CONFIG_MX35) 154 switch (port) { 155 case 0: /* OTG port */ 156 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | 157 MX35_OTG_OCPOL_BIT); 158 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; 159 160 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 161 v |= MX35_OTG_PM_BIT; 162 163 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 164 v |= MX35_OTG_PP_BIT; 165 166 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 167 v |= MX35_OTG_OCPOL_BIT; 168 169 break; 170 case 1: /* H1 port */ 171 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | 172 MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | 173 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | 174 MX35_H1_IPPUE_UP_BIT); 175 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; 176 177 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 178 v |= MX35_H1_PM_BIT; 179 180 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 181 v |= MX35_H1_PP_BIT; 182 183 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 184 v |= MX35_H1_OCPOL_BIT; 185 186 if (!(flags & MXC_EHCI_TTL_ENABLED)) 187 v |= MX35_H1_TLL_BIT; 188 189 if (flags & MXC_EHCI_INTERNAL_PHY) 190 v |= MX35_H1_USBTE_BIT; 191 192 if (flags & MXC_EHCI_IPPUE_DOWN) 193 v |= MX35_H1_IPPUE_DOWN_BIT; 194 195 if (flags & MXC_EHCI_IPPUE_UP) 196 v |= MX35_H1_IPPUE_UP_BIT; 197 198 break; 199 default: 200 return -EINVAL; 201 } 202 #else 203 #error MXC EHCI USB driver not supported on this platform 204 #endif 205 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 206 207 return 0; 208 } 209 210 int ehci_hcd_init(int index, enum usb_init_type init, 211 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 212 { 213 struct usb_ehci *ehci; 214 #ifdef CONFIG_MX31 215 struct clock_control_regs *sc_regs = 216 (struct clock_control_regs *)CCM_BASE; 217 218 __raw_readl(&sc_regs->ccmr); 219 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; 220 #endif 221 222 udelay(80); 223 224 ehci = (struct usb_ehci *)(IMX_USB_BASE + 225 IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); 226 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 227 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 228 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 229 setbits_le32(&ehci->usbmode, CM_HOST); 230 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 231 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 232 #ifdef CONFIG_MX35 233 /* Workaround for ENGcm11601 */ 234 __raw_writel(0, &ehci->sbuscfg); 235 #endif 236 237 udelay(10000); 238 239 return 0; 240 } 241 242 /* 243 * Destroy the appropriate control structures corresponding 244 * the the EHCI host controller. 245 */ 246 int ehci_hcd_stop(int index) 247 { 248 return 0; 249 } 250
