1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2015 Sanchayan Maity <sanchayan.maity (at) toradex.com> 4 * Copyright (C) 2015 Toradex AG 5 * 6 * Based on ehci-mx6 driver 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <usb.h> 12 #include <errno.h> 13 #include <linux/compiler.h> 14 #include <asm/io.h> 15 #include <asm-generic/gpio.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/imx-regs.h> 18 #include <asm/arch/crm_regs.h> 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <asm/mach-imx/regs-usbphy.h> 21 #include <usb/ehci-ci.h> 22 #include <linux/libfdt.h> 23 #include <fdtdec.h> 24 25 #include "ehci.h" 26 27 #define USB_NC_REG_OFFSET 0x00000800 28 29 #define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6) 30 31 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ 32 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ 33 34 /* USBCMD */ 35 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ 36 #define UCMD_RESET (1 << 1) /* controller reset */ 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 static const unsigned phy_bases[] = { 41 USB_PHY0_BASE_ADDR, 42 USB_PHY1_BASE_ADDR, 43 }; 44 45 static const unsigned nc_reg_bases[] = { 46 USBC0_BASE_ADDR, 47 USBC1_BASE_ADDR, 48 }; 49 50 static void usb_internal_phy_clock_gate(int index) 51 { 52 void __iomem *phy_reg; 53 54 phy_reg = (void __iomem *)phy_bases[index]; 55 clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE); 56 } 57 58 static void usb_power_config(int index) 59 { 60 struct anadig_reg __iomem *anadig = 61 (struct anadig_reg __iomem *)ANADIG_BASE_ADDR; 62 void __iomem *pll_ctrl; 63 64 switch (index) { 65 case 0: 66 pll_ctrl = &anadig->pll3_ctrl; 67 clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS); 68 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE 69 | ANADIG_PLL3_CTRL_POWERDOWN 70 | ANADIG_PLL_CTRL_EN_USB_CLKS); 71 break; 72 case 1: 73 pll_ctrl = &anadig->pll7_ctrl; 74 clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS); 75 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE 76 | ANADIG_PLL7_CTRL_POWERDOWN 77 | ANADIG_PLL_CTRL_EN_USB_CLKS); 78 break; 79 default: 80 return; 81 } 82 } 83 84 static void usb_phy_enable(int index, struct usb_ehci *ehci) 85 { 86 void __iomem *phy_reg; 87 void __iomem *phy_ctrl; 88 void __iomem *usb_cmd; 89 90 phy_reg = (void __iomem *)phy_bases[index]; 91 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 92 usb_cmd = (void __iomem *)&ehci->usbcmd; 93 94 /* Stop then Reset */ 95 clrbits_le32(usb_cmd, UCMD_RUN_STOP); 96 while (readl(usb_cmd) & UCMD_RUN_STOP) 97 ; 98 99 setbits_le32(usb_cmd, UCMD_RESET); 100 while (readl(usb_cmd) & UCMD_RESET) 101 ; 102 103 /* Reset USBPHY module */ 104 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 105 udelay(10); 106 107 /* Remove CLKGATE and SFTRST */ 108 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 109 udelay(10); 110 111 /* Power up the PHY */ 112 writel(0, phy_reg + USBPHY_PWD); 113 114 /* Enable FS/LS device */ 115 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 116 USBPHY_CTRL_ENUTMILEVEL3); 117 } 118 119 static void usb_oc_config(int index) 120 { 121 void __iomem *ctrl; 122 123 ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET); 124 125 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); 126 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); 127 } 128 129 int __weak board_usb_phy_mode(int port) 130 { 131 return 0; 132 } 133 134 int __weak board_ehci_hcd_init(int port) 135 { 136 return 0; 137 } 138 139 int ehci_vf_common_init(struct usb_ehci *ehci, int index) 140 { 141 int ret; 142 143 /* Do board specific initialisation */ 144 ret = board_ehci_hcd_init(index); 145 if (ret) 146 return ret; 147 148 usb_power_config(index); 149 usb_oc_config(index); 150 usb_internal_phy_clock_gate(index); 151 usb_phy_enable(index, ehci); 152 153 return 0; 154 } 155 156 #ifndef CONFIG_DM_USB 157 int ehci_hcd_init(int index, enum usb_init_type init, 158 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 159 { 160 struct usb_ehci *ehci; 161 enum usb_init_type type; 162 int ret; 163 164 if (index >= ARRAY_SIZE(nc_reg_bases)) 165 return -EINVAL; 166 167 ehci = (struct usb_ehci *)nc_reg_bases[index]; 168 169 ret = ehci_vf_common_init(index); 170 if (ret) 171 return ret; 172 173 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 174 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 175 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 176 177 type = board_usb_phy_mode(index); 178 if (type != init) 179 return -ENODEV; 180 181 if (init == USB_INIT_DEVICE) { 182 setbits_le32(&ehci->usbmode, CM_DEVICE); 183 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); 184 setbits_le32(&ehci->portsc, USB_EN); 185 } else if (init == USB_INIT_HOST) { 186 setbits_le32(&ehci->usbmode, CM_HOST); 187 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); 188 setbits_le32(&ehci->portsc, USB_EN); 189 } 190 191 return 0; 192 } 193 194 int ehci_hcd_stop(int index) 195 { 196 return 0; 197 } 198 #else 199 /* Possible port types (dual role mode) */ 200 enum dr_mode { 201 DR_MODE_NONE = 0, 202 DR_MODE_HOST, /* supports host operation */ 203 DR_MODE_DEVICE, /* supports device operation */ 204 DR_MODE_OTG, /* supports both */ 205 }; 206 207 struct ehci_vf_priv_data { 208 struct ehci_ctrl ctrl; 209 struct usb_ehci *ehci; 210 struct gpio_desc cdet_gpio; 211 enum usb_init_type init_type; 212 enum dr_mode dr_mode; 213 u32 portnr; 214 }; 215 216 static int vf_usb_ofdata_to_platdata(struct udevice *dev) 217 { 218 struct ehci_vf_priv_data *priv = dev_get_priv(dev); 219 const void *dt_blob = gd->fdt_blob; 220 int node = dev_of_offset(dev); 221 const char *mode; 222 223 priv->portnr = dev->seq; 224 225 priv->ehci = (struct usb_ehci *)devfdt_get_addr(dev); 226 mode = fdt_getprop(dt_blob, node, "dr_mode", NULL); 227 if (mode) { 228 if (0 == strcmp(mode, "host")) { 229 priv->dr_mode = DR_MODE_HOST; 230 priv->init_type = USB_INIT_HOST; 231 } else if (0 == strcmp(mode, "peripheral")) { 232 priv->dr_mode = DR_MODE_DEVICE; 233 priv->init_type = USB_INIT_DEVICE; 234 } else if (0 == strcmp(mode, "otg")) { 235 priv->dr_mode = DR_MODE_OTG; 236 /* 237 * We set init_type to device by default when OTG 238 * mode is requested. If a valid gpio is provided 239 * we will switch the init_type based on the state 240 * of the gpio pin. 241 */ 242 priv->init_type = USB_INIT_DEVICE; 243 } else { 244 debug("%s: Cannot decode dr_mode '%s'\n", 245 __func__, mode); 246 return -EINVAL; 247 } 248 } else { 249 priv->dr_mode = DR_MODE_HOST; 250 priv->init_type = USB_INIT_HOST; 251 } 252 253 if (priv->dr_mode == DR_MODE_OTG) { 254 gpio_request_by_name_nodev(offset_to_ofnode(node), 255 "fsl,cdet-gpio", 0, &priv->cdet_gpio, 256 GPIOD_IS_IN); 257 if (dm_gpio_is_valid(&priv->cdet_gpio)) { 258 if (dm_gpio_get_value(&priv->cdet_gpio)) 259 priv->init_type = USB_INIT_DEVICE; 260 else 261 priv->init_type = USB_INIT_HOST; 262 } 263 } 264 265 return 0; 266 } 267 268 static int vf_init_after_reset(struct ehci_ctrl *dev) 269 { 270 struct ehci_vf_priv_data *priv = dev->priv; 271 enum usb_init_type type = priv->init_type; 272 struct usb_ehci *ehci = priv->ehci; 273 int ret; 274 275 ret = ehci_vf_common_init(priv->ehci, priv->portnr); 276 if (ret) 277 return ret; 278 279 if (type == USB_INIT_DEVICE) 280 return 0; 281 282 setbits_le32(&ehci->usbmode, CM_HOST); 283 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); 284 setbits_le32(&ehci->portsc, USB_EN); 285 286 mdelay(10); 287 288 return 0; 289 } 290 291 static const struct ehci_ops vf_ehci_ops = { 292 .init_after_reset = vf_init_after_reset 293 }; 294 295 static int vf_usb_bind(struct udevice *dev) 296 { 297 static int num_controllers; 298 299 /* 300 * Without this hack, if we return ENODEV for USB Controller 0, on 301 * probe for the next controller, USB Controller 1 will be given a 302 * sequence number of 0. This conflicts with our requirement of 303 * sequence numbers while initialising the peripherals. 304 */ 305 dev->req_seq = num_controllers; 306 num_controllers++; 307 308 return 0; 309 } 310 311 static int ehci_usb_probe(struct udevice *dev) 312 { 313 struct usb_platdata *plat = dev_get_platdata(dev); 314 struct ehci_vf_priv_data *priv = dev_get_priv(dev); 315 struct usb_ehci *ehci = priv->ehci; 316 struct ehci_hccr *hccr; 317 struct ehci_hcor *hcor; 318 int ret; 319 320 ret = ehci_vf_common_init(ehci, priv->portnr); 321 if (ret) 322 return ret; 323 324 if (priv->init_type != plat->init_type) 325 return -ENODEV; 326 327 if (priv->init_type == USB_INIT_HOST) { 328 setbits_le32(&ehci->usbmode, CM_HOST); 329 writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc); 330 setbits_le32(&ehci->portsc, USB_EN); 331 } 332 333 mdelay(10); 334 335 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 336 hcor = (struct ehci_hcor *)((uint32_t)hccr + 337 HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 338 339 return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type); 340 } 341 342 static const struct udevice_id vf_usb_ids[] = { 343 { .compatible = "fsl,vf610-usb" }, 344 { } 345 }; 346 347 U_BOOT_DRIVER(usb_ehci) = { 348 .name = "ehci_vf", 349 .id = UCLASS_USB, 350 .of_match = vf_usb_ids, 351 .bind = vf_usb_bind, 352 .probe = ehci_usb_probe, 353 .remove = ehci_deregister, 354 .ops = &ehci_usb_ops, 355 .ofdata_to_platdata = vf_usb_ofdata_to_platdata, 356 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 357 .priv_auto_alloc_size = sizeof(struct ehci_vf_priv_data), 358 .flags = DM_FLAG_ALLOC_PRIV_DMA, 359 }; 360 #endif 361
