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      1 // SPDX-License-Identifier: GPL-2.0+
      2 /*
      3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
      4  */
      5 
      6 #include <common.h>
      7 #include <asm/io.h>
      8 #include <asm/arch/imx-regs.h>
      9 
     10 /*
     11  * MX7ULP WDOG Register Map
     12  */
     13 struct wdog_regs {
     14 	u8 cs1;
     15 	u8 cs2;
     16 	u16 reserve0;
     17 	u32 cnt;
     18 	u32 toval;
     19 	u32 win;
     20 };
     21 
     22 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
     23 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
     24 #endif
     25 
     26 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
     27 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
     28 
     29 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
     30 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
     31 
     32 #define WDGCS1_WDGE                      (1<<7)
     33 #define WDGCS1_WDGUPDATE                 (1<<5)
     34 
     35 #define WDGCS2_FLG                       (1<<6)
     36 
     37 #define WDG_BUS_CLK                      (0x0)
     38 #define WDG_LPO_CLK                      (0x1)
     39 #define WDG_32KHZ_CLK                    (0x2)
     40 #define WDG_EXT_CLK                      (0x3)
     41 
     42 void hw_watchdog_set_timeout(u16 val)
     43 {
     44 	/* setting timeout value */
     45 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
     46 
     47 	writel(val, &wdog->toval);
     48 }
     49 
     50 void hw_watchdog_reset(void)
     51 {
     52 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
     53 
     54 	writel(REFRESH_WORD0, &wdog->cnt);
     55 	writel(REFRESH_WORD1, &wdog->cnt);
     56 }
     57 
     58 void hw_watchdog_init(void)
     59 {
     60 	u8 val;
     61 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
     62 
     63 	writel(UNLOCK_WORD0, &wdog->cnt);
     64 	writel(UNLOCK_WORD1, &wdog->cnt);
     65 
     66 	val = readb(&wdog->cs2);
     67 	val |= WDGCS2_FLG;
     68 	writeb(val, &wdog->cs2);
     69 
     70 	hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
     71 	writel(0, &wdog->win);
     72 
     73 	writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
     74 	writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
     75 
     76 	hw_watchdog_reset();
     77 }
     78 
     79 void reset_cpu(ulong addr)
     80 {
     81 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
     82 
     83 	writel(UNLOCK_WORD0, &wdog->cnt);
     84 	writel(UNLOCK_WORD1, &wdog->cnt);
     85 
     86 	hw_watchdog_set_timeout(5); /* 5ms timeout */
     87 	writel(0, &wdog->win);
     88 
     89 	writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
     90 	writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
     91 
     92 	hw_watchdog_reset();
     93 
     94 	while (1);
     95 }
     96