1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2007-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * MPC8610HPCD board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 15 16 /* video */ 17 #define CONFIG_FSL_DIU_FB 18 19 #ifdef CONFIG_FSL_DIU_FB 20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 21 #define CONFIG_VIDEO_LOGO 22 #define CONFIG_VIDEO_BMP_LOGO 23 #endif 24 25 #ifdef RUN_DIAG 26 #define CONFIG_SYS_DIAG_ADDR 0xff800000 27 #endif 28 29 /* 30 * virtual address to be used for temporary mappings. There 31 * should be 128k free at this VA. 32 */ 33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 34 35 #define CONFIG_PCI1 1 /* PCI controller 1 */ 36 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 37 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 38 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 41 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 44 45 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 46 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 47 #define CONFIG_ALTIVEC 1 48 49 /* 50 * L2CR setup -- make sure this is right for your board! 51 */ 52 #define CONFIG_SYS_L2 53 #define L2_INIT 0 54 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 58 #endif 59 60 #define CONFIG_MISC_INIT_R 1 61 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 63 #define CONFIG_SYS_MEMTEST_END 0x00400000 64 65 /* 66 * Base addresses -- Note these are effective addresses where the 67 * actual resources get mapped (not physical addresses) 68 */ 69 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 70 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 71 72 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 73 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 74 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 75 76 /* DDR Setup */ 77 #undef CONFIG_FSL_DDR_INTERACTIVE 78 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 79 #define CONFIG_DDR_SPD 80 81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 87 #define CONFIG_VERY_BIG_RAM 88 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 91 92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 93 94 /* These are used when DDR doesn't use SPD. */ 95 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 96 97 #if 0 /* TODO */ 98 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 99 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 100 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 101 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 102 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 103 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 104 #define CONFIG_SYS_DDR_MODE_1 0x00480432 105 #define CONFIG_SYS_DDR_MODE_2 0x00000000 106 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 107 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 108 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 109 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 110 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 111 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 112 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 113 114 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 115 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 116 #define CONFIG_SYS_DDR_SBE 0x000f0000 117 118 #endif 119 120 #define CONFIG_ID_EEPROM 121 #define CONFIG_SYS_I2C_EEPROM_NXID 122 #define CONFIG_ID_EEPROM 123 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 125 126 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 127 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 128 129 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 130 131 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 132 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 133 134 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 135 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 136 #if 0 /* TODO */ 137 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 138 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 139 #endif 140 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 141 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 142 143 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 144 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 145 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 146 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 147 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 148 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 149 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 150 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 151 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 152 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 153 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 154 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 155 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 156 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 157 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 158 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 159 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 160 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 161 162 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 163 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 164 165 #undef CONFIG_SYS_FLASH_CHECKSUM 166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 169 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 170 171 #define CONFIG_FLASH_CFI_DRIVER 172 #define CONFIG_SYS_FLASH_CFI 173 #define CONFIG_SYS_FLASH_EMPTY_INFO 174 175 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 176 #define CONFIG_SYS_RAMBOOT 177 #else 178 #undef CONFIG_SYS_RAMBOOT 179 #endif 180 181 #if defined(CONFIG_SYS_RAMBOOT) 182 #undef CONFIG_SPD_EEPROM 183 #define CONFIG_SYS_SDRAM_SIZE 256 184 #endif 185 186 #undef CONFIG_CLOCKS_IN_MHZ 187 188 #define CONFIG_SYS_INIT_RAM_LOCK 1 189 #ifndef CONFIG_SYS_INIT_RAM_LOCK 190 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 191 #else 192 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 193 #endif 194 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 195 196 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 197 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 198 199 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 200 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 201 202 /* Serial Port */ 203 #define CONFIG_SYS_NS16550_SERIAL 204 #define CONFIG_SYS_NS16550_REG_SIZE 1 205 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 206 207 #define CONFIG_SYS_BAUDRATE_TABLE \ 208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 209 210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 212 213 /* maximum size of the flat tree (8K) */ 214 #define OF_FLAT_TREE_MAX_SIZE 8192 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_FSL 221 #define CONFIG_SYS_FSL_I2C_SPEED 400000 222 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 223 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 224 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 225 226 /* 227 * General PCI 228 * Addresses are mapped 1-1. 229 */ 230 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 231 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 232 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 233 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 234 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 235 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 236 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 237 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 238 239 /* controller 1, Base address 0xa000 */ 240 #define CONFIG_SYS_PCIE1_NAME "ULI" 241 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 242 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 243 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 244 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 245 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 246 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 247 248 /* controller 2, Base Address 0x9000 */ 249 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 250 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 251 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 252 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 253 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 254 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 255 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 256 257 #if defined(CONFIG_PCI) 258 259 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 260 261 #define CONFIG_ULI526X 262 #ifdef CONFIG_ULI526X 263 #endif 264 265 /************************************************************ 266 * USB support 267 ************************************************************/ 268 #define CONFIG_PCI_OHCI 1 269 #define CONFIG_USB_OHCI_NEW 1 270 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 271 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 272 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 273 274 #if !defined(CONFIG_PCI_PNP) 275 #define PCI_ENET0_IOADDR 0xe0000000 276 #define PCI_ENET0_MEMADDR 0xe0000000 277 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 278 #endif 279 280 #ifdef CONFIG_SCSI_AHCI 281 #define CONFIG_SATA_ULI5288 282 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 283 #define CONFIG_SYS_SCSI_MAX_LUN 1 284 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 285 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 286 #endif 287 288 #endif /* CONFIG_PCI */ 289 290 /* 291 * BAT0 2G Cacheable, non-guarded 292 * 0x0000_0000 2G DDR 293 */ 294 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 295 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 296 297 /* 298 * BAT1 1G Cache-inhibited, guarded 299 * 0x8000_0000 256M PCI-1 Memory 300 * 0xa000_0000 256M PCI-Express 1 Memory 301 * 0x9000_0000 256M PCI-Express 2 Memory 302 */ 303 304 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 305 | BATL_GUARDEDSTORAGE) 306 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 307 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 308 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 309 310 /* 311 * BAT2 16M Cache-inhibited, guarded 312 * 0xe100_0000 1M PCI-1 I/O 313 */ 314 315 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 316 | BATL_GUARDEDSTORAGE) 317 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 318 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 319 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 320 321 /* 322 * BAT3 4M Cache-inhibited, guarded 323 * 0xe000_0000 4M CCSR 324 */ 325 326 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 327 | BATL_GUARDEDSTORAGE) 328 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 329 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 330 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 331 332 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 333 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 334 | BATL_PP_RW | BATL_CACHEINHIBIT \ 335 | BATL_GUARDEDSTORAGE) 336 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 337 | BATU_BL_1M | BATU_VS | BATU_VP) 338 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 339 | BATL_PP_RW | BATL_CACHEINHIBIT) 340 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 341 #endif 342 343 /* 344 * BAT4 32M Cache-inhibited, guarded 345 * 0xe200_0000 1M PCI-Express 2 I/O 346 * 0xe300_0000 1M PCI-Express 1 I/O 347 */ 348 349 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 350 | BATL_GUARDEDSTORAGE) 351 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 352 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 353 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 354 355 /* 356 * BAT5 128K Cacheable, non-guarded 357 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 358 */ 359 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 360 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 361 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 362 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 363 364 /* 365 * BAT6 256M Cache-inhibited, guarded 366 * 0xf000_0000 256M FLASH 367 */ 368 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 369 | BATL_GUARDEDSTORAGE) 370 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 371 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 372 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 373 374 /* Map the last 1M of flash where we're running from reset */ 375 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 376 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 377 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 378 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 379 | BATL_MEMCOHERENCE) 380 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 381 382 /* 383 * BAT7 4M Cache-inhibited, guarded 384 * 0xe800_0000 4M PIXIS 385 */ 386 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 387 | BATL_GUARDEDSTORAGE) 388 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 389 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 390 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 391 392 /* 393 * Environment 394 */ 395 #ifndef CONFIG_SYS_RAMBOOT 396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 397 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 398 #define CONFIG_ENV_SIZE 0x2000 399 #else 400 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 401 #define CONFIG_ENV_SIZE 0x2000 402 #endif 403 404 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 405 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 406 407 /* 408 * BOOTP options 409 */ 410 #define CONFIG_BOOTP_BOOTFILESIZE 411 412 /* 413 * Command line configuration. 414 */ 415 416 #define CONFIG_WATCHDOG /* watchdog enabled */ 417 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 418 419 /* 420 * Miscellaneous configurable options 421 */ 422 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 423 424 /* 425 * For booting Linux, the board info and command line data 426 * have to be in the first 8 MB of memory, since this is 427 * the maximum mapped by the Linux kernel during initialization. 428 */ 429 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 430 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 431 432 #if defined(CONFIG_CMD_KGDB) 433 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 434 #endif 435 436 /* 437 * Environment Configuration 438 */ 439 #define CONFIG_IPADDR 192.168.1.100 440 441 #define CONFIG_HOSTNAME "unknown" 442 #define CONFIG_ROOTPATH "/opt/nfsroot" 443 #define CONFIG_BOOTFILE "uImage" 444 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 445 446 #define CONFIG_SERVERIP 192.168.1.1 447 #define CONFIG_GATEWAYIP 192.168.1.1 448 #define CONFIG_NETMASK 255.255.255.0 449 450 /* default location for tftp and bootm */ 451 #define CONFIG_LOADADDR 0x10000000 452 453 #if defined(CONFIG_PCI1) 454 #define PCI_ENV \ 455 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 456 "echo e;md ${a}e00 9\0" \ 457 "pci1regs=setenv a e0008; run pcireg\0" \ 458 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 459 "pci d.w $b.0 56 1\0" \ 460 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 461 "pci w.w $b.0 56 ffff\0" \ 462 "pci1err=setenv a e0008; run pcierr\0" \ 463 "pci1errc=setenv a e0008; run pcierrc\0" 464 #else 465 #define PCI_ENV "" 466 #endif 467 468 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 469 #define PCIE_ENV \ 470 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 471 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 472 "pcie1regs=setenv a e000a; run pciereg\0" \ 473 "pcie2regs=setenv a e0009; run pciereg\0" \ 474 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 475 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 476 "pci d $b.0 130 1\0" \ 477 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 478 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 479 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 480 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 481 "pcie1err=setenv a e000a; run pcieerr\0" \ 482 "pcie2err=setenv a e0009; run pcieerr\0" \ 483 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 484 "pcie2errc=setenv a e0009; run pcieerrc\0" 485 #else 486 #define PCIE_ENV "" 487 #endif 488 489 #define DMA_ENV \ 490 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 491 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 492 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 493 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 494 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 495 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 496 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 497 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 498 499 #ifdef ENV_DEBUG 500 #define CONFIG_EXTRA_ENV_SETTINGS \ 501 "netdev=eth0\0" \ 502 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 503 "tftpflash=tftpboot $loadaddr $uboot; " \ 504 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 505 " +$filesize; " \ 506 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 507 " +$filesize; " \ 508 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 509 " $filesize; " \ 510 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 511 " +$filesize; " \ 512 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 513 " $filesize\0" \ 514 "consoledev=ttyS0\0" \ 515 "ramdiskaddr=0x18000000\0" \ 516 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 517 "fdtaddr=0x17c00000\0" \ 518 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 519 "bdev=sda3\0" \ 520 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 521 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 522 "maxcpus=1" \ 523 "eoi=mw e00400b0 0\0" \ 524 "iack=md e00400a0 1\0" \ 525 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 526 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 527 "md ${a}f00 5\0" \ 528 "ddr1regs=setenv a e0002; run ddrreg\0" \ 529 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 530 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 531 "md ${a}e60 1; md ${a}ef0 1d\0" \ 532 "guregs=setenv a e00e0; run gureg\0" \ 533 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 534 "mcmregs=setenv a e0001; run mcmreg\0" \ 535 "diuregs=md e002c000 1d\0" \ 536 "dium=mw e002c01c\0" \ 537 "diuerr=md e002c014 1\0" \ 538 "pmregs=md e00e1000 2b\0" \ 539 "lawregs=md e0000c08 4b\0" \ 540 "lbcregs=md e0005000 36\0" \ 541 "dma0regs=md e0021100 12\0" \ 542 "dma1regs=md e0021180 12\0" \ 543 "dma2regs=md e0021200 12\0" \ 544 "dma3regs=md e0021280 12\0" \ 545 PCI_ENV \ 546 PCIE_ENV \ 547 DMA_ENV 548 #else 549 #define CONFIG_EXTRA_ENV_SETTINGS \ 550 "netdev=eth0\0" \ 551 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 552 "consoledev=ttyS0\0" \ 553 "ramdiskaddr=0x18000000\0" \ 554 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 555 "fdtaddr=0x17c00000\0" \ 556 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 557 "bdev=sda3\0" 558 #endif 559 560 #define CONFIG_NFSBOOTCOMMAND \ 561 "setenv bootargs root=/dev/nfs rw " \ 562 "nfsroot=$serverip:$rootpath " \ 563 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 564 "console=$consoledev,$baudrate $othbootargs;" \ 565 "tftp $loadaddr $bootfile;" \ 566 "tftp $fdtaddr $fdtfile;" \ 567 "bootm $loadaddr - $fdtaddr" 568 569 #define CONFIG_RAMBOOTCOMMAND \ 570 "setenv bootargs root=/dev/ram rw " \ 571 "console=$consoledev,$baudrate $othbootargs;" \ 572 "tftp $ramdiskaddr $ramdiskfile;" \ 573 "tftp $loadaddr $bootfile;" \ 574 "tftp $fdtaddr $fdtfile;" \ 575 "bootm $loadaddr $ramdiskaddr $fdtaddr" 576 577 #define CONFIG_BOOTCOMMAND \ 578 "setenv bootargs root=/dev/$bdev rw " \ 579 "console=$consoledev,$baudrate $othbootargs;" \ 580 "tftp $loadaddr $bootfile;" \ 581 "tftp $fdtaddr $fdtfile;" \ 582 "bootm $loadaddr - $fdtaddr" 583 584 #endif /* __CONFIG_H */ 585
