1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014 Freescale Semiconductor 4 */ 5 6 #ifndef __LS2_SIMU_H 7 #define __LS2_SIMU_H 8 9 #include "ls2080a_common.h" 10 11 #define CONFIG_SYS_CLK_FREQ 100000000 12 #define CONFIG_DDR_CLK_FREQ 133333333 13 14 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 15 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 16 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 17 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 18 #endif 19 20 /* SMSC 91C111 ethernet configuration */ 21 #define CONFIG_SMC91111 22 #define CONFIG_SMC91111_BASE (0x2210000) 23 24 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 25 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 26 27 #ifdef CONFIG_MTD_NOR_FLASH 28 #define CONFIG_FLASH_CFI_DRIVER 29 #define CONFIG_SYS_FLASH_CFI 30 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 31 #define CONFIG_SYS_FLASH_QUIET_TEST 32 #endif 33 34 /* 35 * NOR Flash Timing Params 36 */ 37 #define CONFIG_SYS_NOR0_CSPR \ 38 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 39 CSPR_PORT_SIZE_16 | \ 40 CSPR_MSEL_NOR | \ 41 CSPR_V) 42 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 43 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 44 CSPR_PORT_SIZE_16 | \ 45 CSPR_MSEL_NOR | \ 46 CSPR_V) 47 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 48 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 49 FTIM0_NOR_TEADC(0x1) | \ 50 FTIM0_NOR_TEAHC(0x1)) 51 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 52 FTIM1_NOR_TRAD_NOR(0x1)) 53 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 54 FTIM2_NOR_TCH(0x0) | \ 55 FTIM2_NOR_TWP(0x1)) 56 #define CONFIG_SYS_NOR_FTIM3 0x04000000 57 #define CONFIG_SYS_IFC_CCR 0x01000000 58 59 #ifdef CONFIG_MTD_NOR_FLASH 60 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 61 62 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 63 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 64 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 65 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 66 67 #define CONFIG_SYS_FLASH_EMPTY_INFO 68 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 69 #endif 70 71 #define CONFIG_NAND_FSL_IFC 72 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 73 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 74 75 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 76 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 77 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 78 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 79 | CSPR_V) 80 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 81 82 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 83 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 84 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 85 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 86 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 87 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 88 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 89 90 #define CONFIG_SYS_NAND_ONFI_DETECTION 91 92 /* ONFI NAND Flash mode0 Timing Params */ 93 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 94 FTIM0_NAND_TWP(0x18) | \ 95 FTIM0_NAND_TWCHT(0x07) | \ 96 FTIM0_NAND_TWH(0x0a)) 97 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 98 FTIM1_NAND_TWBE(0x39) | \ 99 FTIM1_NAND_TRR(0x0e) | \ 100 FTIM1_NAND_TRP(0x18)) 101 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 102 FTIM2_NAND_TREH(0x0a) | \ 103 FTIM2_NAND_TWHRE(0x1e)) 104 #define CONFIG_SYS_NAND_FTIM3 0x0 105 106 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 107 #define CONFIG_SYS_MAX_NAND_DEVICE 1 108 #define CONFIG_MTD_NAND_VERIFY_WRITE 109 110 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 111 112 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 113 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 114 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 115 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 116 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 117 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 118 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 119 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 120 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 121 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 122 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 123 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 124 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 125 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 126 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 127 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 128 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 129 130 /* MMC */ 131 #ifdef CONFIG_MMC 132 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 133 #endif 134 135 /* Debug Server firmware */ 136 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 137 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 138 139 /* MC firmware */ 140 #define CONFIG_SYS_LS_MC_DPL_IN_NOR 141 #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL 142 143 #define CONFIG_SYS_LS_MC_DPC_IN_NOR 144 #define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL 145 146 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 147 148 /* Store environment at top of flash */ 149 #define CONFIG_ENV_SIZE 0x1000 150 151 #endif /* __LS2_SIMU_H */ 152
