1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #ifdef CONFIG_FSL_QSPI 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #define CONFIG_SYS_I2C_EARLY_INIT 20 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 21 #endif 22 23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 24 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 25 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 26 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 27 28 #define CONFIG_DDR_SPD 29 #define CONFIG_DDR_ECC 30 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 32 #define SPD_EEPROM_ADDRESS1 0x51 33 #define SPD_EEPROM_ADDRESS2 0x52 34 #define SPD_EEPROM_ADDRESS3 0x53 35 #define SPD_EEPROM_ADDRESS4 0x54 36 #define SPD_EEPROM_ADDRESS5 0x55 37 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 38 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 39 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 40 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 41 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 42 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 43 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 44 #endif 45 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 46 47 /* SATA */ 48 #define CONFIG_SCSI_AHCI_PLAT 49 50 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 51 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 52 53 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 54 #define CONFIG_SYS_SCSI_MAX_LUN 1 55 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 56 CONFIG_SYS_SCSI_MAX_LUN) 57 58 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 59 60 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 61 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 62 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 63 64 #define CONFIG_SYS_NOR0_CSPR \ 65 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 66 CSPR_PORT_SIZE_16 | \ 67 CSPR_MSEL_NOR | \ 68 CSPR_V) 69 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 71 CSPR_PORT_SIZE_16 | \ 72 CSPR_MSEL_NOR | \ 73 CSPR_V) 74 #define CONFIG_SYS_NOR1_CSPR \ 75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 76 CSPR_PORT_SIZE_16 | \ 77 CSPR_MSEL_NOR | \ 78 CSPR_V) 79 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 81 CSPR_PORT_SIZE_16 | \ 82 CSPR_MSEL_NOR | \ 83 CSPR_V) 84 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 85 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 86 FTIM0_NOR_TEADC(0x5) | \ 87 FTIM0_NOR_TEAHC(0x5)) 88 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 89 FTIM1_NOR_TRAD_NOR(0x1a) |\ 90 FTIM1_NOR_TSEQRAD_NOR(0x13)) 91 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 92 FTIM2_NOR_TCH(0x4) | \ 93 FTIM2_NOR_TWPH(0x0E) | \ 94 FTIM2_NOR_TWP(0x1c)) 95 #define CONFIG_SYS_NOR_FTIM3 0x04000000 96 #define CONFIG_SYS_IFC_CCR 0x01000000 97 98 #ifdef CONFIG_MTD_NOR_FLASH 99 #define CONFIG_FLASH_CFI_DRIVER 100 #define CONFIG_SYS_FLASH_CFI 101 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 102 #define CONFIG_SYS_FLASH_QUIET_TEST 103 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 104 105 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 106 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 107 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 108 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 109 110 #define CONFIG_SYS_FLASH_EMPTY_INFO 111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 112 CONFIG_SYS_FLASH_BASE + 0x40000000} 113 #endif 114 115 #define CONFIG_NAND_FSL_IFC 116 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 117 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 118 119 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 120 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 121 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 122 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 123 | CSPR_V) 124 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 125 126 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 127 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 128 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 129 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 130 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 131 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 132 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 133 134 #define CONFIG_SYS_NAND_ONFI_DETECTION 135 136 /* ONFI NAND Flash mode0 Timing Params */ 137 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 138 FTIM0_NAND_TWP(0x18) | \ 139 FTIM0_NAND_TWCHT(0x07) | \ 140 FTIM0_NAND_TWH(0x0a)) 141 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 142 FTIM1_NAND_TWBE(0x39) | \ 143 FTIM1_NAND_TRR(0x0e) | \ 144 FTIM1_NAND_TRP(0x18)) 145 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 146 FTIM2_NAND_TREH(0x0a) | \ 147 FTIM2_NAND_TWHRE(0x1e)) 148 #define CONFIG_SYS_NAND_FTIM3 0x0 149 150 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 151 #define CONFIG_SYS_MAX_NAND_DEVICE 1 152 #define CONFIG_MTD_NAND_VERIFY_WRITE 153 154 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 155 156 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 157 #define QIXIS_LBMAP_SWITCH 0x06 158 #define QIXIS_LBMAP_MASK 0x0f 159 #define QIXIS_LBMAP_SHIFT 0 160 #define QIXIS_LBMAP_DFLTBANK 0x00 161 #define QIXIS_LBMAP_ALTBANK 0x04 162 #define QIXIS_LBMAP_NAND 0x09 163 #define QIXIS_LBMAP_SD 0x00 164 #define QIXIS_LBMAP_QSPI 0x0f 165 #define QIXIS_RST_CTL_RESET 0x31 166 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 167 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 168 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 169 #define QIXIS_RCW_SRC_NAND 0x107 170 #define QIXIS_RCW_SRC_SD 0x40 171 #define QIXIS_RCW_SRC_QSPI 0x62 172 #define QIXIS_RST_FORCE_MEM 0x01 173 174 #define CONFIG_SYS_CSPR3_EXT (0x0) 175 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 176 | CSPR_PORT_SIZE_8 \ 177 | CSPR_MSEL_GPCM \ 178 | CSPR_V) 179 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 180 | CSPR_PORT_SIZE_8 \ 181 | CSPR_MSEL_GPCM \ 182 | CSPR_V) 183 184 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 185 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 186 /* QIXIS Timing parameters for IFC CS3 */ 187 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 188 FTIM0_GPCM_TEADC(0x0e) | \ 189 FTIM0_GPCM_TEAHC(0x0e)) 190 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 191 FTIM1_GPCM_TRAD(0x3f)) 192 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 193 FTIM2_GPCM_TCH(0xf) | \ 194 FTIM2_GPCM_TWP(0x3E)) 195 #define CONFIG_SYS_CS3_FTIM3 0x0 196 197 #if defined(CONFIG_SPL) 198 #if defined(CONFIG_NAND_BOOT) 199 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 200 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 201 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 202 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 203 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 204 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 205 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 206 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 207 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 208 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 209 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 210 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 211 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 212 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 213 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 214 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 215 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 216 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 217 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 218 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 219 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 226 227 #define CONFIG_ENV_OFFSET (896 * 1024) 228 #define CONFIG_ENV_SECT_SIZE 0x20000 229 #define CONFIG_ENV_SIZE 0x2000 230 #define CONFIG_SPL_PAD_TO 0x20000 231 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 233 #elif defined(CONFIG_SD_BOOT) 234 #define CONFIG_ENV_OFFSET 0x300000 235 #define CONFIG_SYS_MMC_ENV_DEV 0 236 #define CONFIG_ENV_SIZE 0x20000 237 #endif 238 #else 239 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 240 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 241 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 242 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 243 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 244 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 245 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 246 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 247 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 248 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 249 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 250 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 251 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 252 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 253 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 254 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 255 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 256 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 257 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 258 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 259 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 260 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 261 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 262 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 263 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 264 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 265 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 266 267 #ifndef CONFIG_QSPI_BOOT 268 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 269 #define CONFIG_ENV_SECT_SIZE 0x20000 270 #define CONFIG_ENV_SIZE 0x2000 271 #endif 272 #endif 273 274 /* Debug Server firmware */ 275 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 276 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 277 278 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 279 280 /* 281 * I2C 282 */ 283 #define I2C_MUX_PCA_ADDR 0x77 284 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 285 286 /* I2C bus multiplexer */ 287 #define I2C_MUX_CH_DEFAULT 0x8 288 289 /* SPI */ 290 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 291 #define CONFIG_SPI_FLASH 292 293 #ifdef CONFIG_FSL_DSPI 294 #define CONFIG_SPI_FLASH_STMICRO 295 #define CONFIG_SPI_FLASH_SST 296 #define CONFIG_SPI_FLASH_EON 297 #endif 298 299 #ifdef CONFIG_FSL_QSPI 300 #define CONFIG_SPI_FLASH_SPANSION 301 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 302 #define FSL_QSPI_FLASH_NUM 4 303 #endif 304 /* 305 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 306 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 307 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 308 */ 309 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 310 311 #endif 312 313 /* 314 * MMC 315 */ 316 #ifdef CONFIG_MMC 317 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 318 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 319 #endif 320 321 /* 322 * RTC configuration 323 */ 324 #define RTC 325 #define CONFIG_RTC_DS3231 1 326 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 327 328 /* EEPROM */ 329 #define CONFIG_ID_EEPROM 330 #define CONFIG_SYS_I2C_EEPROM_NXID 331 #define CONFIG_SYS_EEPROM_BUS_NUM 0 332 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 333 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 334 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 336 337 #define CONFIG_FSL_MEMAC 338 339 #ifdef CONFIG_PCI 340 #define CONFIG_PCI_SCAN_SHOW 341 #endif 342 343 /* MMC */ 344 #ifdef CONFIG_MMC 345 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 346 #endif 347 348 /* Initial environment variables */ 349 #undef CONFIG_EXTRA_ENV_SETTINGS 350 #ifdef CONFIG_SECURE_BOOT 351 #define CONFIG_EXTRA_ENV_SETTINGS \ 352 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 353 "loadaddr=0x80100000\0" \ 354 "kernel_addr=0x100000\0" \ 355 "ramdisk_addr=0x800000\0" \ 356 "ramdisk_size=0x2000000\0" \ 357 "fdt_high=0xa0000000\0" \ 358 "initrd_high=0xffffffffffffffff\0" \ 359 "kernel_start=0x581000000\0" \ 360 "kernel_load=0xa0000000\0" \ 361 "kernel_size=0x2800000\0" \ 362 "mcmemsize=0x40000000\0" \ 363 "mcinitcmd=esbc_validate 0x580700000;" \ 364 "esbc_validate 0x580740000;" \ 365 "fsl_mc start mc 0x580a00000" \ 366 " 0x580e00000 \0" 367 #elif defined(CONFIG_SD_BOOT) 368 #define CONFIG_EXTRA_ENV_SETTINGS \ 369 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 370 "loadaddr=0x90100000\0" \ 371 "kernel_addr=0x800\0" \ 372 "ramdisk_addr=0x800000\0" \ 373 "ramdisk_size=0x2000000\0" \ 374 "fdt_high=0xa0000000\0" \ 375 "initrd_high=0xffffffffffffffff\0" \ 376 "kernel_start=0x8000\0" \ 377 "kernel_load=0xa0000000\0" \ 378 "kernel_size=0x14000\0" \ 379 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 380 "mmc read 0x80100000 0x7000 0x800;" \ 381 "fsl_mc start mc 0x80000000 0x80100000\0" \ 382 "mcmemsize=0x70000000 \0" 383 #else 384 #define CONFIG_EXTRA_ENV_SETTINGS \ 385 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 386 "loadaddr=0x80100000\0" \ 387 "kernel_addr=0x100000\0" \ 388 "ramdisk_addr=0x800000\0" \ 389 "ramdisk_size=0x2000000\0" \ 390 "fdt_high=0xa0000000\0" \ 391 "initrd_high=0xffffffffffffffff\0" \ 392 "kernel_start=0x581000000\0" \ 393 "kernel_load=0xa0000000\0" \ 394 "kernel_size=0x2800000\0" \ 395 "mcmemsize=0x40000000\0" \ 396 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 397 " 0x580e00000 \0" 398 #endif /* CONFIG_SECURE_BOOT */ 399 400 401 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 402 #define CONFIG_FSL_MEMAC 403 #define CONFIG_PHYLIB_10G 404 #define CONFIG_PHY_VITESSE 405 #define CONFIG_PHY_REALTEK 406 #define CONFIG_PHY_TERANETICS 407 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 408 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 409 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 410 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 411 412 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 413 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 414 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 415 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 416 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 417 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 418 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 419 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 420 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 421 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 422 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 423 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 424 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 425 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 426 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 427 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 428 429 #define CONFIG_MII /* MII PHY management */ 430 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 431 432 #endif 433 434 #include <asm/fsl_secure_boot.h> 435 436 #endif /* __LS2_QDS_H */ 437
