1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // A Disassembler object is used to disassemble a block of code instruction by 6 // instruction. The default implementation of the NameConverter object can be 7 // overriden to modify register names or to do symbol lookup on addresses. 8 // 9 // The example below will disassemble a block of code and print it to stdout. 10 // 11 // NameConverter converter; 12 // Disassembler d(converter); 13 // for (byte* pc = begin; pc < end;) { 14 // v8::internal::EmbeddedVector<char, 256> buffer; 15 // byte* prev_pc = pc; 16 // pc += d.InstructionDecode(buffer, pc); 17 // printf("%p %08x %s\n", 18 // prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer); 19 // } 20 // 21 // The Disassembler class also has a convenience method to disassemble a block 22 // of code into a FILE*, meaning that the above functionality could also be 23 // achieved by just calling Disassembler::Disassemble(stdout, begin, end); 24 25 #include <assert.h> 26 #include <stdarg.h> 27 #include <stdio.h> 28 #include <string.h> 29 30 #if V8_TARGET_ARCH_S390 31 32 #include "src/base/platform/platform.h" 33 #include "src/disasm.h" 34 #include "src/macro-assembler.h" 35 #include "src/s390/constants-s390.h" 36 37 namespace v8 { 38 namespace internal { 39 40 const auto GetRegConfig = RegisterConfiguration::Default; 41 42 //------------------------------------------------------------------------------ 43 44 // Decoder decodes and disassembles instructions into an output buffer. 45 // It uses the converter to convert register names and call destinations into 46 // more informative description. 47 class Decoder { 48 public: 49 Decoder(const disasm::NameConverter& converter, Vector<char> out_buffer) 50 : converter_(converter), out_buffer_(out_buffer), out_buffer_pos_(0) { 51 out_buffer_[out_buffer_pos_] = '\0'; 52 } 53 54 ~Decoder() {} 55 56 // Writes one disassembled instruction into 'buffer' (0-terminated). 57 // Returns the length of the disassembled machine instruction in bytes. 58 int InstructionDecode(byte* instruction); 59 60 private: 61 // Bottleneck functions to print into the out_buffer. 62 void PrintChar(const char ch); 63 void Print(const char* str); 64 65 // Printing of common values. 66 void PrintRegister(int reg); 67 void PrintDRegister(int reg); 68 void PrintSoftwareInterrupt(SoftwareInterruptCodes svc); 69 70 // Handle formatting of instructions and their options. 71 int FormatRegister(Instruction* instr, const char* option); 72 int FormatFloatingRegister(Instruction* instr, const char* option); 73 int FormatMask(Instruction* instr, const char* option); 74 int FormatDisplacement(Instruction* instr, const char* option); 75 int FormatImmediate(Instruction* instr, const char* option); 76 int FormatOption(Instruction* instr, const char* option); 77 void Format(Instruction* instr, const char* format); 78 void Unknown(Instruction* instr); 79 void UnknownFormat(Instruction* instr, const char* opcname); 80 81 bool DecodeSpecial(Instruction* instr); 82 bool DecodeGeneric(Instruction* instr); 83 84 const disasm::NameConverter& converter_; 85 Vector<char> out_buffer_; 86 int out_buffer_pos_; 87 88 DISALLOW_COPY_AND_ASSIGN(Decoder); 89 }; 90 91 // Support for assertions in the Decoder formatting functions. 92 #define STRING_STARTS_WITH(string, compare_string) \ 93 (strncmp(string, compare_string, strlen(compare_string)) == 0) 94 95 // Append the ch to the output buffer. 96 void Decoder::PrintChar(const char ch) { out_buffer_[out_buffer_pos_++] = ch; } 97 98 // Append the str to the output buffer. 99 void Decoder::Print(const char* str) { 100 char cur = *str++; 101 while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) { 102 PrintChar(cur); 103 cur = *str++; 104 } 105 out_buffer_[out_buffer_pos_] = 0; 106 } 107 108 // Print the register name according to the active name converter. 109 void Decoder::PrintRegister(int reg) { 110 Print(converter_.NameOfCPURegister(reg)); 111 } 112 113 // Print the double FP register name according to the active name converter. 114 void Decoder::PrintDRegister(int reg) { 115 Print(GetRegConfig()->GetDoubleRegisterName(reg)); 116 } 117 118 // Print SoftwareInterrupt codes. Factoring this out reduces the complexity of 119 // the FormatOption method. 120 void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) { 121 switch (svc) { 122 case kCallRtRedirected: 123 Print("call rt redirected"); 124 return; 125 case kBreakpoint: 126 Print("breakpoint"); 127 return; 128 default: 129 if (svc >= kStopCode) { 130 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d - 0x%x", 131 svc & kStopCodeMask, svc & kStopCodeMask); 132 } else { 133 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", svc); 134 } 135 return; 136 } 137 } 138 139 // Handle all register based formatting in this function to reduce the 140 // complexity of FormatOption. 141 int Decoder::FormatRegister(Instruction* instr, const char* format) { 142 DCHECK_EQ(format[0], 'r'); 143 144 if (format[1] == '1') { // 'r1: register resides in bit 8-11 145 int reg = instr->Bits<SixByteInstr, int>(39, 36); 146 PrintRegister(reg); 147 return 2; 148 } else if (format[1] == '2') { // 'r2: register resides in bit 12-15 149 int reg = instr->Bits<SixByteInstr, int>(35, 32); 150 // indicating it is a r0 for displacement, in which case the offset 151 // should be 0. 152 if (format[2] == 'd') { 153 if (reg == 0) return 4; 154 PrintRegister(reg); 155 return 3; 156 } else { 157 PrintRegister(reg); 158 return 2; 159 } 160 } else if (format[1] == '3') { // 'r3: register resides in bit 16-19 161 int reg = instr->Bits<SixByteInstr, int>(31, 28); 162 PrintRegister(reg); 163 return 2; 164 } else if (format[1] == '4') { // 'r4: register resides in bit 20-23 165 int reg = instr->Bits<SixByteInstr, int>(27, 24); 166 PrintRegister(reg); 167 return 2; 168 } else if (format[1] == '5') { // 'r5: register resides in bit 24-27 169 int reg = instr->Bits<SixByteInstr, int>(23, 20); 170 PrintRegister(reg); 171 return 2; 172 } else if (format[1] == '6') { // 'r6: register resides in bit 28-31 173 int reg = instr->Bits<SixByteInstr, int>(19, 16); 174 PrintRegister(reg); 175 return 2; 176 } else if (format[1] == '7') { // 'r6: register resides in bit 32-35 177 int reg = instr->Bits<SixByteInstr, int>(15, 12); 178 PrintRegister(reg); 179 return 2; 180 } 181 182 UNREACHABLE(); 183 } 184 185 int Decoder::FormatFloatingRegister(Instruction* instr, const char* format) { 186 DCHECK_EQ(format[0], 'f'); 187 188 // reuse 1, 5 and 6 because it is coresponding 189 if (format[1] == '1') { // 'r1: register resides in bit 8-11 190 RRInstruction* rrinstr = reinterpret_cast<RRInstruction*>(instr); 191 int reg = rrinstr->R1Value(); 192 PrintDRegister(reg); 193 return 2; 194 } else if (format[1] == '2') { // 'f2: register resides in bit 12-15 195 RRInstruction* rrinstr = reinterpret_cast<RRInstruction*>(instr); 196 int reg = rrinstr->R2Value(); 197 PrintDRegister(reg); 198 return 2; 199 } else if (format[1] == '3') { // 'f3: register resides in bit 16-19 200 RRDInstruction* rrdinstr = reinterpret_cast<RRDInstruction*>(instr); 201 int reg = rrdinstr->R1Value(); 202 PrintDRegister(reg); 203 return 2; 204 } else if (format[1] == '5') { // 'f5: register resides in bit 24-28 205 RREInstruction* rreinstr = reinterpret_cast<RREInstruction*>(instr); 206 int reg = rreinstr->R1Value(); 207 PrintDRegister(reg); 208 return 2; 209 } else if (format[1] == '6') { // 'f6: register resides in bit 29-32 210 RREInstruction* rreinstr = reinterpret_cast<RREInstruction*>(instr); 211 int reg = rreinstr->R2Value(); 212 PrintDRegister(reg); 213 return 2; 214 } 215 UNREACHABLE(); 216 } 217 218 // FormatOption takes a formatting string and interprets it based on 219 // the current instructions. The format string points to the first 220 // character of the option string (the option escape has already been 221 // consumed by the caller.) FormatOption returns the number of 222 // characters that were consumed from the formatting string. 223 int Decoder::FormatOption(Instruction* instr, const char* format) { 224 switch (format[0]) { 225 case 'o': { 226 if (instr->Bit(10) == 1) { 227 Print("o"); 228 } 229 return 1; 230 } 231 case '.': { 232 if (instr->Bit(0) == 1) { 233 Print("."); 234 } else { 235 Print(" "); // ensure consistent spacing 236 } 237 return 1; 238 } 239 case 'r': { 240 return FormatRegister(instr, format); 241 } 242 case 'f': { 243 return FormatFloatingRegister(instr, format); 244 } 245 case 'i': { // int16 246 return FormatImmediate(instr, format); 247 } 248 case 'u': { // uint16 249 int32_t value = instr->Bits(15, 0); 250 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 251 return 6; 252 } 253 case 'l': { 254 // Link (LK) Bit 0 255 if (instr->Bit(0) == 1) { 256 Print("l"); 257 } 258 return 1; 259 } 260 case 'a': { 261 // Absolute Address Bit 1 262 if (instr->Bit(1) == 1) { 263 Print("a"); 264 } 265 return 1; 266 } 267 case 't': { // 'target: target of branch instructions 268 // target26 or target16 269 DCHECK(STRING_STARTS_WITH(format, "target")); 270 if ((format[6] == '2') && (format[7] == '6')) { 271 int off = ((instr->Bits(25, 2)) << 8) >> 6; 272 out_buffer_pos_ += SNPrintF( 273 out_buffer_ + out_buffer_pos_, "%+d -> %s", off, 274 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off)); 275 return 8; 276 } else if ((format[6] == '1') && (format[7] == '6')) { 277 int off = ((instr->Bits(15, 2)) << 18) >> 16; 278 out_buffer_pos_ += SNPrintF( 279 out_buffer_ + out_buffer_pos_, "%+d -> %s", off, 280 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off)); 281 return 8; 282 } 283 break; 284 case 'm': { 285 return FormatMask(instr, format); 286 } 287 } 288 case 'd': { // ds value for offset 289 return FormatDisplacement(instr, format); 290 } 291 default: { 292 UNREACHABLE(); 293 break; 294 } 295 } 296 297 UNREACHABLE(); 298 } 299 300 int Decoder::FormatMask(Instruction* instr, const char* format) { 301 DCHECK_EQ(format[0], 'm'); 302 int32_t value = 0; 303 if ((format[1] == '1')) { // prints the mask format in bits 8-12 304 value = reinterpret_cast<RRInstruction*>(instr)->R1Value(); 305 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value); 306 return 2; 307 } else if (format[1] == '2') { // mask format in bits 16-19 308 value = reinterpret_cast<RXInstruction*>(instr)->B2Value(); 309 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value); 310 return 2; 311 } else if (format[1] == '3') { // mask format in bits 20-23 312 value = reinterpret_cast<RRFInstruction*>(instr)->M4Value(); 313 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value); 314 return 2; 315 } 316 317 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 318 return 2; 319 } 320 321 int Decoder::FormatDisplacement(Instruction* instr, const char* format) { 322 DCHECK_EQ(format[0], 'd'); 323 324 if (format[1] == '1') { // displacement in 20-31 325 RSInstruction* rsinstr = reinterpret_cast<RSInstruction*>(instr); 326 uint16_t value = rsinstr->D2Value(); 327 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 328 329 return 2; 330 } else if (format[1] == '2') { // displacement in 20-39 331 RXYInstruction* rxyinstr = reinterpret_cast<RXYInstruction*>(instr); 332 int32_t value = rxyinstr->D2Value(); 333 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 334 return 2; 335 } else if (format[1] == '4') { // SS displacement 2 36-47 336 SSInstruction* ssInstr = reinterpret_cast<SSInstruction*>(instr); 337 uint16_t value = ssInstr->D2Value(); 338 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 339 return 2; 340 } else if (format[1] == '3') { // SS displacement 1 20 - 32 341 SSInstruction* ssInstr = reinterpret_cast<SSInstruction*>(instr); 342 uint16_t value = ssInstr->D1Value(); 343 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 344 return 2; 345 } else { // s390 specific 346 int32_t value = SIGN_EXT_IMM16(instr->Bits(15, 0) & ~3); 347 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 348 return 1; 349 } 350 } 351 352 int Decoder::FormatImmediate(Instruction* instr, const char* format) { 353 DCHECK_EQ(format[0], 'i'); 354 355 if (format[1] == '1') { // immediate in 16-31 356 RIInstruction* riinstr = reinterpret_cast<RIInstruction*>(instr); 357 int16_t value = riinstr->I2Value(); 358 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 359 return 2; 360 } else if (format[1] == '2') { // immediate in 16-48 361 RILInstruction* rilinstr = reinterpret_cast<RILInstruction*>(instr); 362 int32_t value = rilinstr->I2Value(); 363 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 364 return 2; 365 } else if (format[1] == '3') { // immediate in I format 366 IInstruction* iinstr = reinterpret_cast<IInstruction*>(instr); 367 int8_t value = iinstr->IValue(); 368 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 369 return 2; 370 } else if (format[1] == '4') { // immediate in 16-31, but outputs as offset 371 RIInstruction* riinstr = reinterpret_cast<RIInstruction*>(instr); 372 int16_t value = riinstr->I2Value() * 2; 373 if (value >= 0) 374 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "*+"); 375 else 376 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "*"); 377 378 out_buffer_pos_ += SNPrintF( 379 out_buffer_ + out_buffer_pos_, "%d -> %s", value, 380 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + value)); 381 return 2; 382 } else if (format[1] == '5') { // immediate in 16-31, but outputs as offset 383 RILInstruction* rilinstr = reinterpret_cast<RILInstruction*>(instr); 384 int32_t value = rilinstr->I2Value() * 2; 385 if (value >= 0) 386 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "*+"); 387 else 388 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "*"); 389 390 out_buffer_pos_ += SNPrintF( 391 out_buffer_ + out_buffer_pos_, "%d -> %s", value, 392 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + value)); 393 return 2; 394 } else if (format[1] == '6') { // unsigned immediate in 16-31 395 RIInstruction* riinstr = reinterpret_cast<RIInstruction*>(instr); 396 uint16_t value = riinstr->I2UnsignedValue(); 397 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 398 return 2; 399 } else if (format[1] == '7') { // unsigned immediate in 16-47 400 RILInstruction* rilinstr = reinterpret_cast<RILInstruction*>(instr); 401 uint32_t value = rilinstr->I2UnsignedValue(); 402 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 403 return 2; 404 } else if (format[1] == '8') { // unsigned immediate in 8-15 405 SSInstruction* ssinstr = reinterpret_cast<SSInstruction*>(instr); 406 uint8_t value = ssinstr->Length(); 407 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 408 return 2; 409 } else if (format[1] == '9') { // unsigned immediate in 16-23 410 RIEInstruction* rie_instr = reinterpret_cast<RIEInstruction*>(instr); 411 uint8_t value = rie_instr->I3Value(); 412 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 413 return 2; 414 } else if (format[1] == 'a') { // unsigned immediate in 24-31 415 RIEInstruction* rie_instr = reinterpret_cast<RIEInstruction*>(instr); 416 uint8_t value = rie_instr->I4Value(); 417 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 418 return 2; 419 } else if (format[1] == 'b') { // unsigned immediate in 32-39 420 RIEInstruction* rie_instr = reinterpret_cast<RIEInstruction*>(instr); 421 uint8_t value = rie_instr->I5Value(); 422 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 423 return 2; 424 } else if (format[1] == 'c') { // signed immediate in 8-15 425 SSInstruction* ssinstr = reinterpret_cast<SSInstruction*>(instr); 426 int8_t value = ssinstr->Length(); 427 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 428 return 2; 429 } else if (format[1] == 'd') { // signed immediate in 32-47 430 SILInstruction* silinstr = reinterpret_cast<SILInstruction*>(instr); 431 int16_t value = silinstr->I2Value(); 432 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 433 return 2; 434 } else if (format[1] == 'e') { // immediate in 16-47, but outputs as offset 435 RILInstruction* rilinstr = reinterpret_cast<RILInstruction*>(instr); 436 int32_t value = rilinstr->I2Value() * 2; 437 if (value >= 0) 438 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "*+"); 439 else 440 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "*"); 441 442 out_buffer_pos_ += SNPrintF( 443 out_buffer_ + out_buffer_pos_, "%d -> %s", value, 444 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + value)); 445 return 2; 446 } 447 448 UNREACHABLE(); 449 } 450 451 // Format takes a formatting string for a whole instruction and prints it into 452 // the output buffer. All escaped options are handed to FormatOption to be 453 // parsed further. 454 void Decoder::Format(Instruction* instr, const char* format) { 455 char cur = *format++; 456 while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) { 457 if (cur == '\'') { // Single quote is used as the formatting escape. 458 format += FormatOption(instr, format); 459 } else { 460 out_buffer_[out_buffer_pos_++] = cur; 461 } 462 cur = *format++; 463 } 464 out_buffer_[out_buffer_pos_] = '\0'; 465 } 466 467 // The disassembler may end up decoding data inlined in the code. We do not want 468 // it to crash if the data does not resemble any known instruction. 469 #define VERIFY(condition) \ 470 if (!(condition)) { \ 471 Unknown(instr); \ 472 return; \ 473 } 474 475 // For currently unimplemented decodings the disassembler calls Unknown(instr) 476 // which will just print "unknown" of the instruction bits. 477 void Decoder::Unknown(Instruction* instr) { Format(instr, "unknown"); } 478 479 // For currently unimplemented decodings the disassembler calls 480 // UnknownFormat(instr) which will just print opcode name of the 481 // instruction bits. 482 void Decoder::UnknownFormat(Instruction* instr, const char* name) { 483 char buffer[100]; 484 snprintf(buffer, sizeof(buffer), "%s (unknown-format)", name); 485 Format(instr, buffer); 486 } 487 488 #undef VERIFY 489 #undef STRING_STARTS_WITH 490 491 // Handles special cases of instructions; 492 // @return true if successfully decoded 493 bool Decoder::DecodeSpecial(Instruction* instr) { 494 Opcode opcode = instr->S390OpcodeValue(); 495 switch (opcode) { 496 case BKPT: 497 Format(instr, "bkpt"); 498 break; 499 case DUMY: 500 Format(instr, "dumy\t'r1, 'd2 ( 'r2d, 'r3 )"); 501 break; 502 /* RR format */ 503 case LDR: 504 Format(instr, "ldr\t'f1,'f2"); 505 break; 506 case BCR: 507 Format(instr, "bcr\t'm1,'r2"); 508 break; 509 case OR: 510 Format(instr, "or\t'r1,'r2"); 511 break; 512 case CR: 513 Format(instr, "cr\t'r1,'r2"); 514 break; 515 case MR: 516 Format(instr, "mr\t'r1,'r2"); 517 break; 518 case HER_Z: 519 Format(instr, "her\t'r1,'r2"); 520 break; 521 /* RI-b format */ 522 case BRAS: 523 Format(instr, "bras\t'r1,'i1"); 524 break; 525 /* RRE format */ 526 case MDBR: 527 Format(instr, "mdbr\t'f5,'f6"); 528 break; 529 case SDBR: 530 Format(instr, "sdbr\t'f5,'f6"); 531 break; 532 case ADBR: 533 Format(instr, "adbr\t'f5,'f6"); 534 break; 535 case CDBR: 536 Format(instr, "cdbr\t'f5,'f6"); 537 break; 538 case MEEBR: 539 Format(instr, "meebr\t'f5,'f6"); 540 break; 541 case SQDBR: 542 Format(instr, "sqdbr\t'f5,'f6"); 543 break; 544 case SQEBR: 545 Format(instr, "sqebr\t'f5,'f6"); 546 break; 547 case LCDBR: 548 Format(instr, "lcdbr\t'f5,'f6"); 549 break; 550 case LCEBR: 551 Format(instr, "lcebr\t'f5,'f6"); 552 break; 553 case LTEBR: 554 Format(instr, "ltebr\t'f5,'f6"); 555 break; 556 case LDEBR: 557 Format(instr, "ldebr\t'f5,'f6"); 558 break; 559 case CEBR: 560 Format(instr, "cebr\t'f5,'f6"); 561 break; 562 case AEBR: 563 Format(instr, "aebr\t'f5,'f6"); 564 break; 565 case SEBR: 566 Format(instr, "sebr\t'f5,'f6"); 567 break; 568 case DEBR: 569 Format(instr, "debr\t'f5,'f6"); 570 break; 571 case LTDBR: 572 Format(instr, "ltdbr\t'f5,'f6"); 573 break; 574 case LDGR: 575 Format(instr, "ldgr\t'f5,'f6"); 576 break; 577 case DDBR: 578 Format(instr, "ddbr\t'f5,'f6"); 579 break; 580 case LZDR: 581 Format(instr, "lzdr\t'f5"); 582 break; 583 /* RRF-e format */ 584 case FIEBRA: 585 Format(instr, "fiebra\t'f5,'m2,'f6,'m3"); 586 break; 587 case FIDBRA: 588 Format(instr, "fidbra\t'f5,'m2,'f6,'m3"); 589 break; 590 /* RX-a format */ 591 case IC_z: 592 Format(instr, "ic\t'r1,'d1('r2d,'r3)"); 593 break; 594 case AL: 595 Format(instr, "al\t'r1,'d1('r2d,'r3)"); 596 break; 597 case LE: 598 Format(instr, "le\t'f1,'d1('r2d,'r3)"); 599 break; 600 case LD: 601 Format(instr, "ld\t'f1,'d1('r2d,'r3)"); 602 break; 603 case STE: 604 Format(instr, "ste\t'f1,'d1('r2d,'r3)"); 605 break; 606 case STD: 607 Format(instr, "std\t'f1,'d1('r2d,'r3)"); 608 break; 609 /* S format */ 610 // TRAP4 is used in calling to native function. it will not be generated 611 // in native code. 612 case TRAP4: 613 Format(instr, "trap4"); 614 break; 615 /* RIL-a format */ 616 case CFI: 617 Format(instr, "cfi\t'r1,'i2"); 618 break; 619 case CGFI: 620 Format(instr, "cgfi\t'r1,'i2"); 621 break; 622 case AFI: 623 Format(instr, "afi\t'r1,'i2"); 624 break; 625 case AGFI: 626 Format(instr, "agfi\t'r1,'i2"); 627 break; 628 case MSFI: 629 Format(instr, "msfi\t'r1,'i2"); 630 break; 631 case MSGFI: 632 Format(instr, "msgfi\t'r1,'i2"); 633 break; 634 case ALSIH: 635 Format(instr, "alsih\t'r1,'i2"); 636 break; 637 case ALSIHN: 638 Format(instr, "alsihn\t'r1,'i2"); 639 break; 640 case CIH: 641 Format(instr, "cih\t'r1,'i2"); 642 break; 643 case AIH: 644 Format(instr, "aih\t'r1,'i2"); 645 break; 646 case LGFI: 647 Format(instr, "lgfi\t'r1,'i2"); 648 break; 649 /* SIY format */ 650 case ASI: 651 Format(instr, "asi\t'd2('r3),'ic"); 652 break; 653 case AGSI: 654 Format(instr, "agsi\t'd2('r3),'ic"); 655 break; 656 /* RXY-a format */ 657 case LT: 658 Format(instr, "lt\t'r1,'d2('r2d,'r3)"); 659 break; 660 case LDY: 661 Format(instr, "ldy\t'f1,'d2('r2d,'r3)"); 662 break; 663 case LEY: 664 Format(instr, "ley\t'f1,'d2('r2d,'r3)"); 665 break; 666 case STDY: 667 Format(instr, "stdy\t'f1,'d2('r2d,'r3)"); 668 break; 669 case STEY: 670 Format(instr, "stey\t'f1,'d2('r2d,'r3)"); 671 break; 672 /* RXE format */ 673 case LDEB: 674 Format(instr, "ldeb\t'f1,'d2('r2d,'r3)"); 675 break; 676 default: 677 return false; 678 } 679 return true; 680 } 681 682 // Handles common cases of instructions; 683 // @return true if successfully decoded 684 bool Decoder::DecodeGeneric(Instruction* instr) { 685 Opcode opcode = instr->S390OpcodeValue(); 686 switch (opcode) { 687 /* 2 bytes */ 688 #define DECODE_RR_INSTRUCTIONS(name, opcode_name, opcode_value) \ 689 case opcode_name: \ 690 Format(instr, #name "\t'r1,'r2"); \ 691 break; 692 S390_RR_OPCODE_LIST(DECODE_RR_INSTRUCTIONS) 693 #undef DECODE_RR_INSTRUCTIONS 694 695 /* 4 bytes */ 696 #define DECODE_RS_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 697 case opcode_name: \ 698 Format(instr, #name "\t'r1,'r2,'d1('r3)"); \ 699 break; 700 S390_RS_A_OPCODE_LIST(DECODE_RS_A_INSTRUCTIONS) 701 #undef DECODE_RS_A_INSTRUCTIONS 702 703 #define DECODE_RSI_INSTRUCTIONS(name, opcode_name, opcode_value) \ 704 case opcode_name: \ 705 Format(instr, #name "\t'r1,'r2,'i4"); \ 706 break; 707 S390_RSI_OPCODE_LIST(DECODE_RSI_INSTRUCTIONS) 708 #undef DECODE_RSI_INSTRUCTIONS 709 710 #define DECODE_RI_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 711 case opcode_name: \ 712 Format(instr, #name "\t'r1,'i1"); \ 713 break; 714 S390_RI_A_OPCODE_LIST(DECODE_RI_A_INSTRUCTIONS) 715 #undef DECODE_RI_A_INSTRUCTIONS 716 717 #define DECODE_RI_B_INSTRUCTIONS(name, opcode_name, opcode_value) \ 718 case opcode_name: \ 719 Format(instr, #name "\t'r1,'i4"); \ 720 break; 721 S390_RI_B_OPCODE_LIST(DECODE_RI_B_INSTRUCTIONS) 722 #undef DECODE_RI_B_INSTRUCTIONS 723 724 #define DECODE_RI_C_INSTRUCTIONS(name, opcode_name, opcode_value) \ 725 case opcode_name: \ 726 Format(instr, #name "\t'm1,'i4"); \ 727 break; 728 S390_RI_C_OPCODE_LIST(DECODE_RI_C_INSTRUCTIONS) 729 #undef DECODE_RI_C_INSTRUCTIONS 730 731 #define DECODE_RRE_INSTRUCTIONS(name, opcode_name, opcode_value) \ 732 case opcode_name: \ 733 Format(instr, #name "\t'r5,'r6"); \ 734 break; 735 S390_RRE_OPCODE_LIST(DECODE_RRE_INSTRUCTIONS) 736 #undef DECODE_RRE_INSTRUCTIONS 737 738 #define DECODE_RRF_A_INSTRUCTIONS(name, opcode_name, opcode_val) \ 739 case opcode_name: \ 740 Format(instr, #name "\t'r5,'r6,'r3"); \ 741 break; 742 S390_RRF_A_OPCODE_LIST(DECODE_RRF_A_INSTRUCTIONS) 743 #undef DECODE_RRF_A_INSTRUCTIONS 744 745 #define DECODE_RRF_C_INSTRUCTIONS(name, opcode_name, opcode_val) \ 746 case opcode_name: \ 747 Format(instr, #name "\t'r5,'r6,'m2"); \ 748 break; 749 S390_RRF_C_OPCODE_LIST(DECODE_RRF_C_INSTRUCTIONS) 750 #undef DECODE_RRF_C_INSTRUCTIONS 751 752 #define DECODE_RRF_E_INSTRUCTIONS(name, opcode_name, opcode_val) \ 753 case opcode_name: \ 754 Format(instr, #name "\t'r5,'m2,'f6"); \ 755 break; 756 S390_RRF_E_OPCODE_LIST(DECODE_RRF_E_INSTRUCTIONS) 757 #undef DECODE_RRF_E_INSTRUCTIONS 758 759 #define DECODE_RX_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 760 case opcode_name: \ 761 Format(instr, #name "\t'r1,'d1('r2d,'r3)"); \ 762 break; 763 S390_RX_A_OPCODE_LIST(DECODE_RX_A_INSTRUCTIONS) 764 #undef DECODE_RX_A_INSTRUCTIONS 765 766 #define DECODE_RX_B_INSTRUCTIONS(name, opcode_name, opcode_value) \ 767 case opcode_name: \ 768 Format(instr, #name "\t'm1,'d1('r2d,'r3)"); \ 769 break; 770 S390_RX_B_OPCODE_LIST(DECODE_RX_B_INSTRUCTIONS) 771 #undef DECODE_RX_B_INSTRUCTIONS 772 773 #define DECODE_RRD_INSTRUCTIONS(name, opcode_name, opcode_value) \ 774 case opcode_name: \ 775 Format(instr, #name "\t'f3,'f5,'f6"); \ 776 break; 777 S390_RRD_OPCODE_LIST(DECODE_RRD_INSTRUCTIONS) 778 #undef DECODE_RRD_INSTRUCTIONS 779 780 #define DECODE_SI_INSTRUCTIONS(name, opcode_name, opcode_value) \ 781 case opcode_name: \ 782 Format(instr, #name "\t'd1('r3),'i8"); \ 783 break; 784 S390_SI_OPCODE_LIST(DECODE_SI_INSTRUCTIONS) 785 #undef DECODE_SI_INSTRUCTIONS 786 787 /* 6 bytes */ 788 #define DECODE_VRR_C_INSTRUCTIONS(name, opcode_name, opcode_value) \ 789 case opcode_name: \ 790 Format(instr, #name "\t'f1,'f2,'f3"); \ 791 break; 792 S390_VRR_C_OPCODE_LIST(DECODE_VRR_C_INSTRUCTIONS) 793 #undef DECODE_VRR_C_INSTRUCTIONS 794 795 #define DECODE_RIL_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 796 case opcode_name: \ 797 Format(instr, #name "\t'r1,'i7"); \ 798 break; 799 S390_RIL_A_OPCODE_LIST(DECODE_RIL_A_INSTRUCTIONS) 800 #undef DECODE_RIL_A_INSTRUCTIONS 801 802 #define DECODE_RIL_B_INSTRUCTIONS(name, opcode_name, opcode_value) \ 803 case opcode_name: \ 804 Format(instr, #name "\t'r1,'ie"); \ 805 break; 806 S390_RIL_B_OPCODE_LIST(DECODE_RIL_B_INSTRUCTIONS) 807 #undef DECODE_RIL_B_INSTRUCTIONS 808 809 #define DECODE_RIL_C_INSTRUCTIONS(name, opcode_name, opcode_value) \ 810 case opcode_name: \ 811 Format(instr, #name "\t'm1,'ie"); \ 812 break; 813 S390_RIL_C_OPCODE_LIST(DECODE_RIL_C_INSTRUCTIONS) 814 #undef DECODE_RIL_C_INSTRUCTIONS 815 816 #define DECODE_SIY_INSTRUCTIONS(name, opcode_name, opcode_value) \ 817 case opcode_name: \ 818 Format(instr, #name "\t'd2('r3),'i8"); \ 819 break; 820 S390_SIY_OPCODE_LIST(DECODE_SIY_INSTRUCTIONS) 821 #undef DECODE_SIY_INSTRUCTIONS 822 823 #define DECODE_RIE_D_INSTRUCTIONS(name, opcode_name, opcode_value) \ 824 case opcode_name: \ 825 Format(instr, #name "\t'r1,'r2,'i1"); \ 826 break; 827 S390_RIE_D_OPCODE_LIST(DECODE_RIE_D_INSTRUCTIONS) 828 #undef DECODE_RIE_D_INSTRUCTIONS 829 830 #define DECODE_RIE_E_INSTRUCTIONS(name, opcode_name, opcode_value) \ 831 case opcode_name: \ 832 Format(instr, #name "\t'r1,'r2,'i4"); \ 833 break; 834 S390_RIE_E_OPCODE_LIST(DECODE_RIE_E_INSTRUCTIONS) 835 #undef DECODE_RIE_E_INSTRUCTIONS 836 837 #define DECODE_RIE_F_INSTRUCTIONS(name, opcode_name, opcode_value) \ 838 case opcode_name: \ 839 Format(instr, #name "\t'r1,'r2,'i9,'ia,'ib"); \ 840 break; 841 S390_RIE_F_OPCODE_LIST(DECODE_RIE_F_INSTRUCTIONS) 842 #undef DECODE_RIE_F_INSTRUCTIONS 843 844 #define DECODE_RSY_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 845 case opcode_name: \ 846 Format(instr, #name "\t'r1,'r2,'d2('r3)"); \ 847 break; 848 S390_RSY_A_OPCODE_LIST(DECODE_RSY_A_INSTRUCTIONS) 849 #undef DECODE_RSY_A_INSTRUCTIONS 850 851 #define DECODE_RSY_B_INSTRUCTIONS(name, opcode_name, opcode_value) \ 852 case opcode_name: \ 853 Format(instr, #name "\t'm2,'r1,'d2('r3)"); \ 854 break; 855 S390_RSY_B_OPCODE_LIST(DECODE_RSY_B_INSTRUCTIONS) 856 #undef DECODE_RSY_B_INSTRUCTIONS 857 858 #define DECODE_RXY_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 859 case opcode_name: \ 860 Format(instr, #name "\t'r1,'d2('r2d,'r3)"); \ 861 break; 862 S390_RXY_A_OPCODE_LIST(DECODE_RXY_A_INSTRUCTIONS) 863 #undef DECODE_RXY_A_INSTRUCTIONS 864 865 #define DECODE_RXY_B_INSTRUCTIONS(name, opcode_name, opcode_value) \ 866 case opcode_name: \ 867 Format(instr, #name "\t'm1,'d2('r2d,'r3)"); \ 868 break; 869 S390_RXY_B_OPCODE_LIST(DECODE_RXY_B_INSTRUCTIONS) 870 #undef DECODE_RXY_B_INSTRUCTIONS 871 872 #define DECODE_RXE_INSTRUCTIONS(name, opcode_name, opcode_value) \ 873 case opcode_name: \ 874 Format(instr, #name "\t'f1,'d1('r2d, 'r3)"); \ 875 break; 876 S390_RXE_OPCODE_LIST(DECODE_RXE_INSTRUCTIONS) 877 #undef DECODE_RXE_INSTRUCTIONS 878 879 #define DECODE_SIL_INSTRUCTIONS(name, opcode_name, opcode_value) \ 880 case opcode_name: \ 881 Format(instr, #name "\t'd3('r3),'id"); \ 882 break; 883 S390_SIL_OPCODE_LIST(DECODE_SIL_INSTRUCTIONS) 884 #undef DECODE_SIL_INSTRUCTIONS 885 886 #define DECODE_SS_A_INSTRUCTIONS(name, opcode_name, opcode_value) \ 887 case opcode_name: \ 888 Format(instr, #name "\t'd3('i8,'r3),'d4('r7)"); \ 889 break; 890 S390_SS_A_OPCODE_LIST(DECODE_SS_A_INSTRUCTIONS) 891 #undef DECODE_SS_A_INSTRUCTIONS 892 893 default: 894 return false; 895 } 896 return true; 897 } 898 899 // Disassemble the instruction at *instr_ptr into the output buffer. 900 int Decoder::InstructionDecode(byte* instr_ptr) { 901 Instruction* instr = Instruction::At(instr_ptr); 902 int instrLength = instr->InstructionLength(); 903 904 // Print the Instruction bits. 905 if (instrLength == 2) { 906 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, 907 "%04x ", instr->InstructionBits<TwoByteInstr>()); 908 } else if (instrLength == 4) { 909 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, 910 "%08x ", instr->InstructionBits<FourByteInstr>()); 911 } else { 912 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, 913 "%012" PRIx64 " ", instr->InstructionBits<SixByteInstr>()); 914 } 915 916 bool decoded = DecodeSpecial(instr); 917 if (!decoded) 918 decoded = DecodeGeneric(instr); 919 if (!decoded) 920 Unknown(instr); 921 return instrLength; 922 } 923 924 } // namespace internal 925 } // namespace v8 926 927 //------------------------------------------------------------------------------ 928 929 namespace disasm { 930 931 const char* NameConverter::NameOfAddress(byte* addr) const { 932 v8::internal::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr)); 933 return tmp_buffer_.start(); 934 } 935 936 const char* NameConverter::NameOfConstant(byte* addr) const { 937 return NameOfAddress(addr); 938 } 939 940 const char* NameConverter::NameOfCPURegister(int reg) const { 941 return v8::internal::GetRegConfig()->GetGeneralRegisterName(reg); 942 } 943 944 const char* NameConverter::NameOfByteCPURegister(int reg) const { 945 UNREACHABLE(); // S390 does not have the concept of a byte register 946 return "nobytereg"; 947 } 948 949 const char* NameConverter::NameOfXMMRegister(int reg) const { 950 // S390 does not have XMM register 951 // TODO(joransiu): Consider update this for Vector Regs 952 UNREACHABLE(); 953 } 954 955 const char* NameConverter::NameInCode(byte* addr) const { 956 // The default name converter is called for unknown code. So we will not try 957 // to access any memory. 958 return ""; 959 } 960 961 //------------------------------------------------------------------------------ 962 963 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer, 964 byte* instruction) { 965 v8::internal::Decoder d(converter_, buffer); 966 return d.InstructionDecode(instruction); 967 } 968 969 // The S390 assembler does not currently use constant pools. 970 int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; } 971 972 void Disassembler::Disassemble(FILE* f, byte* begin, byte* end, 973 UnimplementedOpcodeAction unimplemented_action) { 974 NameConverter converter; 975 Disassembler d(converter, unimplemented_action); 976 for (byte* pc = begin; pc < end;) { 977 v8::internal::EmbeddedVector<char, 128> buffer; 978 buffer[0] = '\0'; 979 byte* prev_pc = pc; 980 pc += d.InstructionDecode(buffer, pc); 981 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), 982 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 983 } 984 } 985 986 } // namespace disasm 987 988 #endif // V8_TARGET_ARCH_S390 989
