Home | History | Annotate | Download | only in aarch32
      1 // Copyright 2016, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // -----------------------------------------------------------------------------
     29 // This file is auto generated from the
     30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using
     31 // tools/generate_tests.py.
     32 //
     33 // PLEASE DO NOT EDIT.
     34 // -----------------------------------------------------------------------------
     35 
     36 
     37 #include "test-runner.h"
     38 
     39 #include "test-utils.h"
     40 #include "test-utils-aarch32.h"
     41 
     42 #include "aarch32/assembler-aarch32.h"
     43 #include "aarch32/macro-assembler-aarch32.h"
     44 
     45 #define BUF_SIZE (4096)
     46 
     47 namespace vixl {
     48 namespace aarch32 {
     49 
     50 // List of instruction mnemonics.
     51 #define FOREACH_INSTRUCTION(M) \
     52   M(adc)                       \
     53   M(adcs)                      \
     54   M(add)                       \
     55   M(adds)                      \
     56   M(and_)                      \
     57   M(ands)                      \
     58   M(bic)                       \
     59   M(bics)                      \
     60   M(eor)                       \
     61   M(eors)                      \
     62   M(orr)                       \
     63   M(orrs)                      \
     64   M(rsb)                       \
     65   M(rsbs)                      \
     66   M(rsc)                       \
     67   M(rscs)                      \
     68   M(sbc)                       \
     69   M(sbcs)                      \
     70   M(sub)                       \
     71   M(subs)
     72 
     73 
     74 // The following definitions are defined again in each generated test, therefore
     75 // we need to place them in an anomymous namespace. It expresses that they are
     76 // local to this file only, and the compiler is not allowed to share these types
     77 // across test files during template instantiation. Specifically, `Operands` has
     78 // various layouts across generated tests so it absolutely cannot be shared.
     79 
     80 #ifdef VIXL_INCLUDE_TARGET_A32
     81 namespace {
     82 
     83 // Values to be passed to the assembler to produce the instruction under test.
     84 struct Operands {
     85   Condition cond;
     86   Register rd;
     87   Register rn;
     88   Register rm;
     89   ShiftType shift;
     90   uint32_t amount;
     91 };
     92 
     93 // This structure contains all data needed to test one specific
     94 // instruction.
     95 struct TestData {
     96   // The `operands` field represents what to pass to the assembler to
     97   // produce the instruction.
     98   Operands operands;
     99   // True if we need to generate an IT instruction for this test to be valid.
    100   bool in_it_block;
    101   // The condition to give the IT instruction, this will be set to "al" by
    102   // default.
    103   Condition it_condition;
    104   // Description of the operands, used for error reporting.
    105   const char* operands_description;
    106   // Unique identifier, used for generating traces.
    107   const char* identifier;
    108 };
    109 
    110 struct TestResult {
    111   size_t size;
    112   const byte* encoding;
    113 };
    114 
    115 // Each element of this array produce one instruction encoding.
    116 const TestData kTests[] = {{{eq, r13, r6, r7, ASR, 5},
    117                             false,
    118                             al,
    119                             "eq r13 r6 r7 ASR 5",
    120                             "eq_r13_r6_r7_ASR_5"},
    121                            {{mi, r8, r11, r8, ASR, 32},
    122                             false,
    123                             al,
    124                             "mi r8 r11 r8 ASR 32",
    125                             "mi_r8_r11_r8_ASR_32"},
    126                            {{hi, r2, r3, r10, ASR, 18},
    127                             false,
    128                             al,
    129                             "hi r2 r3 r10 ASR 18",
    130                             "hi_r2_r3_r10_ASR_18"},
    131                            {{ls, r13, r8, r14, LSR, 32},
    132                             false,
    133                             al,
    134                             "ls r13 r8 r14 LSR 32",
    135                             "ls_r13_r8_r14_LSR_32"},
    136                            {{cc, r8, r9, r2, ASR, 3},
    137                             false,
    138                             al,
    139                             "cc r8 r9 r2 ASR 3",
    140                             "cc_r8_r9_r2_ASR_3"},
    141                            {{ls, r14, r2, r5, LSR, 2},
    142                             false,
    143                             al,
    144                             "ls r14 r2 r5 LSR 2",
    145                             "ls_r14_r2_r5_LSR_2"},
    146                            {{pl, r8, r6, r1, ASR, 31},
    147                             false,
    148                             al,
    149                             "pl r8 r6 r1 ASR 31",
    150                             "pl_r8_r6_r1_ASR_31"},
    151                            {{le, r2, r0, r14, LSR, 3},
    152                             false,
    153                             al,
    154                             "le r2 r0 r14 LSR 3",
    155                             "le_r2_r0_r14_LSR_3"},
    156                            {{ne, r2, r0, r13, LSR, 15},
    157                             false,
    158                             al,
    159                             "ne r2 r0 r13 LSR 15",
    160                             "ne_r2_r0_r13_LSR_15"},
    161                            {{ge, r9, r12, r3, LSR, 8},
    162                             false,
    163                             al,
    164                             "ge r9 r12 r3 LSR 8",
    165                             "ge_r9_r12_r3_LSR_8"},
    166                            {{pl, r13, r8, r1, ASR, 7},
    167                             false,
    168                             al,
    169                             "pl r13 r8 r1 ASR 7",
    170                             "pl_r13_r8_r1_ASR_7"},
    171                            {{cs, r10, r13, r4, LSR, 5},
    172                             false,
    173                             al,
    174                             "cs r10 r13 r4 LSR 5",
    175                             "cs_r10_r13_r4_LSR_5"},
    176                            {{pl, r13, r8, r11, ASR, 17},
    177                             false,
    178                             al,
    179                             "pl r13 r8 r11 ASR 17",
    180                             "pl_r13_r8_r11_ASR_17"},
    181                            {{cs, r8, r7, r3, LSR, 9},
    182                             false,
    183                             al,
    184                             "cs r8 r7 r3 LSR 9",
    185                             "cs_r8_r7_r3_LSR_9"},
    186                            {{vc, r11, r2, r7, LSR, 30},
    187                             false,
    188                             al,
    189                             "vc r11 r2 r7 LSR 30",
    190                             "vc_r11_r2_r7_LSR_30"},
    191                            {{ge, r6, r14, r7, LSR, 19},
    192                             false,
    193                             al,
    194                             "ge r6 r14 r7 LSR 19",
    195                             "ge_r6_r14_r7_LSR_19"},
    196                            {{cc, r11, r3, r0, LSR, 20},
    197                             false,
    198                             al,
    199                             "cc r11 r3 r0 LSR 20",
    200                             "cc_r11_r3_r0_LSR_20"},
    201                            {{lt, r10, r9, r7, ASR, 25},
    202                             false,
    203                             al,
    204                             "lt r10 r9 r7 ASR 25",
    205                             "lt_r10_r9_r7_ASR_25"},
    206                            {{ne, r8, r0, r12, LSR, 30},
    207                             false,
    208                             al,
    209                             "ne r8 r0 r12 LSR 30",
    210                             "ne_r8_r0_r12_LSR_30"},
    211                            {{vc, r1, r4, r13, ASR, 32},
    212                             false,
    213                             al,
    214                             "vc r1 r4 r13 ASR 32",
    215                             "vc_r1_r4_r13_ASR_32"},
    216                            {{al, r8, r14, r8, LSR, 14},
    217                             false,
    218                             al,
    219                             "al r8 r14 r8 LSR 14",
    220                             "al_r8_r14_r8_LSR_14"},
    221                            {{pl, r2, r12, r7, ASR, 2},
    222                             false,
    223                             al,
    224                             "pl r2 r12 r7 ASR 2",
    225                             "pl_r2_r12_r7_ASR_2"},
    226                            {{pl, r11, r1, r0, LSR, 14},
    227                             false,
    228                             al,
    229                             "pl r11 r1 r0 LSR 14",
    230                             "pl_r11_r1_r0_LSR_14"},
    231                            {{gt, r5, r11, r9, ASR, 24},
    232                             false,
    233                             al,
    234                             "gt r5 r11 r9 ASR 24",
    235                             "gt_r5_r11_r9_ASR_24"},
    236                            {{eq, r8, r9, r12, ASR, 6},
    237                             false,
    238                             al,
    239                             "eq r8 r9 r12 ASR 6",
    240                             "eq_r8_r9_r12_ASR_6"},
    241                            {{cs, r10, r9, r12, LSR, 30},
    242                             false,
    243                             al,
    244                             "cs r10 r9 r12 LSR 30",
    245                             "cs_r10_r9_r12_LSR_30"},
    246                            {{lt, r7, r11, r2, ASR, 21},
    247                             false,
    248                             al,
    249                             "lt r7 r11 r2 ASR 21",
    250                             "lt_r7_r11_r2_ASR_21"},
    251                            {{eq, r14, r3, r11, LSR, 10},
    252                             false,
    253                             al,
    254                             "eq r14 r3 r11 LSR 10",
    255                             "eq_r14_r3_r11_LSR_10"},
    256                            {{vs, r4, r11, r5, ASR, 7},
    257                             false,
    258                             al,
    259                             "vs r4 r11 r5 ASR 7",
    260                             "vs_r4_r11_r5_ASR_7"},
    261                            {{le, r7, r14, r12, ASR, 3},
    262                             false,
    263                             al,
    264                             "le r7 r14 r12 ASR 3",
    265                             "le_r7_r14_r12_ASR_3"},
    266                            {{ne, r7, r4, r0, ASR, 17},
    267                             false,
    268                             al,
    269                             "ne r7 r4 r0 ASR 17",
    270                             "ne_r7_r4_r0_ASR_17"},
    271                            {{hi, r5, r11, r3, ASR, 4},
    272                             false,
    273                             al,
    274                             "hi r5 r11 r3 ASR 4",
    275                             "hi_r5_r11_r3_ASR_4"},
    276                            {{cs, r8, r7, r9, LSR, 24},
    277                             false,
    278                             al,
    279                             "cs r8 r7 r9 LSR 24",
    280                             "cs_r8_r7_r9_LSR_24"},
    281                            {{vc, r3, r9, r13, LSR, 7},
    282                             false,
    283                             al,
    284                             "vc r3 r9 r13 LSR 7",
    285                             "vc_r3_r9_r13_LSR_7"},
    286                            {{lt, r6, r14, r3, LSR, 2},
    287                             false,
    288                             al,
    289                             "lt r6 r14 r3 LSR 2",
    290                             "lt_r6_r14_r3_LSR_2"},
    291                            {{lt, r10, r14, r2, LSR, 29},
    292                             false,
    293                             al,
    294                             "lt r10 r14 r2 LSR 29",
    295                             "lt_r10_r14_r2_LSR_29"},
    296                            {{mi, r8, r12, r0, ASR, 30},
    297                             false,
    298                             al,
    299                             "mi r8 r12 r0 ASR 30",
    300                             "mi_r8_r12_r0_ASR_30"},
    301                            {{ls, r9, r0, r5, LSR, 25},
    302                             false,
    303                             al,
    304                             "ls r9 r0 r5 LSR 25",
    305                             "ls_r9_r0_r5_LSR_25"},
    306                            {{ls, r10, r12, r5, ASR, 21},
    307                             false,
    308                             al,
    309                             "ls r10 r12 r5 ASR 21",
    310                             "ls_r10_r12_r5_ASR_21"},
    311                            {{vs, r9, r10, r0, LSR, 8},
    312                             false,
    313                             al,
    314                             "vs r9 r10 r0 LSR 8",
    315                             "vs_r9_r10_r0_LSR_8"},
    316                            {{mi, r13, r9, r9, LSR, 32},
    317                             false,
    318                             al,
    319                             "mi r13 r9 r9 LSR 32",
    320                             "mi_r13_r9_r9_LSR_32"},
    321                            {{mi, r10, r14, r4, ASR, 5},
    322                             false,
    323                             al,
    324                             "mi r10 r14 r4 ASR 5",
    325                             "mi_r10_r14_r4_ASR_5"},
    326                            {{ls, r12, r2, r12, LSR, 7},
    327                             false,
    328                             al,
    329                             "ls r12 r2 r12 LSR 7",
    330                             "ls_r12_r2_r12_LSR_7"},
    331                            {{ne, r5, r5, r11, LSR, 20},
    332                             false,
    333                             al,
    334                             "ne r5 r5 r11 LSR 20",
    335                             "ne_r5_r5_r11_LSR_20"},
    336                            {{vc, r5, r2, r13, ASR, 15},
    337                             false,
    338                             al,
    339                             "vc r5 r2 r13 ASR 15",
    340                             "vc_r5_r2_r13_ASR_15"},
    341                            {{cc, r8, r13, r0, LSR, 2},
    342                             false,
    343                             al,
    344                             "cc r8 r13 r0 LSR 2",
    345                             "cc_r8_r13_r0_LSR_2"},
    346                            {{hi, r5, r5, r12, LSR, 9},
    347                             false,
    348                             al,
    349                             "hi r5 r5 r12 LSR 9",
    350                             "hi_r5_r5_r12_LSR_9"},
    351                            {{cs, r9, r10, r5, ASR, 29},
    352                             false,
    353                             al,
    354                             "cs r9 r10 r5 ASR 29",
    355                             "cs_r9_r10_r5_ASR_29"},
    356                            {{le, r14, r1, r2, ASR, 10},
    357                             false,
    358                             al,
    359                             "le r14 r1 r2 ASR 10",
    360                             "le_r14_r1_r2_ASR_10"},
    361                            {{mi, r1, r11, r5, LSR, 23},
    362                             false,
    363                             al,
    364                             "mi r1 r11 r5 LSR 23",
    365                             "mi_r1_r11_r5_LSR_23"},
    366                            {{vc, r3, r0, r12, LSR, 9},
    367                             false,
    368                             al,
    369                             "vc r3 r0 r12 LSR 9",
    370                             "vc_r3_r0_r12_LSR_9"},
    371                            {{cs, r2, r4, r11, LSR, 14},
    372                             false,
    373                             al,
    374                             "cs r2 r4 r11 LSR 14",
    375                             "cs_r2_r4_r11_LSR_14"},
    376                            {{gt, r8, r13, r2, ASR, 29},
    377                             false,
    378                             al,
    379                             "gt r8 r13 r2 ASR 29",
    380                             "gt_r8_r13_r2_ASR_29"},
    381                            {{vc, r1, r8, r13, ASR, 9},
    382                             false,
    383                             al,
    384                             "vc r1 r8 r13 ASR 9",
    385                             "vc_r1_r8_r13_ASR_9"},
    386                            {{vs, r3, r10, r6, LSR, 29},
    387                             false,
    388                             al,
    389                             "vs r3 r10 r6 LSR 29",
    390                             "vs_r3_r10_r6_LSR_29"},
    391                            {{ge, r1, r3, r6, LSR, 6},
    392                             false,
    393                             al,
    394                             "ge r1 r3 r6 LSR 6",
    395                             "ge_r1_r3_r6_LSR_6"},
    396                            {{cs, r5, r1, r9, ASR, 4},
    397                             false,
    398                             al,
    399                             "cs r5 r1 r9 ASR 4",
    400                             "cs_r5_r1_r9_ASR_4"},
    401                            {{le, r3, r6, r14, ASR, 22},
    402                             false,
    403                             al,
    404                             "le r3 r6 r14 ASR 22",
    405                             "le_r3_r6_r14_ASR_22"},
    406                            {{le, r4, r4, r9, LSR, 15},
    407                             false,
    408                             al,
    409                             "le r4 r4 r9 LSR 15",
    410                             "le_r4_r4_r9_LSR_15"},
    411                            {{le, r13, r3, r1, LSR, 25},
    412                             false,
    413                             al,
    414                             "le r13 r3 r1 LSR 25",
    415                             "le_r13_r3_r1_LSR_25"},
    416                            {{cc, r8, r14, r8, ASR, 5},
    417                             false,
    418                             al,
    419                             "cc r8 r14 r8 ASR 5",
    420                             "cc_r8_r14_r8_ASR_5"},
    421                            {{ge, r6, r12, r0, ASR, 14},
    422                             false,
    423                             al,
    424                             "ge r6 r12 r0 ASR 14",
    425                             "ge_r6_r12_r0_ASR_14"},
    426                            {{gt, r3, r6, r10, LSR, 15},
    427                             false,
    428                             al,
    429                             "gt r3 r6 r10 LSR 15",
    430                             "gt_r3_r6_r10_LSR_15"},
    431                            {{cs, r0, r5, r6, LSR, 29},
    432                             false,
    433                             al,
    434                             "cs r0 r5 r6 LSR 29",
    435                             "cs_r0_r5_r6_LSR_29"},
    436                            {{pl, r6, r4, r3, LSR, 13},
    437                             false,
    438                             al,
    439                             "pl r6 r4 r3 LSR 13",
    440                             "pl_r6_r4_r3_LSR_13"},
    441                            {{pl, r8, r12, r6, LSR, 5},
    442                             false,
    443                             al,
    444                             "pl r8 r12 r6 LSR 5",
    445                             "pl_r8_r12_r6_LSR_5"},
    446                            {{vc, r13, r7, r0, LSR, 18},
    447                             false,
    448                             al,
    449                             "vc r13 r7 r0 LSR 18",
    450                             "vc_r13_r7_r0_LSR_18"},
    451                            {{ne, r0, r12, r8, ASR, 1},
    452                             false,
    453                             al,
    454                             "ne r0 r12 r8 ASR 1",
    455                             "ne_r0_r12_r8_ASR_1"},
    456                            {{ls, r8, r2, r10, ASR, 14},
    457                             false,
    458                             al,
    459                             "ls r8 r2 r10 ASR 14",
    460                             "ls_r8_r2_r10_ASR_14"},
    461                            {{al, r5, r3, r9, ASR, 2},
    462                             false,
    463                             al,
    464                             "al r5 r3 r9 ASR 2",
    465                             "al_r5_r3_r9_ASR_2"},
    466                            {{vc, r1, r14, r13, LSR, 4},
    467                             false,
    468                             al,
    469                             "vc r1 r14 r13 LSR 4",
    470                             "vc_r1_r14_r13_LSR_4"},
    471                            {{vc, r0, r10, r4, LSR, 30},
    472                             false,
    473                             al,
    474                             "vc r0 r10 r4 LSR 30",
    475                             "vc_r0_r10_r4_LSR_30"},
    476                            {{al, r3, r0, r11, ASR, 14},
    477                             false,
    478                             al,
    479                             "al r3 r0 r11 ASR 14",
    480                             "al_r3_r0_r11_ASR_14"},
    481                            {{vs, r3, r11, r10, ASR, 23},
    482                             false,
    483                             al,
    484                             "vs r3 r11 r10 ASR 23",
    485                             "vs_r3_r11_r10_ASR_23"},
    486                            {{ls, r0, r9, r0, ASR, 8},
    487                             false,
    488                             al,
    489                             "ls r0 r9 r0 ASR 8",
    490                             "ls_r0_r9_r0_ASR_8"},
    491                            {{le, r2, r8, r10, LSR, 5},
    492                             false,
    493                             al,
    494                             "le r2 r8 r10 LSR 5",
    495                             "le_r2_r8_r10_LSR_5"},
    496                            {{cs, r0, r5, r0, LSR, 31},
    497                             false,
    498                             al,
    499                             "cs r0 r5 r0 LSR 31",
    500                             "cs_r0_r5_r0_LSR_31"},
    501                            {{cc, r1, r10, r13, LSR, 27},
    502                             false,
    503                             al,
    504                             "cc r1 r10 r13 LSR 27",
    505                             "cc_r1_r10_r13_LSR_27"},
    506                            {{ge, r11, r13, r12, ASR, 17},
    507                             false,
    508                             al,
    509                             "ge r11 r13 r12 ASR 17",
    510                             "ge_r11_r13_r12_ASR_17"},
    511                            {{eq, r2, r9, r4, LSR, 12},
    512                             false,
    513                             al,
    514                             "eq r2 r9 r4 LSR 12",
    515                             "eq_r2_r9_r4_LSR_12"},
    516                            {{ge, r4, r14, r0, ASR, 13},
    517                             false,
    518                             al,
    519                             "ge r4 r14 r0 ASR 13",
    520                             "ge_r4_r14_r0_ASR_13"},
    521                            {{vc, r1, r6, r0, ASR, 16},
    522                             false,
    523                             al,
    524                             "vc r1 r6 r0 ASR 16",
    525                             "vc_r1_r6_r0_ASR_16"},
    526                            {{hi, r7, r9, r12, LSR, 11},
    527                             false,
    528                             al,
    529                             "hi r7 r9 r12 LSR 11",
    530                             "hi_r7_r9_r12_LSR_11"},
    531                            {{eq, r14, r11, r12, LSR, 29},
    532                             false,
    533                             al,
    534                             "eq r14 r11 r12 LSR 29",
    535                             "eq_r14_r11_r12_LSR_29"},
    536                            {{ge, r14, r13, r4, ASR, 23},
    537                             false,
    538                             al,
    539                             "ge r14 r13 r4 ASR 23",
    540                             "ge_r14_r13_r4_ASR_23"},
    541                            {{pl, r8, r0, r14, ASR, 25},
    542                             false,
    543                             al,
    544                             "pl r8 r0 r14 ASR 25",
    545                             "pl_r8_r0_r14_ASR_25"},
    546                            {{ne, r7, r13, r12, LSR, 14},
    547                             false,
    548                             al,
    549                             "ne r7 r13 r12 LSR 14",
    550                             "ne_r7_r13_r12_LSR_14"},
    551                            {{vs, r13, r4, r7, ASR, 10},
    552                             false,
    553                             al,
    554                             "vs r13 r4 r7 ASR 10",
    555                             "vs_r13_r4_r7_ASR_10"},
    556                            {{mi, r3, r14, r9, ASR, 15},
    557                             false,
    558                             al,
    559                             "mi r3 r14 r9 ASR 15",
    560                             "mi_r3_r14_r9_ASR_15"},
    561                            {{cs, r14, r9, r14, ASR, 25},
    562                             false,
    563                             al,
    564                             "cs r14 r9 r14 ASR 25",
    565                             "cs_r14_r9_r14_ASR_25"},
    566                            {{cc, r11, r7, r4, LSR, 4},
    567                             false,
    568                             al,
    569                             "cc r11 r7 r4 LSR 4",
    570                             "cc_r11_r7_r4_LSR_4"},
    571                            {{cc, r11, r7, r2, ASR, 1},
    572                             false,
    573                             al,
    574                             "cc r11 r7 r2 ASR 1",
    575                             "cc_r11_r7_r2_ASR_1"},
    576                            {{al, r0, r5, r5, LSR, 11},
    577                             false,
    578                             al,
    579                             "al r0 r5 r5 LSR 11",
    580                             "al_r0_r5_r5_LSR_11"},
    581                            {{eq, r3, r5, r13, LSR, 3},
    582                             false,
    583                             al,
    584                             "eq r3 r5 r13 LSR 3",
    585                             "eq_r3_r5_r13_LSR_3"},
    586                            {{ge, r11, r1, r1, ASR, 24},
    587                             false,
    588                             al,
    589                             "ge r11 r1 r1 ASR 24",
    590                             "ge_r11_r1_r1_ASR_24"},
    591                            {{lt, r13, r12, r12, LSR, 9},
    592                             false,
    593                             al,
    594                             "lt r13 r12 r12 LSR 9",
    595                             "lt_r13_r12_r12_LSR_9"},
    596                            {{cs, r13, r1, r14, LSR, 26},
    597                             false,
    598                             al,
    599                             "cs r13 r1 r14 LSR 26",
    600                             "cs_r13_r1_r14_LSR_26"},
    601                            {{ge, r10, r4, r4, LSR, 31},
    602                             false,
    603                             al,
    604                             "ge r10 r4 r4 LSR 31",
    605                             "ge_r10_r4_r4_LSR_31"},
    606                            {{pl, r7, r7, r5, ASR, 5},
    607                             false,
    608                             al,
    609                             "pl r7 r7 r5 ASR 5",
    610                             "pl_r7_r7_r5_ASR_5"},
    611                            {{eq, r2, r13, r10, ASR, 26},
    612                             false,
    613                             al,
    614                             "eq r2 r13 r10 ASR 26",
    615                             "eq_r2_r13_r10_ASR_26"},
    616                            {{ne, r5, r8, r13, LSR, 23},
    617                             false,
    618                             al,
    619                             "ne r5 r8 r13 LSR 23",
    620                             "ne_r5_r8_r13_LSR_23"},
    621                            {{al, r0, r5, r12, LSR, 1},
    622                             false,
    623                             al,
    624                             "al r0 r5 r12 LSR 1",
    625                             "al_r0_r5_r12_LSR_1"},
    626                            {{al, r10, r11, r4, ASR, 23},
    627                             false,
    628                             al,
    629                             "al r10 r11 r4 ASR 23",
    630                             "al_r10_r11_r4_ASR_23"},
    631                            {{al, r0, r11, r10, LSR, 1},
    632                             false,
    633                             al,
    634                             "al r0 r11 r10 LSR 1",
    635                             "al_r0_r11_r10_LSR_1"},
    636                            {{eq, r9, r9, r2, LSR, 18},
    637                             false,
    638                             al,
    639                             "eq r9 r9 r2 LSR 18",
    640                             "eq_r9_r9_r2_LSR_18"},
    641                            {{mi, r2, r9, r8, ASR, 25},
    642                             false,
    643                             al,
    644                             "mi r2 r9 r8 ASR 25",
    645                             "mi_r2_r9_r8_ASR_25"},
    646                            {{vc, r6, r7, r1, LSR, 3},
    647                             false,
    648                             al,
    649                             "vc r6 r7 r1 LSR 3",
    650                             "vc_r6_r7_r1_LSR_3"},
    651                            {{pl, r6, r10, r0, ASR, 29},
    652                             false,
    653                             al,
    654                             "pl r6 r10 r0 ASR 29",
    655                             "pl_r6_r10_r0_ASR_29"},
    656                            {{gt, r9, r5, r5, ASR, 10},
    657                             false,
    658                             al,
    659                             "gt r9 r5 r5 ASR 10",
    660                             "gt_r9_r5_r5_ASR_10"},
    661                            {{mi, r1, r0, r3, LSR, 28},
    662                             false,
    663                             al,
    664                             "mi r1 r0 r3 LSR 28",
    665                             "mi_r1_r0_r3_LSR_28"},
    666                            {{ne, r10, r11, r9, LSR, 8},
    667                             false,
    668                             al,
    669                             "ne r10 r11 r9 LSR 8",
    670                             "ne_r10_r11_r9_LSR_8"},
    671                            {{ls, r1, r9, r3, ASR, 29},
    672                             false,
    673                             al,
    674                             "ls r1 r9 r3 ASR 29",
    675                             "ls_r1_r9_r3_ASR_29"},
    676                            {{eq, r13, r10, r13, LSR, 9},
    677                             false,
    678                             al,
    679                             "eq r13 r10 r13 LSR 9",
    680                             "eq_r13_r10_r13_LSR_9"},
    681                            {{mi, r13, r0, r3, ASR, 20},
    682                             false,
    683                             al,
    684                             "mi r13 r0 r3 ASR 20",
    685                             "mi_r13_r0_r3_ASR_20"},
    686                            {{eq, r14, r13, r12, ASR, 18},
    687                             false,
    688                             al,
    689                             "eq r14 r13 r12 ASR 18",
    690                             "eq_r14_r13_r12_ASR_18"},
    691                            {{mi, r10, r7, r6, ASR, 2},
    692                             false,
    693                             al,
    694                             "mi r10 r7 r6 ASR 2",
    695                             "mi_r10_r7_r6_ASR_2"},
    696                            {{hi, r0, r1, r2, LSR, 32},
    697                             false,
    698                             al,
    699                             "hi r0 r1 r2 LSR 32",
    700                             "hi_r0_r1_r2_LSR_32"},
    701                            {{pl, r10, r2, r8, LSR, 14},
    702                             false,
    703                             al,
    704                             "pl r10 r2 r8 LSR 14",
    705                             "pl_r10_r2_r8_LSR_14"},
    706                            {{le, r12, r6, r2, ASR, 8},
    707                             false,
    708                             al,
    709                             "le r12 r6 r2 ASR 8",
    710                             "le_r12_r6_r2_ASR_8"},
    711                            {{gt, r4, r0, r4, ASR, 12},
    712                             false,
    713                             al,
    714                             "gt r4 r0 r4 ASR 12",
    715                             "gt_r4_r0_r4_ASR_12"},
    716                            {{eq, r9, r0, r10, LSR, 15},
    717                             false,
    718                             al,
    719                             "eq r9 r0 r10 LSR 15",
    720                             "eq_r9_r0_r10_LSR_15"},
    721                            {{ge, r7, r1, r8, ASR, 8},
    722                             false,
    723                             al,
    724                             "ge r7 r1 r8 ASR 8",
    725                             "ge_r7_r1_r8_ASR_8"},
    726                            {{al, r1, r1, r12, ASR, 7},
    727                             false,
    728                             al,
    729                             "al r1 r1 r12 ASR 7",
    730                             "al_r1_r1_r12_ASR_7"},
    731                            {{lt, r13, r1, r2, LSR, 11},
    732                             false,
    733                             al,
    734                             "lt r13 r1 r2 LSR 11",
    735                             "lt_r13_r1_r2_LSR_11"},
    736                            {{cc, r2, r5, r3, ASR, 3},
    737                             false,
    738                             al,
    739                             "cc r2 r5 r3 ASR 3",
    740                             "cc_r2_r5_r3_ASR_3"},
    741                            {{ne, r8, r2, r9, LSR, 14},
    742                             false,
    743                             al,
    744                             "ne r8 r2 r9 LSR 14",
    745                             "ne_r8_r2_r9_LSR_14"},
    746                            {{eq, r11, r8, r1, LSR, 3},
    747                             false,
    748                             al,
    749                             "eq r11 r8 r1 LSR 3",
    750                             "eq_r11_r8_r1_LSR_3"},
    751                            {{al, r3, r14, r11, LSR, 14},
    752                             false,
    753                             al,
    754                             "al r3 r14 r11 LSR 14",
    755                             "al_r3_r14_r11_LSR_14"},
    756                            {{pl, r1, r2, r7, LSR, 31},
    757                             false,
    758                             al,
    759                             "pl r1 r2 r7 LSR 31",
    760                             "pl_r1_r2_r7_LSR_31"},
    761                            {{eq, r14, r2, r5, LSR, 20},
    762                             false,
    763                             al,
    764                             "eq r14 r2 r5 LSR 20",
    765                             "eq_r14_r2_r5_LSR_20"},
    766                            {{hi, r7, r13, r3, LSR, 21},
    767                             false,
    768                             al,
    769                             "hi r7 r13 r3 LSR 21",
    770                             "hi_r7_r13_r3_LSR_21"},
    771                            {{gt, r14, r7, r11, LSR, 16},
    772                             false,
    773                             al,
    774                             "gt r14 r7 r11 LSR 16",
    775                             "gt_r14_r7_r11_LSR_16"},
    776                            {{ls, r0, r5, r14, ASR, 25},
    777                             false,
    778                             al,
    779                             "ls r0 r5 r14 ASR 25",
    780                             "ls_r0_r5_r14_ASR_25"},
    781                            {{cc, r0, r7, r8, LSR, 4},
    782                             false,
    783                             al,
    784                             "cc r0 r7 r8 LSR 4",
    785                             "cc_r0_r7_r8_LSR_4"},
    786                            {{hi, r3, r5, r9, ASR, 9},
    787                             false,
    788                             al,
    789                             "hi r3 r5 r9 ASR 9",
    790                             "hi_r3_r5_r9_ASR_9"},
    791                            {{hi, r10, r5, r5, ASR, 15},
    792                             false,
    793                             al,
    794                             "hi r10 r5 r5 ASR 15",
    795                             "hi_r10_r5_r5_ASR_15"},
    796                            {{le, r7, r14, r0, LSR, 19},
    797                             false,
    798                             al,
    799                             "le r7 r14 r0 LSR 19",
    800                             "le_r7_r14_r0_LSR_19"},
    801                            {{gt, r10, r1, r2, LSR, 16},
    802                             false,
    803                             al,
    804                             "gt r10 r1 r2 LSR 16",
    805                             "gt_r10_r1_r2_LSR_16"},
    806                            {{ls, r4, r14, r10, LSR, 21},
    807                             false,
    808                             al,
    809                             "ls r4 r14 r10 LSR 21",
    810                             "ls_r4_r14_r10_LSR_21"},
    811                            {{mi, r12, r14, r3, LSR, 11},
    812                             false,
    813                             al,
    814                             "mi r12 r14 r3 LSR 11",
    815                             "mi_r12_r14_r3_LSR_11"},
    816                            {{al, r7, r9, r4, LSR, 12},
    817                             false,
    818                             al,
    819                             "al r7 r9 r4 LSR 12",
    820                             "al_r7_r9_r4_LSR_12"},
    821                            {{cc, r0, r10, r1, ASR, 20},
    822                             false,
    823                             al,
    824                             "cc r0 r10 r1 ASR 20",
    825                             "cc_r0_r10_r1_ASR_20"},
    826                            {{mi, r0, r2, r11, LSR, 31},
    827                             false,
    828                             al,
    829                             "mi r0 r2 r11 LSR 31",
    830                             "mi_r0_r2_r11_LSR_31"},
    831                            {{cs, r7, r9, r6, ASR, 22},
    832                             false,
    833                             al,
    834                             "cs r7 r9 r6 ASR 22",
    835                             "cs_r7_r9_r6_ASR_22"},
    836                            {{gt, r9, r6, r13, LSR, 25},
    837                             false,
    838                             al,
    839                             "gt r9 r6 r13 LSR 25",
    840                             "gt_r9_r6_r13_LSR_25"},
    841                            {{cc, r1, r2, r8, ASR, 16},
    842                             false,
    843                             al,
    844                             "cc r1 r2 r8 ASR 16",
    845                             "cc_r1_r2_r8_ASR_16"},
    846                            {{ne, r6, r4, r14, ASR, 12},
    847                             false,
    848                             al,
    849                             "ne r6 r4 r14 ASR 12",
    850                             "ne_r6_r4_r14_ASR_12"},
    851                            {{al, r7, r2, r14, ASR, 11},
    852                             false,
    853                             al,
    854                             "al r7 r2 r14 ASR 11",
    855                             "al_r7_r2_r14_ASR_11"},
    856                            {{gt, r10, r14, r13, LSR, 22},
    857                             false,
    858                             al,
    859                             "gt r10 r14 r13 LSR 22",
    860                             "gt_r10_r14_r13_LSR_22"},
    861                            {{lt, r0, r8, r6, LSR, 25},
    862                             false,
    863                             al,
    864                             "lt r0 r8 r6 LSR 25",
    865                             "lt_r0_r8_r6_LSR_25"},
    866                            {{ne, r12, r5, r6, ASR, 20},
    867                             false,
    868                             al,
    869                             "ne r12 r5 r6 ASR 20",
    870                             "ne_r12_r5_r6_ASR_20"},
    871                            {{pl, r12, r6, r7, ASR, 27},
    872                             false,
    873                             al,
    874                             "pl r12 r6 r7 ASR 27",
    875                             "pl_r12_r6_r7_ASR_27"},
    876                            {{gt, r5, r8, r7, ASR, 19},
    877                             false,
    878                             al,
    879                             "gt r5 r8 r7 ASR 19",
    880                             "gt_r5_r8_r7_ASR_19"},
    881                            {{le, r12, r1, r4, LSR, 22},
    882                             false,
    883                             al,
    884                             "le r12 r1 r4 LSR 22",
    885                             "le_r12_r1_r4_LSR_22"},
    886                            {{le, r9, r8, r11, LSR, 17},
    887                             false,
    888                             al,
    889                             "le r9 r8 r11 LSR 17",
    890                             "le_r9_r8_r11_LSR_17"},
    891                            {{gt, r5, r2, r3, ASR, 30},
    892                             false,
    893                             al,
    894                             "gt r5 r2 r3 ASR 30",
    895                             "gt_r5_r2_r3_ASR_30"},
    896                            {{ge, r8, r7, r7, ASR, 31},
    897                             false,
    898                             al,
    899                             "ge r8 r7 r7 ASR 31",
    900                             "ge_r8_r7_r7_ASR_31"},
    901                            {{lt, r14, r8, r11, ASR, 23},
    902                             false,
    903                             al,
    904                             "lt r14 r8 r11 ASR 23",
    905                             "lt_r14_r8_r11_ASR_23"},
    906                            {{cc, r0, r11, r6, LSR, 1},
    907                             false,
    908                             al,
    909                             "cc r0 r11 r6 LSR 1",
    910                             "cc_r0_r11_r6_LSR_1"},
    911                            {{pl, r0, r6, r14, LSR, 2},
    912                             false,
    913                             al,
    914                             "pl r0 r6 r14 LSR 2",
    915                             "pl_r0_r6_r14_LSR_2"},
    916                            {{lt, r4, r2, r1, ASR, 16},
    917                             false,
    918                             al,
    919                             "lt r4 r2 r1 ASR 16",
    920                             "lt_r4_r2_r1_ASR_16"},
    921                            {{pl, r14, r2, r14, ASR, 19},
    922                             false,
    923                             al,
    924                             "pl r14 r2 r14 ASR 19",
    925                             "pl_r14_r2_r14_ASR_19"},
    926                            {{cs, r13, r5, r9, LSR, 32},
    927                             false,
    928                             al,
    929                             "cs r13 r5 r9 LSR 32",
    930                             "cs_r13_r5_r9_LSR_32"},
    931                            {{cc, r13, r8, r1, LSR, 1},
    932                             false,
    933                             al,
    934                             "cc r13 r8 r1 LSR 1",
    935                             "cc_r13_r8_r1_LSR_1"},
    936                            {{cs, r7, r9, r10, LSR, 17},
    937                             false,
    938                             al,
    939                             "cs r7 r9 r10 LSR 17",
    940                             "cs_r7_r9_r10_LSR_17"},
    941                            {{vc, r2, r1, r7, LSR, 29},
    942                             false,
    943                             al,
    944                             "vc r2 r1 r7 LSR 29",
    945                             "vc_r2_r1_r7_LSR_29"},
    946                            {{hi, r9, r2, r1, ASR, 17},
    947                             false,
    948                             al,
    949                             "hi r9 r2 r1 ASR 17",
    950                             "hi_r9_r2_r1_ASR_17"},
    951                            {{cc, r14, r14, r7, ASR, 17},
    952                             false,
    953                             al,
    954                             "cc r14 r14 r7 ASR 17",
    955                             "cc_r14_r14_r7_ASR_17"},
    956                            {{vs, r4, r8, r1, LSR, 17},
    957                             false,
    958                             al,
    959                             "vs r4 r8 r1 LSR 17",
    960                             "vs_r4_r8_r1_LSR_17"},
    961                            {{vs, r8, r0, r6, LSR, 8},
    962                             false,
    963                             al,
    964                             "vs r8 r0 r6 LSR 8",
    965                             "vs_r8_r0_r6_LSR_8"},
    966                            {{vs, r8, r0, r14, LSR, 12},
    967                             false,
    968                             al,
    969                             "vs r8 r0 r14 LSR 12",
    970                             "vs_r8_r0_r14_LSR_12"},
    971                            {{vc, r5, r8, r1, ASR, 10},
    972                             false,
    973                             al,
    974                             "vc r5 r8 r1 ASR 10",
    975                             "vc_r5_r8_r1_ASR_10"},
    976                            {{eq, r2, r0, r5, ASR, 12},
    977                             false,
    978                             al,
    979                             "eq r2 r0 r5 ASR 12",
    980                             "eq_r2_r0_r5_ASR_12"},
    981                            {{vc, r13, r2, r11, LSR, 27},
    982                             false,
    983                             al,
    984                             "vc r13 r2 r11 LSR 27",
    985                             "vc_r13_r2_r11_LSR_27"},
    986                            {{vc, r9, r3, r1, LSR, 15},
    987                             false,
    988                             al,
    989                             "vc r9 r3 r1 LSR 15",
    990                             "vc_r9_r3_r1_LSR_15"},
    991                            {{gt, r3, r11, r10, ASR, 19},
    992                             false,
    993                             al,
    994                             "gt r3 r11 r10 ASR 19",
    995                             "gt_r3_r11_r10_ASR_19"},
    996                            {{pl, r1, r0, r6, ASR, 23},
    997                             false,
    998                             al,
    999                             "pl r1 r0 r6 ASR 23",
   1000                             "pl_r1_r0_r6_ASR_23"},
   1001                            {{ls, r3, r7, r8, LSR, 8},
   1002                             false,
   1003                             al,
   1004                             "ls r3 r7 r8 LSR 8",
   1005                             "ls_r3_r7_r8_LSR_8"},
   1006                            {{ls, r12, r14, r11, LSR, 22},
   1007                             false,
   1008                             al,
   1009                             "ls r12 r14 r11 LSR 22",
   1010                             "ls_r12_r14_r11_LSR_22"},
   1011                            {{vc, r5, r3, r8, ASR, 6},
   1012                             false,
   1013                             al,
   1014                             "vc r5 r3 r8 ASR 6",
   1015                             "vc_r5_r3_r8_ASR_6"},
   1016                            {{le, r4, r13, r14, LSR, 10},
   1017                             false,
   1018                             al,
   1019                             "le r4 r13 r14 LSR 10",
   1020                             "le_r4_r13_r14_LSR_10"},
   1021                            {{vc, r7, r4, r14, ASR, 8},
   1022                             false,
   1023                             al,
   1024                             "vc r7 r4 r14 ASR 8",
   1025                             "vc_r7_r4_r14_ASR_8"},
   1026                            {{ge, r3, r7, r8, LSR, 3},
   1027                             false,
   1028                             al,
   1029                             "ge r3 r7 r8 LSR 3",
   1030                             "ge_r3_r7_r8_LSR_3"},
   1031                            {{al, r13, r8, r4, LSR, 18},
   1032                             false,
   1033                             al,
   1034                             "al r13 r8 r4 LSR 18",
   1035                             "al_r13_r8_r4_LSR_18"},
   1036                            {{gt, r7, r0, r6, ASR, 21},
   1037                             false,
   1038                             al,
   1039                             "gt r7 r0 r6 ASR 21",
   1040                             "gt_r7_r0_r6_ASR_21"},
   1041                            {{al, r3, r11, r13, LSR, 31},
   1042                             false,
   1043                             al,
   1044                             "al r3 r11 r13 LSR 31",
   1045                             "al_r3_r11_r13_LSR_31"},
   1046                            {{le, r5, r0, r11, ASR, 6},
   1047                             false,
   1048                             al,
   1049                             "le r5 r0 r11 ASR 6",
   1050                             "le_r5_r0_r11_ASR_6"},
   1051                            {{cc, r11, r2, r5, LSR, 26},
   1052                             false,
   1053                             al,
   1054                             "cc r11 r2 r5 LSR 26",
   1055                             "cc_r11_r2_r5_LSR_26"},
   1056                            {{eq, r10, r14, r7, ASR, 8},
   1057                             false,
   1058                             al,
   1059                             "eq r10 r14 r7 ASR 8",
   1060                             "eq_r10_r14_r7_ASR_8"},
   1061                            {{ne, r0, r0, r5, LSR, 3},
   1062                             false,
   1063                             al,
   1064                             "ne r0 r0 r5 LSR 3",
   1065                             "ne_r0_r0_r5_LSR_3"},
   1066                            {{mi, r9, r1, r2, ASR, 6},
   1067                             false,
   1068                             al,
   1069                             "mi r9 r1 r2 ASR 6",
   1070                             "mi_r9_r1_r2_ASR_6"},
   1071                            {{eq, r6, r10, r13, ASR, 17},
   1072                             false,
   1073                             al,
   1074                             "eq r6 r10 r13 ASR 17",
   1075                             "eq_r6_r10_r13_ASR_17"},
   1076                            {{hi, r2, r7, r0, ASR, 32},
   1077                             false,
   1078                             al,
   1079                             "hi r2 r7 r0 ASR 32",
   1080                             "hi_r2_r7_r0_ASR_32"},
   1081                            {{ge, r14, r3, r11, LSR, 17},
   1082                             false,
   1083                             al,
   1084                             "ge r14 r3 r11 LSR 17",
   1085                             "ge_r14_r3_r11_LSR_17"},
   1086                            {{cc, r6, r4, r5, LSR, 4},
   1087                             false,
   1088                             al,
   1089                             "cc r6 r4 r5 LSR 4",
   1090                             "cc_r6_r4_r5_LSR_4"},
   1091                            {{al, r9, r14, r3, LSR, 32},
   1092                             false,
   1093                             al,
   1094                             "al r9 r14 r3 LSR 32",
   1095                             "al_r9_r14_r3_LSR_32"},
   1096                            {{vc, r14, r14, r6, LSR, 23},
   1097                             false,
   1098                             al,
   1099                             "vc r14 r14 r6 LSR 23",
   1100                             "vc_r14_r14_r6_LSR_23"},
   1101                            {{le, r1, r9, r7, ASR, 6},
   1102                             false,
   1103                             al,
   1104                             "le r1 r9 r7 ASR 6",
   1105                             "le_r1_r9_r7_ASR_6"},
   1106                            {{mi, r2, r11, r7, ASR, 5},
   1107                             false,
   1108                             al,
   1109                             "mi r2 r11 r7 ASR 5",
   1110                             "mi_r2_r11_r7_ASR_5"},
   1111                            {{le, r3, r14, r9, LSR, 25},
   1112                             false,
   1113                             al,
   1114                             "le r3 r14 r9 LSR 25",
   1115                             "le_r3_r14_r9_LSR_25"},
   1116                            {{mi, r10, r8, r10, ASR, 25},
   1117                             false,
   1118                             al,
   1119                             "mi r10 r8 r10 ASR 25",
   1120                             "mi_r10_r8_r10_ASR_25"},
   1121                            {{eq, r5, r9, r5, LSR, 24},
   1122                             false,
   1123                             al,
   1124                             "eq r5 r9 r5 LSR 24",
   1125                             "eq_r5_r9_r5_LSR_24"},
   1126                            {{al, r2, r3, r13, ASR, 24},
   1127                             false,
   1128                             al,
   1129                             "al r2 r3 r13 ASR 24",
   1130                             "al_r2_r3_r13_ASR_24"},
   1131                            {{cc, r6, r3, r7, ASR, 23},
   1132                             false,
   1133                             al,
   1134                             "cc r6 r3 r7 ASR 23",
   1135                             "cc_r6_r3_r7_ASR_23"},
   1136                            {{ge, r11, r11, r13, LSR, 7},
   1137                             false,
   1138                             al,
   1139                             "ge r11 r11 r13 LSR 7",
   1140                             "ge_r11_r11_r13_LSR_7"},
   1141                            {{vc, r14, r1, r3, ASR, 17},
   1142                             false,
   1143                             al,
   1144                             "vc r14 r1 r3 ASR 17",
   1145                             "vc_r14_r1_r3_ASR_17"},
   1146                            {{ls, r5, r1, r14, ASR, 3},
   1147                             false,
   1148                             al,
   1149                             "ls r5 r1 r14 ASR 3",
   1150                             "ls_r5_r1_r14_ASR_3"},
   1151                            {{ge, r13, r5, r4, LSR, 18},
   1152                             false,
   1153                             al,
   1154                             "ge r13 r5 r4 LSR 18",
   1155                             "ge_r13_r5_r4_LSR_18"},
   1156                            {{gt, r6, r5, r14, LSR, 6},
   1157                             false,
   1158                             al,
   1159                             "gt r6 r5 r14 LSR 6",
   1160                             "gt_r6_r5_r14_LSR_6"},
   1161                            {{eq, r9, r6, r7, LSR, 11},
   1162                             false,
   1163                             al,
   1164                             "eq r9 r6 r7 LSR 11",
   1165                             "eq_r9_r6_r7_LSR_11"},
   1166                            {{eq, r14, r6, r12, ASR, 27},
   1167                             false,
   1168                             al,
   1169                             "eq r14 r6 r12 ASR 27",
   1170                             "eq_r14_r6_r12_ASR_27"},
   1171                            {{pl, r14, r14, r9, ASR, 19},
   1172                             false,
   1173                             al,
   1174                             "pl r14 r14 r9 ASR 19",
   1175                             "pl_r14_r14_r9_ASR_19"},
   1176                            {{le, r14, r12, r8, LSR, 13},
   1177                             false,
   1178                             al,
   1179                             "le r14 r12 r8 LSR 13",
   1180                             "le_r14_r12_r8_LSR_13"},
   1181                            {{cc, r7, r5, r5, LSR, 13},
   1182                             false,
   1183                             al,
   1184                             "cc r7 r5 r5 LSR 13",
   1185                             "cc_r7_r5_r5_LSR_13"},
   1186                            {{eq, r2, r13, r4, ASR, 19},
   1187                             false,
   1188                             al,
   1189                             "eq r2 r13 r4 ASR 19",
   1190                             "eq_r2_r13_r4_ASR_19"},
   1191                            {{vs, r11, r11, r10, ASR, 2},
   1192                             false,
   1193                             al,
   1194                             "vs r11 r11 r10 ASR 2",
   1195                             "vs_r11_r11_r10_ASR_2"},
   1196                            {{cc, r10, r8, r8, LSR, 23},
   1197                             false,
   1198                             al,
   1199                             "cc r10 r8 r8 LSR 23",
   1200                             "cc_r10_r8_r8_LSR_23"},
   1201                            {{ls, r14, r12, r6, ASR, 30},
   1202                             false,
   1203                             al,
   1204                             "ls r14 r12 r6 ASR 30",
   1205                             "ls_r14_r12_r6_ASR_30"},
   1206                            {{hi, r8, r8, r6, ASR, 19},
   1207                             false,
   1208                             al,
   1209                             "hi r8 r8 r6 ASR 19",
   1210                             "hi_r8_r8_r6_ASR_19"},
   1211                            {{cs, r5, r12, r3, ASR, 6},
   1212                             false,
   1213                             al,
   1214                             "cs r5 r12 r3 ASR 6",
   1215                             "cs_r5_r12_r3_ASR_6"},
   1216                            {{vs, r0, r9, r14, ASR, 5},
   1217                             false,
   1218                             al,
   1219                             "vs r0 r9 r14 ASR 5",
   1220                             "vs_r0_r9_r14_ASR_5"},
   1221                            {{lt, r9, r6, r14, ASR, 7},
   1222                             false,
   1223                             al,
   1224                             "lt r9 r6 r14 ASR 7",
   1225                             "lt_r9_r6_r14_ASR_7"},
   1226                            {{lt, r5, r1, r11, ASR, 3},
   1227                             false,
   1228                             al,
   1229                             "lt r5 r1 r11 ASR 3",
   1230                             "lt_r5_r1_r11_ASR_3"},
   1231                            {{al, r4, r11, r3, LSR, 14},
   1232                             false,
   1233                             al,
   1234                             "al r4 r11 r3 LSR 14",
   1235                             "al_r4_r11_r3_LSR_14"},
   1236                            {{cs, r7, r1, r3, LSR, 10},
   1237                             false,
   1238                             al,
   1239                             "cs r7 r1 r3 LSR 10",
   1240                             "cs_r7_r1_r3_LSR_10"},
   1241                            {{cc, r2, r11, r4, ASR, 29},
   1242                             false,
   1243                             al,
   1244                             "cc r2 r11 r4 ASR 29",
   1245                             "cc_r2_r11_r4_ASR_29"},
   1246                            {{eq, r7, r1, r4, LSR, 31},
   1247                             false,
   1248                             al,
   1249                             "eq r7 r1 r4 LSR 31",
   1250                             "eq_r7_r1_r4_LSR_31"},
   1251                            {{hi, r2, r13, r7, ASR, 17},
   1252                             false,
   1253                             al,
   1254                             "hi r2 r13 r7 ASR 17",
   1255                             "hi_r2_r13_r7_ASR_17"},
   1256                            {{cs, r12, r10, r9, ASR, 4},
   1257                             false,
   1258                             al,
   1259                             "cs r12 r10 r9 ASR 4",
   1260                             "cs_r12_r10_r9_ASR_4"},
   1261                            {{gt, r10, r2, r2, LSR, 28},
   1262                             false,
   1263                             al,
   1264                             "gt r10 r2 r2 LSR 28",
   1265                             "gt_r10_r2_r2_LSR_28"},
   1266                            {{gt, r13, r12, r0, ASR, 2},
   1267                             false,
   1268                             al,
   1269                             "gt r13 r12 r0 ASR 2",
   1270                             "gt_r13_r12_r0_ASR_2"},
   1271                            {{pl, r14, r8, r7, LSR, 1},
   1272                             false,
   1273                             al,
   1274                             "pl r14 r8 r7 LSR 1",
   1275                             "pl_r14_r8_r7_LSR_1"},
   1276                            {{hi, r2, r13, r3, ASR, 20},
   1277                             false,
   1278                             al,
   1279                             "hi r2 r13 r3 ASR 20",
   1280                             "hi_r2_r13_r3_ASR_20"},
   1281                            {{lt, r2, r3, r3, LSR, 13},
   1282                             false,
   1283                             al,
   1284                             "lt r2 r3 r3 LSR 13",
   1285                             "lt_r2_r3_r3_LSR_13"},
   1286                            {{mi, r11, r1, r12, ASR, 24},
   1287                             false,
   1288                             al,
   1289                             "mi r11 r1 r12 ASR 24",
   1290                             "mi_r11_r1_r12_ASR_24"},
   1291                            {{vs, r8, r8, r8, LSR, 1},
   1292                             false,
   1293                             al,
   1294                             "vs r8 r8 r8 LSR 1",
   1295                             "vs_r8_r8_r8_LSR_1"},
   1296                            {{ne, r2, r14, r3, ASR, 31},
   1297                             false,
   1298                             al,
   1299                             "ne r2 r14 r3 ASR 31",
   1300                             "ne_r2_r14_r3_ASR_31"},
   1301                            {{lt, r8, r5, r1, LSR, 11},
   1302                             false,
   1303                             al,
   1304                             "lt r8 r5 r1 LSR 11",
   1305                             "lt_r8_r5_r1_LSR_11"},
   1306                            {{pl, r4, r9, r8, ASR, 31},
   1307                             false,
   1308                             al,
   1309                             "pl r4 r9 r8 ASR 31",
   1310                             "pl_r4_r9_r8_ASR_31"},
   1311                            {{ls, r8, r1, r13, ASR, 4},
   1312                             false,
   1313                             al,
   1314                             "ls r8 r1 r13 ASR 4",
   1315                             "ls_r8_r1_r13_ASR_4"},
   1316                            {{al, r2, r9, r14, LSR, 16},
   1317                             false,
   1318                             al,
   1319                             "al r2 r9 r14 LSR 16",
   1320                             "al_r2_r9_r14_LSR_16"},
   1321                            {{cs, r3, r6, r10, ASR, 5},
   1322                             false,
   1323                             al,
   1324                             "cs r3 r6 r10 ASR 5",
   1325                             "cs_r3_r6_r10_ASR_5"},
   1326                            {{eq, r4, r12, r6, ASR, 9},
   1327                             false,
   1328                             al,
   1329                             "eq r4 r12 r6 ASR 9",
   1330                             "eq_r4_r12_r6_ASR_9"},
   1331                            {{al, r12, r12, r4, ASR, 32},
   1332                             false,
   1333                             al,
   1334                             "al r12 r12 r4 ASR 32",
   1335                             "al_r12_r12_r4_ASR_32"},
   1336                            {{pl, r1, r6, r11, LSR, 19},
   1337                             false,
   1338                             al,
   1339                             "pl r1 r6 r11 LSR 19",
   1340                             "pl_r1_r6_r11_LSR_19"},
   1341                            {{pl, r8, r2, r1, LSR, 13},
   1342                             false,
   1343                             al,
   1344                             "pl r8 r2 r1 LSR 13",
   1345                             "pl_r8_r2_r1_LSR_13"},
   1346                            {{gt, r2, r11, r2, LSR, 23},
   1347                             false,
   1348                             al,
   1349                             "gt r2 r11 r2 LSR 23",
   1350                             "gt_r2_r11_r2_LSR_23"},
   1351                            {{eq, r14, r8, r6, ASR, 31},
   1352                             false,
   1353                             al,
   1354                             "eq r14 r8 r6 ASR 31",
   1355                             "eq_r14_r8_r6_ASR_31"},
   1356                            {{cc, r6, r5, r7, ASR, 31},
   1357                             false,
   1358                             al,
   1359                             "cc r6 r5 r7 ASR 31",
   1360                             "cc_r6_r5_r7_ASR_31"},
   1361                            {{cs, r14, r10, r11, ASR, 28},
   1362                             false,
   1363                             al,
   1364                             "cs r14 r10 r11 ASR 28",
   1365                             "cs_r14_r10_r11_ASR_28"},
   1366                            {{le, r9, r9, r4, LSR, 22},
   1367                             false,
   1368                             al,
   1369                             "le r9 r9 r4 LSR 22",
   1370                             "le_r9_r9_r4_LSR_22"},
   1371                            {{cs, r4, r1, r14, ASR, 11},
   1372                             false,
   1373                             al,
   1374                             "cs r4 r1 r14 ASR 11",
   1375                             "cs_r4_r1_r14_ASR_11"},
   1376                            {{ne, r6, r0, r9, LSR, 30},
   1377                             false,
   1378                             al,
   1379                             "ne r6 r0 r9 LSR 30",
   1380                             "ne_r6_r0_r9_LSR_30"},
   1381                            {{gt, r8, r6, r6, ASR, 16},
   1382                             false,
   1383                             al,
   1384                             "gt r8 r6 r6 ASR 16",
   1385                             "gt_r8_r6_r6_ASR_16"},
   1386                            {{pl, r11, r3, r5, ASR, 4},
   1387                             false,
   1388                             al,
   1389                             "pl r11 r3 r5 ASR 4",
   1390                             "pl_r11_r3_r5_ASR_4"},
   1391                            {{cs, r6, r3, r5, LSR, 20},
   1392                             false,
   1393                             al,
   1394                             "cs r6 r3 r5 LSR 20",
   1395                             "cs_r6_r3_r5_LSR_20"},
   1396                            {{cc, r1, r9, r13, LSR, 26},
   1397                             false,
   1398                             al,
   1399                             "cc r1 r9 r13 LSR 26",
   1400                             "cc_r1_r9_r13_LSR_26"},
   1401                            {{vc, r5, r11, r2, ASR, 14},
   1402                             false,
   1403                             al,
   1404                             "vc r5 r11 r2 ASR 14",
   1405                             "vc_r5_r11_r2_ASR_14"},
   1406                            {{vc, r11, r0, r0, ASR, 12},
   1407                             false,
   1408                             al,
   1409                             "vc r11 r0 r0 ASR 12",
   1410                             "vc_r11_r0_r0_ASR_12"},
   1411                            {{mi, r3, r8, r2, LSR, 7},
   1412                             false,
   1413                             al,
   1414                             "mi r3 r8 r2 LSR 7",
   1415                             "mi_r3_r8_r2_LSR_7"},
   1416                            {{eq, r11, r2, r11, ASR, 32},
   1417                             false,
   1418                             al,
   1419                             "eq r11 r2 r11 ASR 32",
   1420                             "eq_r11_r2_r11_ASR_32"},
   1421                            {{vc, r6, r0, r9, LSR, 5},
   1422                             false,
   1423                             al,
   1424                             "vc r6 r0 r9 LSR 5",
   1425                             "vc_r6_r0_r9_LSR_5"},
   1426                            {{gt, r4, r10, r13, LSR, 15},
   1427                             false,
   1428                             al,
   1429                             "gt r4 r10 r13 LSR 15",
   1430                             "gt_r4_r10_r13_LSR_15"},
   1431                            {{mi, r5, r13, r14, LSR, 30},
   1432                             false,
   1433                             al,
   1434                             "mi r5 r13 r14 LSR 30",
   1435                             "mi_r5_r13_r14_LSR_30"},
   1436                            {{ge, r2, r13, r12, LSR, 12},
   1437                             false,
   1438                             al,
   1439                             "ge r2 r13 r12 LSR 12",
   1440                             "ge_r2_r13_r12_LSR_12"},
   1441                            {{ge, r0, r3, r2, LSR, 2},
   1442                             false,
   1443                             al,
   1444                             "ge r0 r3 r2 LSR 2",
   1445                             "ge_r0_r3_r2_LSR_2"},
   1446                            {{lt, r12, r10, r0, LSR, 7},
   1447                             false,
   1448                             al,
   1449                             "lt r12 r10 r0 LSR 7",
   1450                             "lt_r12_r10_r0_LSR_7"},
   1451                            {{hi, r11, r8, r0, LSR, 15},
   1452                             false,
   1453                             al,
   1454                             "hi r11 r8 r0 LSR 15",
   1455                             "hi_r11_r8_r0_LSR_15"},
   1456                            {{le, r9, r10, r5, LSR, 31},
   1457                             false,
   1458                             al,
   1459                             "le r9 r10 r5 LSR 31",
   1460                             "le_r9_r10_r5_LSR_31"},
   1461                            {{cs, r5, r3, r3, LSR, 5},
   1462                             false,
   1463                             al,
   1464                             "cs r5 r3 r3 LSR 5",
   1465                             "cs_r5_r3_r3_LSR_5"},
   1466                            {{mi, r8, r0, r4, ASR, 1},
   1467                             false,
   1468                             al,
   1469                             "mi r8 r0 r4 ASR 1",
   1470                             "mi_r8_r0_r4_ASR_1"},
   1471                            {{lt, r2, r6, r10, ASR, 22},
   1472                             false,
   1473                             al,
   1474                             "lt r2 r6 r10 ASR 22",
   1475                             "lt_r2_r6_r10_ASR_22"},
   1476                            {{cc, r8, r4, r12, ASR, 22},
   1477                             false,
   1478                             al,
   1479                             "cc r8 r4 r12 ASR 22",
   1480                             "cc_r8_r4_r12_ASR_22"},
   1481                            {{vc, r10, r0, r12, ASR, 21},
   1482                             false,
   1483                             al,
   1484                             "vc r10 r0 r12 ASR 21",
   1485                             "vc_r10_r0_r12_ASR_21"},
   1486                            {{mi, r14, r8, r9, ASR, 26},
   1487                             false,
   1488                             al,
   1489                             "mi r14 r8 r9 ASR 26",
   1490                             "mi_r14_r8_r9_ASR_26"},
   1491                            {{al, r2, r4, r9, LSR, 23},
   1492                             false,
   1493                             al,
   1494                             "al r2 r4 r9 LSR 23",
   1495                             "al_r2_r4_r9_LSR_23"},
   1496                            {{mi, r3, r0, r0, ASR, 22},
   1497                             false,
   1498                             al,
   1499                             "mi r3 r0 r0 ASR 22",
   1500                             "mi_r3_r0_r0_ASR_22"},
   1501                            {{ge, r6, r0, r7, ASR, 8},
   1502                             false,
   1503                             al,
   1504                             "ge r6 r0 r7 ASR 8",
   1505                             "ge_r6_r0_r7_ASR_8"},
   1506                            {{ls, r7, r14, r8, ASR, 23},
   1507                             false,
   1508                             al,
   1509                             "ls r7 r14 r8 ASR 23",
   1510                             "ls_r7_r14_r8_ASR_23"},
   1511                            {{ne, r6, r5, r12, LSR, 30},
   1512                             false,
   1513                             al,
   1514                             "ne r6 r5 r12 LSR 30",
   1515                             "ne_r6_r5_r12_LSR_30"},
   1516                            {{ge, r5, r1, r3, ASR, 29},
   1517                             false,
   1518                             al,
   1519                             "ge r5 r1 r3 ASR 29",
   1520                             "ge_r5_r1_r3_ASR_29"},
   1521                            {{cc, r2, r10, r2, ASR, 17},
   1522                             false,
   1523                             al,
   1524                             "cc r2 r10 r2 ASR 17",
   1525                             "cc_r2_r10_r2_ASR_17"},
   1526                            {{ne, r6, r4, r3, LSR, 2},
   1527                             false,
   1528                             al,
   1529                             "ne r6 r4 r3 LSR 2",
   1530                             "ne_r6_r4_r3_LSR_2"},
   1531                            {{vs, r10, r13, r11, LSR, 19},
   1532                             false,
   1533                             al,
   1534                             "vs r10 r13 r11 LSR 19",
   1535                             "vs_r10_r13_r11_LSR_19"},
   1536                            {{hi, r0, r0, r8, LSR, 27},
   1537                             false,
   1538                             al,
   1539                             "hi r0 r0 r8 LSR 27",
   1540                             "hi_r0_r0_r8_LSR_27"},
   1541                            {{gt, r4, r3, r9, LSR, 16},
   1542                             false,
   1543                             al,
   1544                             "gt r4 r3 r9 LSR 16",
   1545                             "gt_r4_r3_r9_LSR_16"},
   1546                            {{lt, r13, r11, r1, LSR, 21},
   1547                             false,
   1548                             al,
   1549                             "lt r13 r11 r1 LSR 21",
   1550                             "lt_r13_r11_r1_LSR_21"},
   1551                            {{mi, r13, r10, r2, LSR, 30},
   1552                             false,
   1553                             al,
   1554                             "mi r13 r10 r2 LSR 30",
   1555                             "mi_r13_r10_r2_LSR_30"},
   1556                            {{mi, r4, r13, r2, LSR, 19},
   1557                             false,
   1558                             al,
   1559                             "mi r4 r13 r2 LSR 19",
   1560                             "mi_r4_r13_r2_LSR_19"},
   1561                            {{vs, r6, r3, r5, LSR, 8},
   1562                             false,
   1563                             al,
   1564                             "vs r6 r3 r5 LSR 8",
   1565                             "vs_r6_r3_r5_LSR_8"},
   1566                            {{ls, r9, r12, r9, ASR, 28},
   1567                             false,
   1568                             al,
   1569                             "ls r9 r12 r9 ASR 28",
   1570                             "ls_r9_r12_r9_ASR_28"},
   1571                            {{al, r1, r2, r2, ASR, 3},
   1572                             false,
   1573                             al,
   1574                             "al r1 r2 r2 ASR 3",
   1575                             "al_r1_r2_r2_ASR_3"},
   1576                            {{ls, r11, r11, r3, LSR, 2},
   1577                             false,
   1578                             al,
   1579                             "ls r11 r11 r3 LSR 2",
   1580                             "ls_r11_r11_r3_LSR_2"},
   1581                            {{al, r10, r3, r5, LSR, 2},
   1582                             false,
   1583                             al,
   1584                             "al r10 r3 r5 LSR 2",
   1585                             "al_r10_r3_r5_LSR_2"},
   1586                            {{eq, r1, r11, r1, LSR, 14},
   1587                             false,
   1588                             al,
   1589                             "eq r1 r11 r1 LSR 14",
   1590                             "eq_r1_r11_r1_LSR_14"},
   1591                            {{mi, r0, r1, r4, ASR, 12},
   1592                             false,
   1593                             al,
   1594                             "mi r0 r1 r4 ASR 12",
   1595                             "mi_r0_r1_r4_ASR_12"},
   1596                            {{pl, r0, r3, r0, LSR, 5},
   1597                             false,
   1598                             al,
   1599                             "pl r0 r3 r0 LSR 5",
   1600                             "pl_r0_r3_r0_LSR_5"},
   1601                            {{mi, r2, r2, r8, LSR, 27},
   1602                             false,
   1603                             al,
   1604                             "mi r2 r2 r8 LSR 27",
   1605                             "mi_r2_r2_r8_LSR_27"},
   1606                            {{ls, r13, r1, r13, LSR, 20},
   1607                             false,
   1608                             al,
   1609                             "ls r13 r1 r13 LSR 20",
   1610                             "ls_r13_r1_r13_LSR_20"},
   1611                            {{cs, r1, r4, r1, ASR, 5},
   1612                             false,
   1613                             al,
   1614                             "cs r1 r4 r1 ASR 5",
   1615                             "cs_r1_r4_r1_ASR_5"},
   1616                            {{ge, r5, r9, r1, ASR, 6},
   1617                             false,
   1618                             al,
   1619                             "ge r5 r9 r1 ASR 6",
   1620                             "ge_r5_r9_r1_ASR_6"},
   1621                            {{cc, r7, r8, r11, LSR, 30},
   1622                             false,
   1623                             al,
   1624                             "cc r7 r8 r11 LSR 30",
   1625                             "cc_r7_r8_r11_LSR_30"},
   1626                            {{le, r1, r10, r8, LSR, 12},
   1627                             false,
   1628                             al,
   1629                             "le r1 r10 r8 LSR 12",
   1630                             "le_r1_r10_r8_LSR_12"},
   1631                            {{gt, r5, r5, r9, LSR, 6},
   1632                             false,
   1633                             al,
   1634                             "gt r5 r5 r9 LSR 6",
   1635                             "gt_r5_r5_r9_LSR_6"},
   1636                            {{eq, r14, r11, r13, LSR, 21},
   1637                             false,
   1638                             al,
   1639                             "eq r14 r11 r13 LSR 21",
   1640                             "eq_r14_r11_r13_LSR_21"},
   1641                            {{hi, r4, r10, r7, ASR, 29},
   1642                             false,
   1643                             al,
   1644                             "hi r4 r10 r7 ASR 29",
   1645                             "hi_r4_r10_r7_ASR_29"},
   1646                            {{ls, r12, r6, r13, LSR, 30},
   1647                             false,
   1648                             al,
   1649                             "ls r12 r6 r13 LSR 30",
   1650                             "ls_r12_r6_r13_LSR_30"},
   1651                            {{cc, r1, r2, r13, ASR, 31},
   1652                             false,
   1653                             al,
   1654                             "cc r1 r2 r13 ASR 31",
   1655                             "cc_r1_r2_r13_ASR_31"},
   1656                            {{cs, r4, r12, r12, ASR, 31},
   1657                             false,
   1658                             al,
   1659                             "cs r4 r12 r12 ASR 31",
   1660                             "cs_r4_r12_r12_ASR_31"},
   1661                            {{cs, r10, r8, r8, LSR, 25},
   1662                             false,
   1663                             al,
   1664                             "cs r10 r8 r8 LSR 25",
   1665                             "cs_r10_r8_r8_LSR_25"},
   1666                            {{eq, r11, r14, r12, ASR, 9},
   1667                             false,
   1668                             al,
   1669                             "eq r11 r14 r12 ASR 9",
   1670                             "eq_r11_r14_r12_ASR_9"},
   1671                            {{pl, r8, r7, r6, LSR, 29},
   1672                             false,
   1673                             al,
   1674                             "pl r8 r7 r6 LSR 29",
   1675                             "pl_r8_r7_r6_LSR_29"},
   1676                            {{vs, r2, r3, r12, ASR, 15},
   1677                             false,
   1678                             al,
   1679                             "vs r2 r3 r12 ASR 15",
   1680                             "vs_r2_r3_r12_ASR_15"},
   1681                            {{vs, r10, r11, r9, ASR, 31},
   1682                             false,
   1683                             al,
   1684                             "vs r10 r11 r9 ASR 31",
   1685                             "vs_r10_r11_r9_ASR_31"},
   1686                            {{mi, r2, r4, r13, ASR, 2},
   1687                             false,
   1688                             al,
   1689                             "mi r2 r4 r13 ASR 2",
   1690                             "mi_r2_r4_r13_ASR_2"},
   1691                            {{ls, r3, r0, r1, LSR, 25},
   1692                             false,
   1693                             al,
   1694                             "ls r3 r0 r1 LSR 25",
   1695                             "ls_r3_r0_r1_LSR_25"},
   1696                            {{pl, r7, r2, r12, LSR, 16},
   1697                             false,
   1698                             al,
   1699                             "pl r7 r2 r12 LSR 16",
   1700                             "pl_r7_r2_r12_LSR_16"},
   1701                            {{ge, r6, r14, r9, ASR, 30},
   1702                             false,
   1703                             al,
   1704                             "ge r6 r14 r9 ASR 30",
   1705                             "ge_r6_r14_r9_ASR_30"},
   1706                            {{pl, r2, r5, r4, ASR, 11},
   1707                             false,
   1708                             al,
   1709                             "pl r2 r5 r4 ASR 11",
   1710                             "pl_r2_r5_r4_ASR_11"},
   1711                            {{al, r5, r10, r11, ASR, 23},
   1712                             false,
   1713                             al,
   1714                             "al r5 r10 r11 ASR 23",
   1715                             "al_r5_r10_r11_ASR_23"},
   1716                            {{le, r4, r1, r9, LSR, 28},
   1717                             false,
   1718                             al,
   1719                             "le r4 r1 r9 LSR 28",
   1720                             "le_r4_r1_r9_LSR_28"},
   1721                            {{cc, r13, r4, r2, ASR, 25},
   1722                             false,
   1723                             al,
   1724                             "cc r13 r4 r2 ASR 25",
   1725                             "cc_r13_r4_r2_ASR_25"},
   1726                            {{pl, r7, r7, r8, LSR, 9},
   1727                             false,
   1728                             al,
   1729                             "pl r7 r7 r8 LSR 9",
   1730                             "pl_r7_r7_r8_LSR_9"},
   1731                            {{le, r8, r11, r0, ASR, 13},
   1732                             false,
   1733                             al,
   1734                             "le r8 r11 r0 ASR 13",
   1735                             "le_r8_r11_r0_ASR_13"},
   1736                            {{eq, r11, r9, r12, ASR, 32},
   1737                             false,
   1738                             al,
   1739                             "eq r11 r9 r12 ASR 32",
   1740                             "eq_r11_r9_r12_ASR_32"},
   1741                            {{ls, r4, r0, r10, ASR, 31},
   1742                             false,
   1743                             al,
   1744                             "ls r4 r0 r10 ASR 31",
   1745                             "ls_r4_r0_r10_ASR_31"},
   1746                            {{gt, r10, r8, r4, LSR, 22},
   1747                             false,
   1748                             al,
   1749                             "gt r10 r8 r4 LSR 22",
   1750                             "gt_r10_r8_r4_LSR_22"},
   1751                            {{ne, r9, r8, r0, ASR, 21},
   1752                             false,
   1753                             al,
   1754                             "ne r9 r8 r0 ASR 21",
   1755                             "ne_r9_r8_r0_ASR_21"},
   1756                            {{lt, r11, r9, r9, ASR, 27},
   1757                             false,
   1758                             al,
   1759                             "lt r11 r9 r9 ASR 27",
   1760                             "lt_r11_r9_r9_ASR_27"},
   1761                            {{vc, r14, r6, r14, LSR, 22},
   1762                             false,
   1763                             al,
   1764                             "vc r14 r6 r14 LSR 22",
   1765                             "vc_r14_r6_r14_LSR_22"},
   1766                            {{vs, r12, r4, r14, LSR, 12},
   1767                             false,
   1768                             al,
   1769                             "vs r12 r4 r14 LSR 12",
   1770                             "vs_r12_r4_r14_LSR_12"},
   1771                            {{lt, r7, r11, r6, ASR, 9},
   1772                             false,
   1773                             al,
   1774                             "lt r7 r11 r6 ASR 9",
   1775                             "lt_r7_r11_r6_ASR_9"},
   1776                            {{lt, r3, r13, r5, LSR, 8},
   1777                             false,
   1778                             al,
   1779                             "lt r3 r13 r5 LSR 8",
   1780                             "lt_r3_r13_r5_LSR_8"},
   1781                            {{le, r2, r7, r6, ASR, 11},
   1782                             false,
   1783                             al,
   1784                             "le r2 r7 r6 ASR 11",
   1785                             "le_r2_r7_r6_ASR_11"},
   1786                            {{vc, r2, r0, r4, ASR, 25},
   1787                             false,
   1788                             al,
   1789                             "vc r2 r0 r4 ASR 25",
   1790                             "vc_r2_r0_r4_ASR_25"},
   1791                            {{lt, r2, r11, r10, LSR, 10},
   1792                             false,
   1793                             al,
   1794                             "lt r2 r11 r10 LSR 10",
   1795                             "lt_r2_r11_r10_LSR_10"},
   1796                            {{al, r7, r9, r12, ASR, 13},
   1797                             false,
   1798                             al,
   1799                             "al r7 r9 r12 ASR 13",
   1800                             "al_r7_r9_r12_ASR_13"},
   1801                            {{cs, r13, r0, r2, LSR, 2},
   1802                             false,
   1803                             al,
   1804                             "cs r13 r0 r2 LSR 2",
   1805                             "cs_r13_r0_r2_LSR_2"},
   1806                            {{cc, r0, r6, r0, LSR, 23},
   1807                             false,
   1808                             al,
   1809                             "cc r0 r6 r0 LSR 23",
   1810                             "cc_r0_r6_r0_LSR_23"},
   1811                            {{vc, r10, r2, r12, LSR, 21},
   1812                             false,
   1813                             al,
   1814                             "vc r10 r2 r12 LSR 21",
   1815                             "vc_r10_r2_r12_LSR_21"},
   1816                            {{mi, r0, r1, r6, ASR, 28},
   1817                             false,
   1818                             al,
   1819                             "mi r0 r1 r6 ASR 28",
   1820                             "mi_r0_r1_r6_ASR_28"},
   1821                            {{hi, r0, r12, r1, LSR, 23},
   1822                             false,
   1823                             al,
   1824                             "hi r0 r12 r1 LSR 23",
   1825                             "hi_r0_r12_r1_LSR_23"},
   1826                            {{eq, r10, r7, r3, ASR, 6},
   1827                             false,
   1828                             al,
   1829                             "eq r10 r7 r3 ASR 6",
   1830                             "eq_r10_r7_r3_ASR_6"},
   1831                            {{hi, r9, r13, r9, ASR, 9},
   1832                             false,
   1833                             al,
   1834                             "hi r9 r13 r9 ASR 9",
   1835                             "hi_r9_r13_r9_ASR_9"},
   1836                            {{le, r4, r14, r1, LSR, 13},
   1837                             false,
   1838                             al,
   1839                             "le r4 r14 r1 LSR 13",
   1840                             "le_r4_r14_r1_LSR_13"},
   1841                            {{vs, r9, r12, r12, LSR, 2},
   1842                             false,
   1843                             al,
   1844                             "vs r9 r12 r12 LSR 2",
   1845                             "vs_r9_r12_r12_LSR_2"},
   1846                            {{vc, r11, r3, r4, ASR, 7},
   1847                             false,
   1848                             al,
   1849                             "vc r11 r3 r4 ASR 7",
   1850                             "vc_r11_r3_r4_ASR_7"},
   1851                            {{mi, r13, r8, r3, LSR, 8},
   1852                             false,
   1853                             al,
   1854                             "mi r13 r8 r3 LSR 8",
   1855                             "mi_r13_r8_r3_LSR_8"},
   1856                            {{eq, r6, r12, r1, LSR, 12},
   1857                             false,
   1858                             al,
   1859                             "eq r6 r12 r1 LSR 12",
   1860                             "eq_r6_r12_r1_LSR_12"},
   1861                            {{le, r10, r11, r4, LSR, 27},
   1862                             false,
   1863                             al,
   1864                             "le r10 r11 r4 LSR 27",
   1865                             "le_r10_r11_r4_LSR_27"},
   1866                            {{le, r7, r0, r1, ASR, 15},
   1867                             false,
   1868                             al,
   1869                             "le r7 r0 r1 ASR 15",
   1870                             "le_r7_r0_r1_ASR_15"},
   1871                            {{ne, r12, r0, r10, ASR, 13},
   1872                             false,
   1873                             al,
   1874                             "ne r12 r0 r10 ASR 13",
   1875                             "ne_r12_r0_r10_ASR_13"},
   1876                            {{hi, r1, r11, r12, ASR, 1},
   1877                             false,
   1878                             al,
   1879                             "hi r1 r11 r12 ASR 1",
   1880                             "hi_r1_r11_r12_ASR_1"},
   1881                            {{cs, r2, r12, r10, ASR, 28},
   1882                             false,
   1883                             al,
   1884                             "cs r2 r12 r10 ASR 28",
   1885                             "cs_r2_r12_r10_ASR_28"},
   1886                            {{vc, r0, r7, r14, LSR, 4},
   1887                             false,
   1888                             al,
   1889                             "vc r0 r7 r14 LSR 4",
   1890                             "vc_r0_r7_r14_LSR_4"},
   1891                            {{gt, r9, r8, r6, LSR, 6},
   1892                             false,
   1893                             al,
   1894                             "gt r9 r8 r6 LSR 6",
   1895                             "gt_r9_r8_r6_LSR_6"},
   1896                            {{cc, r9, r8, r11, ASR, 5},
   1897                             false,
   1898                             al,
   1899                             "cc r9 r8 r11 ASR 5",
   1900                             "cc_r9_r8_r11_ASR_5"},
   1901                            {{le, r0, r12, r4, ASR, 22},
   1902                             false,
   1903                             al,
   1904                             "le r0 r12 r4 ASR 22",
   1905                             "le_r0_r12_r4_ASR_22"},
   1906                            {{vs, r6, r4, r14, ASR, 2},
   1907                             false,
   1908                             al,
   1909                             "vs r6 r4 r14 ASR 2",
   1910                             "vs_r6_r4_r14_ASR_2"},
   1911                            {{le, r1, r13, r12, ASR, 14},
   1912                             false,
   1913                             al,
   1914                             "le r1 r13 r12 ASR 14",
   1915                             "le_r1_r13_r12_ASR_14"},
   1916                            {{le, r0, r3, r3, LSR, 6},
   1917                             false,
   1918                             al,
   1919                             "le r0 r3 r3 LSR 6",
   1920                             "le_r0_r3_r3_LSR_6"},
   1921                            {{ls, r2, r7, r3, ASR, 23},
   1922                             false,
   1923                             al,
   1924                             "ls r2 r7 r3 ASR 23",
   1925                             "ls_r2_r7_r3_ASR_23"},
   1926                            {{ge, r12, r3, r11, LSR, 13},
   1927                             false,
   1928                             al,
   1929                             "ge r12 r3 r11 LSR 13",
   1930                             "ge_r12_r3_r11_LSR_13"},
   1931                            {{ne, r3, r0, r9, LSR, 16},
   1932                             false,
   1933                             al,
   1934                             "ne r3 r0 r9 LSR 16",
   1935                             "ne_r3_r0_r9_LSR_16"},
   1936                            {{ge, r5, r14, r10, ASR, 24},
   1937                             false,
   1938                             al,
   1939                             "ge r5 r14 r10 ASR 24",
   1940                             "ge_r5_r14_r10_ASR_24"},
   1941                            {{eq, r14, r4, r1, ASR, 16},
   1942                             false,
   1943                             al,
   1944                             "eq r14 r4 r1 ASR 16",
   1945                             "eq_r14_r4_r1_ASR_16"},
   1946                            {{cs, r5, r1, r9, ASR, 17},
   1947                             false,
   1948                             al,
   1949                             "cs r5 r1 r9 ASR 17",
   1950                             "cs_r5_r1_r9_ASR_17"},
   1951                            {{mi, r4, r7, r2, LSR, 17},
   1952                             false,
   1953                             al,
   1954                             "mi r4 r7 r2 LSR 17",
   1955                             "mi_r4_r7_r2_LSR_17"},
   1956                            {{ne, r9, r0, r7, LSR, 18},
   1957                             false,
   1958                             al,
   1959                             "ne r9 r0 r7 LSR 18",
   1960                             "ne_r9_r0_r7_LSR_18"},
   1961                            {{al, r5, r2, r13, LSR, 12},
   1962                             false,
   1963                             al,
   1964                             "al r5 r2 r13 LSR 12",
   1965                             "al_r5_r2_r13_LSR_12"},
   1966                            {{pl, r12, r13, r1, LSR, 28},
   1967                             false,
   1968                             al,
   1969                             "pl r12 r13 r1 LSR 28",
   1970                             "pl_r12_r13_r1_LSR_28"},
   1971                            {{vc, r9, r7, r4, ASR, 7},
   1972                             false,
   1973                             al,
   1974                             "vc r9 r7 r4 ASR 7",
   1975                             "vc_r9_r7_r4_ASR_7"},
   1976                            {{le, r4, r11, r9, ASR, 5},
   1977                             false,
   1978                             al,
   1979                             "le r4 r11 r9 ASR 5",
   1980                             "le_r4_r11_r9_ASR_5"},
   1981                            {{cc, r1, r14, r3, ASR, 26},
   1982                             false,
   1983                             al,
   1984                             "cc r1 r14 r3 ASR 26",
   1985                             "cc_r1_r14_r3_ASR_26"},
   1986                            {{le, r1, r2, r1, LSR, 27},
   1987                             false,
   1988                             al,
   1989                             "le r1 r2 r1 LSR 27",
   1990                             "le_r1_r2_r1_LSR_27"},
   1991                            {{ge, r14, r0, r5, LSR, 11},
   1992                             false,
   1993                             al,
   1994                             "ge r14 r0 r5 LSR 11",
   1995                             "ge_r14_r0_r5_LSR_11"},
   1996                            {{cc, r5, r5, r0, ASR, 19},
   1997                             false,
   1998                             al,
   1999                             "cc r5 r5 r0 ASR 19",
   2000                             "cc_r5_r5_r0_ASR_19"},
   2001                            {{ne, r11, r11, r6, LSR, 4},
   2002                             false,
   2003                             al,
   2004                             "ne r11 r11 r6 LSR 4",
   2005                             "ne_r11_r11_r6_LSR_4"},
   2006                            {{vc, r13, r10, r9, LSR, 18},
   2007                             false,
   2008                             al,
   2009                             "vc r13 r10 r9 LSR 18",
   2010                             "vc_r13_r10_r9_LSR_18"},
   2011                            {{hi, r10, r10, r7, ASR, 26},
   2012                             false,
   2013                             al,
   2014                             "hi r10 r10 r7 ASR 26",
   2015                             "hi_r10_r10_r7_ASR_26"},
   2016                            {{al, r2, r8, r12, ASR, 21},
   2017                             false,
   2018                             al,
   2019                             "al r2 r8 r12 ASR 21",
   2020                             "al_r2_r8_r12_ASR_21"},
   2021                            {{vc, r5, r4, r6, LSR, 5},
   2022                             false,
   2023                             al,
   2024                             "vc r5 r4 r6 LSR 5",
   2025                             "vc_r5_r4_r6_LSR_5"},
   2026                            {{cc, r0, r9, r7, LSR, 24},
   2027                             false,
   2028                             al,
   2029                             "cc r0 r9 r7 LSR 24",
   2030                             "cc_r0_r9_r7_LSR_24"},
   2031                            {{ls, r10, r9, r3, LSR, 32},
   2032                             false,
   2033                             al,
   2034                             "ls r10 r9 r3 LSR 32",
   2035                             "ls_r10_r9_r3_LSR_32"},
   2036                            {{vc, r8, r12, r7, ASR, 14},
   2037                             false,
   2038                             al,
   2039                             "vc r8 r12 r7 ASR 14",
   2040                             "vc_r8_r12_r7_ASR_14"},
   2041                            {{le, r6, r13, r8, ASR, 15},
   2042                             false,
   2043                             al,
   2044                             "le r6 r13 r8 ASR 15",
   2045                             "le_r6_r13_r8_ASR_15"},
   2046                            {{le, r0, r0, r13, ASR, 9},
   2047                             false,
   2048                             al,
   2049                             "le r0 r0 r13 ASR 9",
   2050                             "le_r0_r0_r13_ASR_9"},
   2051                            {{eq, r9, r3, r0, ASR, 5},
   2052                             false,
   2053                             al,
   2054                             "eq r9 r3 r0 ASR 5",
   2055                             "eq_r9_r3_r0_ASR_5"},
   2056                            {{mi, r0, r7, r5, LSR, 21},
   2057                             false,
   2058                             al,
   2059                             "mi r0 r7 r5 LSR 21",
   2060                             "mi_r0_r7_r5_LSR_21"},
   2061                            {{mi, r13, r1, r8, LSR, 19},
   2062                             false,
   2063                             al,
   2064                             "mi r13 r1 r8 LSR 19",
   2065                             "mi_r13_r1_r8_LSR_19"},
   2066                            {{le, r7, r0, r7, ASR, 26},
   2067                             false,
   2068                             al,
   2069                             "le r7 r0 r7 ASR 26",
   2070                             "le_r7_r0_r7_ASR_26"},
   2071                            {{mi, r7, r4, r3, ASR, 20},
   2072                             false,
   2073                             al,
   2074                             "mi r7 r4 r3 ASR 20",
   2075                             "mi_r7_r4_r3_ASR_20"},
   2076                            {{al, r3, r5, r8, ASR, 23},
   2077                             false,
   2078                             al,
   2079                             "al r3 r5 r8 ASR 23",
   2080                             "al_r3_r5_r8_ASR_23"},
   2081                            {{ge, r4, r12, r5, LSR, 28},
   2082                             false,
   2083                             al,
   2084                             "ge r4 r12 r5 LSR 28",
   2085                             "ge_r4_r12_r5_LSR_28"},
   2086                            {{vs, r7, r13, r13, ASR, 1},
   2087                             false,
   2088                             al,
   2089                             "vs r7 r13 r13 ASR 1",
   2090                             "vs_r7_r13_r13_ASR_1"},
   2091                            {{gt, r8, r8, r11, LSR, 23},
   2092                             false,
   2093                             al,
   2094                             "gt r8 r8 r11 LSR 23",
   2095                             "gt_r8_r8_r11_LSR_23"},
   2096                            {{eq, r13, r8, r4, ASR, 7},
   2097                             false,
   2098                             al,
   2099                             "eq r13 r8 r4 ASR 7",
   2100                             "eq_r13_r8_r4_ASR_7"},
   2101                            {{eq, r14, r3, r13, LSR, 12},
   2102                             false,
   2103                             al,
   2104                             "eq r14 r3 r13 LSR 12",
   2105                             "eq_r14_r3_r13_LSR_12"},
   2106                            {{vs, r5, r13, r10, ASR, 21},
   2107                             false,
   2108                             al,
   2109                             "vs r5 r13 r10 ASR 21",
   2110                             "vs_r5_r13_r10_ASR_21"},
   2111                            {{vc, r4, r2, r8, ASR, 31},
   2112                             false,
   2113                             al,
   2114                             "vc r4 r2 r8 ASR 31",
   2115                             "vc_r4_r2_r8_ASR_31"},
   2116                            {{vc, r2, r9, r12, ASR, 18},
   2117                             false,
   2118                             al,
   2119                             "vc r2 r9 r12 ASR 18",
   2120                             "vc_r2_r9_r12_ASR_18"},
   2121                            {{pl, r4, r8, r11, ASR, 3},
   2122                             false,
   2123                             al,
   2124                             "pl r4 r8 r11 ASR 3",
   2125                             "pl_r4_r8_r11_ASR_3"},
   2126                            {{cc, r11, r8, r1, ASR, 13},
   2127                             false,
   2128                             al,
   2129                             "cc r11 r8 r1 ASR 13",
   2130                             "cc_r11_r8_r1_ASR_13"},
   2131                            {{pl, r11, r13, r2, ASR, 11},
   2132                             false,
   2133                             al,
   2134                             "pl r11 r13 r2 ASR 11",
   2135                             "pl_r11_r13_r2_ASR_11"},
   2136                            {{ge, r8, r5, r5, LSR, 9},
   2137                             false,
   2138                             al,
   2139                             "ge r8 r5 r5 LSR 9",
   2140                             "ge_r8_r5_r5_LSR_9"},
   2141                            {{mi, r2, r6, r7, LSR, 22},
   2142                             false,
   2143                             al,
   2144                             "mi r2 r6 r7 LSR 22",
   2145                             "mi_r2_r6_r7_LSR_22"},
   2146                            {{cs, r0, r1, r1, LSR, 27},
   2147                             false,
   2148                             al,
   2149                             "cs r0 r1 r1 LSR 27",
   2150                             "cs_r0_r1_r1_LSR_27"},
   2151                            {{vs, r2, r0, r5, ASR, 22},
   2152                             false,
   2153                             al,
   2154                             "vs r2 r0 r5 ASR 22",
   2155                             "vs_r2_r0_r5_ASR_22"},
   2156                            {{cs, r13, r1, r3, ASR, 10},
   2157                             false,
   2158                             al,
   2159                             "cs r13 r1 r3 ASR 10",
   2160                             "cs_r13_r1_r3_ASR_10"},
   2161                            {{vs, r5, r6, r8, LSR, 24},
   2162                             false,
   2163                             al,
   2164                             "vs r5 r6 r8 LSR 24",
   2165                             "vs_r5_r6_r8_LSR_24"},
   2166                            {{ge, r5, r2, r10, LSR, 15},
   2167                             false,
   2168                             al,
   2169                             "ge r5 r2 r10 LSR 15",
   2170                             "ge_r5_r2_r10_LSR_15"},
   2171                            {{hi, r8, r10, r10, ASR, 26},
   2172                             false,
   2173                             al,
   2174                             "hi r8 r10 r10 ASR 26",
   2175                             "hi_r8_r10_r10_ASR_26"},
   2176                            {{vc, r7, r6, r11, LSR, 19},
   2177                             false,
   2178                             al,
   2179                             "vc r7 r6 r11 LSR 19",
   2180                             "vc_r7_r6_r11_LSR_19"},
   2181                            {{ls, r7, r5, r0, LSR, 1},
   2182                             false,
   2183                             al,
   2184                             "ls r7 r5 r0 LSR 1",
   2185                             "ls_r7_r5_r0_LSR_1"},
   2186                            {{al, r9, r4, r12, LSR, 28},
   2187                             false,
   2188                             al,
   2189                             "al r9 r4 r12 LSR 28",
   2190                             "al_r9_r4_r12_LSR_28"},
   2191                            {{vs, r2, r2, r5, ASR, 19},
   2192                             false,
   2193                             al,
   2194                             "vs r2 r2 r5 ASR 19",
   2195                             "vs_r2_r2_r5_ASR_19"},
   2196                            {{mi, r9, r12, r11, LSR, 26},
   2197                             false,
   2198                             al,
   2199                             "mi r9 r12 r11 LSR 26",
   2200                             "mi_r9_r12_r11_LSR_26"},
   2201                            {{ne, r13, r7, r8, LSR, 6},
   2202                             false,
   2203                             al,
   2204                             "ne r13 r7 r8 LSR 6",
   2205                             "ne_r13_r7_r8_LSR_6"},
   2206                            {{al, r13, r7, r0, LSR, 20},
   2207                             false,
   2208                             al,
   2209                             "al r13 r7 r0 LSR 20",
   2210                             "al_r13_r7_r0_LSR_20"},
   2211                            {{eq, r5, r5, r4, ASR, 9},
   2212                             false,
   2213                             al,
   2214                             "eq r5 r5 r4 ASR 9",
   2215                             "eq_r5_r5_r4_ASR_9"},
   2216                            {{le, r7, r11, r10, ASR, 16},
   2217                             false,
   2218                             al,
   2219                             "le r7 r11 r10 ASR 16",
   2220                             "le_r7_r11_r10_ASR_16"},
   2221                            {{lt, r14, r14, r13, LSR, 3},
   2222                             false,
   2223                             al,
   2224                             "lt r14 r14 r13 LSR 3",
   2225                             "lt_r14_r14_r13_LSR_3"},
   2226                            {{pl, r5, r9, r2, ASR, 7},
   2227                             false,
   2228                             al,
   2229                             "pl r5 r9 r2 ASR 7",
   2230                             "pl_r5_r9_r2_ASR_7"},
   2231                            {{cc, r2, r13, r14, LSR, 13},
   2232                             false,
   2233                             al,
   2234                             "cc r2 r13 r14 LSR 13",
   2235                             "cc_r2_r13_r14_LSR_13"},
   2236                            {{gt, r2, r8, r11, ASR, 11},
   2237                             false,
   2238                             al,
   2239                             "gt r2 r8 r11 ASR 11",
   2240                             "gt_r2_r8_r11_ASR_11"},
   2241                            {{hi, r8, r12, r8, ASR, 1},
   2242                             false,
   2243                             al,
   2244                             "hi r8 r12 r8 ASR 1",
   2245                             "hi_r8_r12_r8_ASR_1"},
   2246                            {{cc, r11, r12, r12, LSR, 26},
   2247                             false,
   2248                             al,
   2249                             "cc r11 r12 r12 LSR 26",
   2250                             "cc_r11_r12_r12_LSR_26"},
   2251                            {{eq, r6, r4, r1, ASR, 27},
   2252                             false,
   2253                             al,
   2254                             "eq r6 r4 r1 ASR 27",
   2255                             "eq_r6_r4_r1_ASR_27"},
   2256                            {{eq, r7, r6, r7, ASR, 17},
   2257                             false,
   2258                             al,
   2259                             "eq r7 r6 r7 ASR 17",
   2260                             "eq_r7_r6_r7_ASR_17"},
   2261                            {{mi, r10, r12, r0, LSR, 3},
   2262                             false,
   2263                             al,
   2264                             "mi r10 r12 r0 LSR 3",
   2265                             "mi_r10_r12_r0_LSR_3"},
   2266                            {{ge, r2, r1, r5, ASR, 20},
   2267                             false,
   2268                             al,
   2269                             "ge r2 r1 r5 ASR 20",
   2270                             "ge_r2_r1_r5_ASR_20"},
   2271                            {{lt, r12, r12, r3, ASR, 25},
   2272                             false,
   2273                             al,
   2274                             "lt r12 r12 r3 ASR 25",
   2275                             "lt_r12_r12_r3_ASR_25"},
   2276                            {{mi, r11, r7, r8, ASR, 13},
   2277                             false,
   2278                             al,
   2279                             "mi r11 r7 r8 ASR 13",
   2280                             "mi_r11_r7_r8_ASR_13"},
   2281                            {{al, r5, r5, r13, ASR, 4},
   2282                             false,
   2283                             al,
   2284                             "al r5 r5 r13 ASR 4",
   2285                             "al_r5_r5_r13_ASR_4"},
   2286                            {{eq, r8, r9, r4, LSR, 5},
   2287                             false,
   2288                             al,
   2289                             "eq r8 r9 r4 LSR 5",
   2290                             "eq_r8_r9_r4_LSR_5"},
   2291                            {{ne, r9, r5, r0, LSR, 5},
   2292                             false,
   2293                             al,
   2294                             "ne r9 r5 r0 LSR 5",
   2295                             "ne_r9_r5_r0_LSR_5"},
   2296                            {{hi, r4, r7, r7, ASR, 22},
   2297                             false,
   2298                             al,
   2299                             "hi r4 r7 r7 ASR 22",
   2300                             "hi_r4_r7_r7_ASR_22"},
   2301                            {{al, r13, r12, r14, ASR, 26},
   2302                             false,
   2303                             al,
   2304                             "al r13 r12 r14 ASR 26",
   2305                             "al_r13_r12_r14_ASR_26"},
   2306                            {{lt, r11, r6, r1, ASR, 11},
   2307                             false,
   2308                             al,
   2309                             "lt r11 r6 r1 ASR 11",
   2310                             "lt_r11_r6_r1_ASR_11"},
   2311                            {{cs, r4, r2, r11, LSR, 27},
   2312                             false,
   2313                             al,
   2314                             "cs r4 r2 r11 LSR 27",
   2315                             "cs_r4_r2_r11_LSR_27"},
   2316                            {{cc, r4, r5, r12, LSR, 22},
   2317                             false,
   2318                             al,
   2319                             "cc r4 r5 r12 LSR 22",
   2320                             "cc_r4_r5_r12_LSR_22"},
   2321                            {{mi, r6, r1, r1, LSR, 23},
   2322                             false,
   2323                             al,
   2324                             "mi r6 r1 r1 LSR 23",
   2325                             "mi_r6_r1_r1_LSR_23"},
   2326                            {{eq, r7, r1, r2, LSR, 30},
   2327                             false,
   2328                             al,
   2329                             "eq r7 r1 r2 LSR 30",
   2330                             "eq_r7_r1_r2_LSR_30"},
   2331                            {{al, r2, r13, r12, ASR, 6},
   2332                             false,
   2333                             al,
   2334                             "al r2 r13 r12 ASR 6",
   2335                             "al_r2_r13_r12_ASR_6"},
   2336                            {{ge, r9, r13, r10, ASR, 19},
   2337                             false,
   2338                             al,
   2339                             "ge r9 r13 r10 ASR 19",
   2340                             "ge_r9_r13_r10_ASR_19"},
   2341                            {{le, r1, r10, r9, LSR, 3},
   2342                             false,
   2343                             al,
   2344                             "le r1 r10 r9 LSR 3",
   2345                             "le_r1_r10_r9_LSR_3"},
   2346                            {{le, r3, r11, r9, LSR, 18},
   2347                             false,
   2348                             al,
   2349                             "le r3 r11 r9 LSR 18",
   2350                             "le_r3_r11_r9_LSR_18"},
   2351                            {{vs, r1, r7, r13, LSR, 23},
   2352                             false,
   2353                             al,
   2354                             "vs r1 r7 r13 LSR 23",
   2355                             "vs_r1_r7_r13_LSR_23"},
   2356                            {{cc, r14, r9, r4, ASR, 2},
   2357                             false,
   2358                             al,
   2359                             "cc r14 r9 r4 ASR 2",
   2360                             "cc_r14_r9_r4_ASR_2"},
   2361                            {{mi, r1, r14, r2, ASR, 15},
   2362                             false,
   2363                             al,
   2364                             "mi r1 r14 r2 ASR 15",
   2365                             "mi_r1_r14_r2_ASR_15"},
   2366                            {{ne, r8, r1, r14, ASR, 32},
   2367                             false,
   2368                             al,
   2369                             "ne r8 r1 r14 ASR 32",
   2370                             "ne_r8_r1_r14_ASR_32"},
   2371                            {{hi, r14, r12, r14, LSR, 21},
   2372                             false,
   2373                             al,
   2374                             "hi r14 r12 r14 LSR 21",
   2375                             "hi_r14_r12_r14_LSR_21"},
   2376                            {{lt, r6, r2, r0, LSR, 1},
   2377                             false,
   2378                             al,
   2379                             "lt r6 r2 r0 LSR 1",
   2380                             "lt_r6_r2_r0_LSR_1"},
   2381                            {{ls, r5, r12, r4, ASR, 4},
   2382                             false,
   2383                             al,
   2384                             "ls r5 r12 r4 ASR 4",
   2385                             "ls_r5_r12_r4_ASR_4"},
   2386                            {{vs, r3, r12, r8, ASR, 25},
   2387                             false,
   2388                             al,
   2389                             "vs r3 r12 r8 ASR 25",
   2390                             "vs_r3_r12_r8_ASR_25"},
   2391                            {{hi, r11, r6, r11, LSR, 11},
   2392                             false,
   2393                             al,
   2394                             "hi r11 r6 r11 LSR 11",
   2395                             "hi_r11_r6_r11_LSR_11"},
   2396                            {{vc, r5, r7, r11, LSR, 13},
   2397                             false,
   2398                             al,
   2399                             "vc r5 r7 r11 LSR 13",
   2400                             "vc_r5_r7_r11_LSR_13"},
   2401                            {{cc, r13, r9, r9, LSR, 21},
   2402                             false,
   2403                             al,
   2404                             "cc r13 r9 r9 LSR 21",
   2405                             "cc_r13_r9_r9_LSR_21"},
   2406                            {{al, r3, r14, r14, ASR, 31},
   2407                             false,
   2408                             al,
   2409                             "al r3 r14 r14 ASR 31",
   2410                             "al_r3_r14_r14_ASR_31"},
   2411                            {{ls, r13, r3, r9, LSR, 28},
   2412                             false,
   2413                             al,
   2414                             "ls r13 r3 r9 LSR 28",
   2415                             "ls_r13_r3_r9_LSR_28"},
   2416                            {{pl, r11, r5, r11, ASR, 26},
   2417                             false,
   2418                             al,
   2419                             "pl r11 r5 r11 ASR 26",
   2420                             "pl_r11_r5_r11_ASR_26"},
   2421                            {{cc, r2, r9, r8, ASR, 25},
   2422                             false,
   2423                             al,
   2424                             "cc r2 r9 r8 ASR 25",
   2425                             "cc_r2_r9_r8_ASR_25"},
   2426                            {{al, r10, r2, r6, ASR, 8},
   2427                             false,
   2428                             al,
   2429                             "al r10 r2 r6 ASR 8",
   2430                             "al_r10_r2_r6_ASR_8"},
   2431                            {{vc, r12, r9, r2, ASR, 15},
   2432                             false,
   2433                             al,
   2434                             "vc r12 r9 r2 ASR 15",
   2435                             "vc_r12_r9_r2_ASR_15"},
   2436                            {{vs, r7, r9, r8, LSR, 13},
   2437                             false,
   2438                             al,
   2439                             "vs r7 r9 r8 LSR 13",
   2440                             "vs_r7_r9_r8_LSR_13"},
   2441                            {{pl, r12, r6, r7, ASR, 21},
   2442                             false,
   2443                             al,
   2444                             "pl r12 r6 r7 ASR 21",
   2445                             "pl_r12_r6_r7_ASR_21"},
   2446                            {{eq, r0, r0, r11, ASR, 10},
   2447                             false,
   2448                             al,
   2449                             "eq r0 r0 r11 ASR 10",
   2450                             "eq_r0_r0_r11_ASR_10"},
   2451                            {{lt, r1, r12, r9, LSR, 8},
   2452                             false,
   2453                             al,
   2454                             "lt r1 r12 r9 LSR 8",
   2455                             "lt_r1_r12_r9_LSR_8"},
   2456                            {{hi, r14, r14, r8, LSR, 4},
   2457                             false,
   2458                             al,
   2459                             "hi r14 r14 r8 LSR 4",
   2460                             "hi_r14_r14_r8_LSR_4"},
   2461                            {{vs, r10, r12, r14, LSR, 14},
   2462                             false,
   2463                             al,
   2464                             "vs r10 r12 r14 LSR 14",
   2465                             "vs_r10_r12_r14_LSR_14"},
   2466                            {{lt, r11, r4, r8, ASR, 4},
   2467                             false,
   2468                             al,
   2469                             "lt r11 r4 r8 ASR 4",
   2470                             "lt_r11_r4_r8_ASR_4"},
   2471                            {{hi, r13, r14, r14, LSR, 8},
   2472                             false,
   2473                             al,
   2474                             "hi r13 r14 r14 LSR 8",
   2475                             "hi_r13_r14_r14_LSR_8"},
   2476                            {{al, r0, r7, r8, ASR, 8},
   2477                             false,
   2478                             al,
   2479                             "al r0 r7 r8 ASR 8",
   2480                             "al_r0_r7_r8_ASR_8"},
   2481                            {{cc, r12, r14, r1, ASR, 25},
   2482                             false,
   2483                             al,
   2484                             "cc r12 r14 r1 ASR 25",
   2485                             "cc_r12_r14_r1_ASR_25"},
   2486                            {{pl, r12, r0, r2, LSR, 4},
   2487                             false,
   2488                             al,
   2489                             "pl r12 r0 r2 LSR 4",
   2490                             "pl_r12_r0_r2_LSR_4"},
   2491                            {{pl, r12, r2, r2, LSR, 15},
   2492                             false,
   2493                             al,
   2494                             "pl r12 r2 r2 LSR 15",
   2495                             "pl_r12_r2_r2_LSR_15"},
   2496                            {{gt, r11, r12, r3, LSR, 13},
   2497                             false,
   2498                             al,
   2499                             "gt r11 r12 r3 LSR 13",
   2500                             "gt_r11_r12_r3_LSR_13"},
   2501                            {{al, r2, r7, r6, ASR, 19},
   2502                             false,
   2503                             al,
   2504                             "al r2 r7 r6 ASR 19",
   2505                             "al_r2_r7_r6_ASR_19"},
   2506                            {{eq, r0, r3, r5, LSR, 11},
   2507                             false,
   2508                             al,
   2509                             "eq r0 r3 r5 LSR 11",
   2510                             "eq_r0_r3_r5_LSR_11"},
   2511                            {{mi, r1, r12, r1, LSR, 25},
   2512                             false,
   2513                             al,
   2514                             "mi r1 r12 r1 LSR 25",
   2515                             "mi_r1_r12_r1_LSR_25"},
   2516                            {{hi, r2, r7, r2, LSR, 20},
   2517                             false,
   2518                             al,
   2519                             "hi r2 r7 r2 LSR 20",
   2520                             "hi_r2_r7_r2_LSR_20"},
   2521                            {{gt, r14, r12, r2, LSR, 2},
   2522                             false,
   2523                             al,
   2524                             "gt r14 r12 r2 LSR 2",
   2525                             "gt_r14_r12_r2_LSR_2"},
   2526                            {{gt, r1, r13, r4, LSR, 15},
   2527                             false,
   2528                             al,
   2529                             "gt r1 r13 r4 LSR 15",
   2530                             "gt_r1_r13_r4_LSR_15"},
   2531                            {{lt, r11, r4, r12, ASR, 11},
   2532                             false,
   2533                             al,
   2534                             "lt r11 r4 r12 ASR 11",
   2535                             "lt_r11_r4_r12_ASR_11"},
   2536                            {{cs, r0, r0, r14, LSR, 26},
   2537                             false,
   2538                             al,
   2539                             "cs r0 r0 r14 LSR 26",
   2540                             "cs_r0_r0_r14_LSR_26"},
   2541                            {{lt, r12, r6, r0, LSR, 22},
   2542                             false,
   2543                             al,
   2544                             "lt r12 r6 r0 LSR 22",
   2545                             "lt_r12_r6_r0_LSR_22"},
   2546                            {{al, r11, r8, r2, ASR, 9},
   2547                             false,
   2548                             al,
   2549                             "al r11 r8 r2 ASR 9",
   2550                             "al_r11_r8_r2_ASR_9"},
   2551                            {{ls, r8, r10, r3, ASR, 17},
   2552                             false,
   2553                             al,
   2554                             "ls r8 r10 r3 ASR 17",
   2555                             "ls_r8_r10_r3_ASR_17"},
   2556                            {{hi, r7, r2, r14, LSR, 13},
   2557                             false,
   2558                             al,
   2559                             "hi r7 r2 r14 LSR 13",
   2560                             "hi_r7_r2_r14_LSR_13"},
   2561                            {{hi, r13, r10, r12, ASR, 31},
   2562                             false,
   2563                             al,
   2564                             "hi r13 r10 r12 ASR 31",
   2565                             "hi_r13_r10_r12_ASR_31"},
   2566                            {{cs, r1, r5, r10, ASR, 29},
   2567                             false,
   2568                             al,
   2569                             "cs r1 r5 r10 ASR 29",
   2570                             "cs_r1_r5_r10_ASR_29"},
   2571                            {{lt, r11, r11, r9, LSR, 18},
   2572                             false,
   2573                             al,
   2574                             "lt r11 r11 r9 LSR 18",
   2575                             "lt_r11_r11_r9_LSR_18"},
   2576                            {{gt, r3, r4, r4, LSR, 1},
   2577                             false,
   2578                             al,
   2579                             "gt r3 r4 r4 LSR 1",
   2580                             "gt_r3_r4_r4_LSR_1"},
   2581                            {{ge, r10, r12, r4, LSR, 12},
   2582                             false,
   2583                             al,
   2584                             "ge r10 r12 r4 LSR 12",
   2585                             "ge_r10_r12_r4_LSR_12"},
   2586                            {{hi, r4, r13, r11, ASR, 25},
   2587                             false,
   2588                             al,
   2589                             "hi r4 r13 r11 ASR 25",
   2590                             "hi_r4_r13_r11_ASR_25"},
   2591                            {{le, r0, r8, r4, ASR, 4},
   2592                             false,
   2593                             al,
   2594                             "le r0 r8 r4 ASR 4",
   2595                             "le_r0_r8_r4_ASR_4"},
   2596                            {{mi, r14, r14, r3, LSR, 31},
   2597                             false,
   2598                             al,
   2599                             "mi r14 r14 r3 LSR 31",
   2600                             "mi_r14_r14_r3_LSR_31"},
   2601                            {{gt, r7, r4, r8, ASR, 15},
   2602                             false,
   2603                             al,
   2604                             "gt r7 r4 r8 ASR 15",
   2605                             "gt_r7_r4_r8_ASR_15"},
   2606                            {{eq, r4, r6, r6, ASR, 1},
   2607                             false,
   2608                             al,
   2609                             "eq r4 r6 r6 ASR 1",
   2610                             "eq_r4_r6_r6_ASR_1"},
   2611                            {{vs, r13, r2, r6, ASR, 30},
   2612                             false,
   2613                             al,
   2614                             "vs r13 r2 r6 ASR 30",
   2615                             "vs_r13_r2_r6_ASR_30"}};
   2616 
   2617 // These headers each contain an array of `TestResult` with the reference output
   2618 // values. The reference arrays are names `kReference{mnemonic}`.
   2619 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-adc-a32.h"
   2620 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-adcs-a32.h"
   2621 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-add-a32.h"
   2622 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-adds-a32.h"
   2623 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-and-a32.h"
   2624 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-ands-a32.h"
   2625 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-bic-a32.h"
   2626 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-bics-a32.h"
   2627 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-eor-a32.h"
   2628 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-eors-a32.h"
   2629 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orr-a32.h"
   2630 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orrs-a32.h"
   2631 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsb-a32.h"
   2632 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsbs-a32.h"
   2633 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsc-a32.h"
   2634 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rscs-a32.h"
   2635 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbc-a32.h"
   2636 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbcs-a32.h"
   2637 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sub-a32.h"
   2638 #include "aarch32/traces/assembler-cond-rd-rn-operand-rm-shift-amount-1to32-subs-a32.h"
   2639 
   2640 
   2641 // The maximum number of errors to report in detail for each test.
   2642 const unsigned kErrorReportLimit = 8;
   2643 
   2644 typedef void (MacroAssembler::*Fn)(Condition cond,
   2645                                    Register rd,
   2646                                    Register rn,
   2647                                    const Operand& op);
   2648 
   2649 void TestHelper(Fn instruction,
   2650                 const char* mnemonic,
   2651                 const TestResult reference[]) {
   2652   unsigned total_error_count = 0;
   2653   MacroAssembler masm(BUF_SIZE);
   2654 
   2655   masm.UseA32();
   2656 
   2657   for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
   2658     // Values to pass to the macro-assembler.
   2659     Condition cond = kTests[i].operands.cond;
   2660     Register rd = kTests[i].operands.rd;
   2661     Register rn = kTests[i].operands.rn;
   2662     Register rm = kTests[i].operands.rm;
   2663     ShiftType shift = kTests[i].operands.shift;
   2664     uint32_t amount = kTests[i].operands.amount;
   2665     Operand op(rm, shift, amount);
   2666 
   2667     int32_t start = masm.GetCursorOffset();
   2668     {
   2669       // We never generate more that 4 bytes, as IT instructions are only
   2670       // allowed for narrow encodings.
   2671       ExactAssemblyScope scope(&masm, 4, ExactAssemblyScope::kMaximumSize);
   2672       if (kTests[i].in_it_block) {
   2673         masm.it(kTests[i].it_condition);
   2674       }
   2675       (masm.*instruction)(cond, rd, rn, op);
   2676     }
   2677     int32_t end = masm.GetCursorOffset();
   2678 
   2679     const byte* result_ptr =
   2680         masm.GetBuffer()->GetOffsetAddress<const byte*>(start);
   2681     VIXL_ASSERT(start < end);
   2682     uint32_t result_size = end - start;
   2683 
   2684     if (Test::generate_test_trace()) {
   2685       // Print the result bytes.
   2686       printf("const byte kInstruction_%s_%s[] = {\n",
   2687              mnemonic,
   2688              kTests[i].identifier);
   2689       for (uint32_t j = 0; j < result_size; j++) {
   2690         if (j == 0) {
   2691           printf("  0x%02" PRIx8, result_ptr[j]);
   2692         } else {
   2693           printf(", 0x%02" PRIx8, result_ptr[j]);
   2694         }
   2695       }
   2696       // This comment is meant to be used by external tools to validate
   2697       // the encoding. We can parse the comment to figure out what
   2698       // instruction this corresponds to.
   2699       if (kTests[i].in_it_block) {
   2700         printf(" // It %s; %s %s\n};\n",
   2701                kTests[i].it_condition.GetName(),
   2702                mnemonic,
   2703                kTests[i].operands_description);
   2704       } else {
   2705         printf(" // %s %s\n};\n", mnemonic, kTests[i].operands_description);
   2706       }
   2707     } else {
   2708       // Check we've emitted the exact same encoding as present in the
   2709       // trace file. Only print up to `kErrorReportLimit` errors.
   2710       if (((result_size != reference[i].size) ||
   2711            (memcmp(result_ptr, reference[i].encoding, reference[i].size) !=
   2712             0)) &&
   2713           (++total_error_count <= kErrorReportLimit)) {
   2714         printf("Error when testing \"%s\" with operands \"%s\":\n",
   2715                mnemonic,
   2716                kTests[i].operands_description);
   2717         printf("  Expected: ");
   2718         for (uint32_t j = 0; j < reference[i].size; j++) {
   2719           if (j == 0) {
   2720             printf("0x%02" PRIx8, reference[i].encoding[j]);
   2721           } else {
   2722             printf(", 0x%02" PRIx8, reference[i].encoding[j]);
   2723           }
   2724         }
   2725         printf("\n");
   2726         printf("  Found:    ");
   2727         for (uint32_t j = 0; j < result_size; j++) {
   2728           if (j == 0) {
   2729             printf("0x%02" PRIx8, result_ptr[j]);
   2730           } else {
   2731             printf(", 0x%02" PRIx8, result_ptr[j]);
   2732           }
   2733         }
   2734         printf("\n");
   2735       }
   2736     }
   2737   }
   2738 
   2739   masm.FinalizeCode();
   2740 
   2741   if (Test::generate_test_trace()) {
   2742     // Finalize the trace file by writing the final `TestResult` array
   2743     // which links all generated instruction encodings.
   2744     printf("const TestResult kReference%s[] = {\n", mnemonic);
   2745     for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
   2746       printf("  {\n");
   2747       printf("    ARRAY_SIZE(kInstruction_%s_%s),\n",
   2748              mnemonic,
   2749              kTests[i].identifier);
   2750       printf("    kInstruction_%s_%s,\n", mnemonic, kTests[i].identifier);
   2751       printf("  },\n");
   2752     }
   2753     printf("};\n");
   2754   } else {
   2755     if (total_error_count > kErrorReportLimit) {
   2756       printf("%u other errors follow.\n",
   2757              total_error_count - kErrorReportLimit);
   2758     }
   2759     // Crash if the test failed.
   2760     VIXL_CHECK(total_error_count == 0);
   2761   }
   2762 }
   2763 
   2764 // Instantiate tests for each instruction in the list.
   2765 #define TEST(mnemonic)                                                        \
   2766   void Test_##mnemonic() {                                                    \
   2767     TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic);   \
   2768   }                                                                           \
   2769   Test test_##mnemonic(                                                       \
   2770       "AARCH32_ASSEMBLER_COND_RD_RN_OPERAND_RM_SHIFT_AMOUNT_1TO32_" #mnemonic \
   2771       "_A32",                                                                 \
   2772       &Test_##mnemonic);
   2773 FOREACH_INSTRUCTION(TEST)
   2774 #undef TEST
   2775 
   2776 }  // namespace
   2777 #endif
   2778 
   2779 }  // namespace aarch32
   2780 }  // namespace vixl
   2781