1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // ----------------------------------------------------------------------------- 29 // This file is auto generated from the 30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using 31 // tools/generate_tests.py. 32 // 33 // PLEASE DO NOT EDIT. 34 // ----------------------------------------------------------------------------- 35 36 37 #include "test-runner.h" 38 39 #include "test-utils.h" 40 #include "test-utils-aarch32.h" 41 42 #include "aarch32/assembler-aarch32.h" 43 #include "aarch32/macro-assembler-aarch32.h" 44 45 #define BUF_SIZE (4096) 46 47 namespace vixl { 48 namespace aarch32 { 49 50 // List of instruction mnemonics. 51 #define FOREACH_INSTRUCTION(M) \ 52 M(mul) \ 53 M(muls) \ 54 M(qadd16) \ 55 M(qadd8) \ 56 M(qasx) \ 57 M(qsax) \ 58 M(qsub16) \ 59 M(qsub8) \ 60 M(sdiv) \ 61 M(shadd16) \ 62 M(shadd8) \ 63 M(shasx) \ 64 M(shsax) \ 65 M(shsub16) \ 66 M(shsub8) \ 67 M(smmul) \ 68 M(smmulr) \ 69 M(smuad) \ 70 M(smuadx) \ 71 M(smulbb) \ 72 M(smulbt) \ 73 M(smultb) \ 74 M(smultt) \ 75 M(smulwb) \ 76 M(smulwt) \ 77 M(smusd) \ 78 M(smusdx) \ 79 M(udiv) \ 80 M(uhadd16) \ 81 M(uhadd8) \ 82 M(uhasx) \ 83 M(uhsax) \ 84 M(uhsub16) \ 85 M(uhsub8) \ 86 M(uqadd16) \ 87 M(uqadd8) \ 88 M(uqasx) \ 89 M(uqsax) \ 90 M(uqsub16) \ 91 M(uqsub8) \ 92 M(usad8) \ 93 M(sadd16) \ 94 M(sadd8) \ 95 M(sasx) \ 96 M(sel) \ 97 M(ssax) \ 98 M(ssub16) \ 99 M(ssub8) \ 100 M(uadd16) \ 101 M(uadd8) \ 102 M(uasx) \ 103 M(usax) \ 104 M(usub16) \ 105 M(usub8) \ 106 M(qadd) \ 107 M(qdadd) \ 108 M(qdsub) \ 109 M(qsub) 110 111 112 // The following definitions are defined again in each generated test, therefore 113 // we need to place them in an anomymous namespace. It expresses that they are 114 // local to this file only, and the compiler is not allowed to share these types 115 // across test files during template instantiation. Specifically, `Operands` has 116 // various layouts across generated tests so it absolutely cannot be shared. 117 118 #ifdef VIXL_INCLUDE_TARGET_A32 119 namespace { 120 121 // Values to be passed to the assembler to produce the instruction under test. 122 struct Operands { 123 Condition cond; 124 Register rd; 125 Register rn; 126 Register rm; 127 }; 128 129 // This structure contains all data needed to test one specific 130 // instruction. 131 struct TestData { 132 // The `operands` field represents what to pass to the assembler to 133 // produce the instruction. 134 Operands operands; 135 // True if we need to generate an IT instruction for this test to be valid. 136 bool in_it_block; 137 // The condition to give the IT instruction, this will be set to "al" by 138 // default. 139 Condition it_condition; 140 // Description of the operands, used for error reporting. 141 const char* operands_description; 142 // Unique identifier, used for generating traces. 143 const char* identifier; 144 }; 145 146 struct TestResult { 147 size_t size; 148 const byte* encoding; 149 }; 150 151 // Each element of this array produce one instruction encoding. 152 const TestData kTests[] = 153 {{{hi, r1, r9, r5}, false, al, "hi r1 r9 r5", "hi_r1_r9_r5"}, 154 {{pl, r8, r6, r2}, false, al, "pl r8 r6 r2", "pl_r8_r6_r2"}, 155 {{hi, r5, r8, r2}, false, al, "hi r5 r8 r2", "hi_r5_r8_r2"}, 156 {{vc, r9, r2, r7}, false, al, "vc r9 r2 r7", "vc_r9_r2_r7"}, 157 {{lt, r4, r6, r3}, false, al, "lt r4 r6 r3", "lt_r4_r6_r3"}, 158 {{le, r11, r6, r2}, false, al, "le r11 r6 r2", "le_r11_r6_r2"}, 159 {{cc, r8, r14, r4}, false, al, "cc r8 r14 r4", "cc_r8_r14_r4"}, 160 {{le, r5, r14, r6}, false, al, "le r5 r14 r6", "le_r5_r14_r6"}, 161 {{lt, r6, r1, r0}, false, al, "lt r6 r1 r0", "lt_r6_r1_r0"}, 162 {{lt, r5, r0, r9}, false, al, "lt r5 r0 r9", "lt_r5_r0_r9"}, 163 {{le, r8, r12, r7}, false, al, "le r8 r12 r7", "le_r8_r12_r7"}, 164 {{eq, r7, r14, r6}, false, al, "eq r7 r14 r6", "eq_r7_r14_r6"}, 165 {{cs, r7, r4, r6}, false, al, "cs r7 r4 r6", "cs_r7_r4_r6"}, 166 {{gt, r9, r6, r9}, false, al, "gt r9 r6 r9", "gt_r9_r6_r9"}, 167 {{ne, r13, r9, r1}, false, al, "ne r13 r9 r1", "ne_r13_r9_r1"}, 168 {{ge, r13, r1, r13}, false, al, "ge r13 r1 r13", "ge_r13_r1_r13"}, 169 {{ls, r8, r10, r2}, false, al, "ls r8 r10 r2", "ls_r8_r10_r2"}, 170 {{hi, r0, r13, r5}, false, al, "hi r0 r13 r5", "hi_r0_r13_r5"}, 171 {{pl, r13, r7, r8}, false, al, "pl r13 r7 r8", "pl_r13_r7_r8"}, 172 {{ge, r4, r13, r11}, false, al, "ge r4 r13 r11", "ge_r4_r13_r11"}, 173 {{cs, r5, r10, r5}, false, al, "cs r5 r10 r5", "cs_r5_r10_r5"}, 174 {{cs, r5, r4, r3}, false, al, "cs r5 r4 r3", "cs_r5_r4_r3"}, 175 {{ls, r6, r14, r8}, false, al, "ls r6 r14 r8", "ls_r6_r14_r8"}, 176 {{vs, r3, r8, r6}, false, al, "vs r3 r8 r6", "vs_r3_r8_r6"}, 177 {{vc, r7, r12, r3}, false, al, "vc r7 r12 r3", "vc_r7_r12_r3"}, 178 {{ge, r1, r4, r1}, false, al, "ge r1 r4 r1", "ge_r1_r4_r1"}, 179 {{cc, r4, r7, r10}, false, al, "cc r4 r7 r10", "cc_r4_r7_r10"}, 180 {{cc, r2, r0, r13}, false, al, "cc r2 r0 r13", "cc_r2_r0_r13"}, 181 {{vs, r9, r6, r8}, false, al, "vs r9 r6 r8", "vs_r9_r6_r8"}, 182 {{cs, r14, r11, r13}, false, al, "cs r14 r11 r13", "cs_r14_r11_r13"}, 183 {{pl, r5, r8, r4}, false, al, "pl r5 r8 r4", "pl_r5_r8_r4"}, 184 {{pl, r2, r3, r7}, false, al, "pl r2 r3 r7", "pl_r2_r3_r7"}, 185 {{cs, r7, r12, r14}, false, al, "cs r7 r12 r14", "cs_r7_r12_r14"}, 186 {{hi, r6, r6, r1}, false, al, "hi r6 r6 r1", "hi_r6_r6_r1"}, 187 {{cc, r6, r9, r6}, false, al, "cc r6 r9 r6", "cc_r6_r9_r6"}, 188 {{ne, r12, r12, r0}, false, al, "ne r12 r12 r0", "ne_r12_r12_r0"}, 189 {{cc, r9, r3, r8}, false, al, "cc r9 r3 r8", "cc_r9_r3_r8"}, 190 {{mi, r13, r6, r1}, false, al, "mi r13 r6 r1", "mi_r13_r6_r1"}, 191 {{lt, r4, r8, r6}, false, al, "lt r4 r8 r6", "lt_r4_r8_r6"}, 192 {{hi, r11, r5, r9}, false, al, "hi r11 r5 r9", "hi_r11_r5_r9"}, 193 {{cc, r6, r10, r6}, false, al, "cc r6 r10 r6", "cc_r6_r10_r6"}, 194 {{eq, r10, r10, r5}, false, al, "eq r10 r10 r5", "eq_r10_r10_r5"}, 195 {{al, r5, r4, r11}, false, al, "al r5 r4 r11", "al_r5_r4_r11"}, 196 {{pl, r11, r11, r2}, false, al, "pl r11 r11 r2", "pl_r11_r11_r2"}, 197 {{ls, r6, r14, r12}, false, al, "ls r6 r14 r12", "ls_r6_r14_r12"}, 198 {{vc, r7, r7, r2}, false, al, "vc r7 r7 r2", "vc_r7_r7_r2"}, 199 {{eq, r10, r8, r4}, false, al, "eq r10 r8 r4", "eq_r10_r8_r4"}, 200 {{al, r14, r7, r2}, false, al, "al r14 r7 r2", "al_r14_r7_r2"}, 201 {{cs, r3, r11, r10}, false, al, "cs r3 r11 r10", "cs_r3_r11_r10"}, 202 {{ls, r11, r4, r0}, false, al, "ls r11 r4 r0", "ls_r11_r4_r0"}, 203 {{hi, r11, r8, r9}, false, al, "hi r11 r8 r9", "hi_r11_r8_r9"}, 204 {{vs, r2, r14, r13}, false, al, "vs r2 r14 r13", "vs_r2_r14_r13"}, 205 {{al, r1, r13, r9}, false, al, "al r1 r13 r9", "al_r1_r13_r9"}, 206 {{eq, r3, r9, r13}, false, al, "eq r3 r9 r13", "eq_r3_r9_r13"}, 207 {{ge, r10, r3, r13}, false, al, "ge r10 r3 r13", "ge_r10_r3_r13"}, 208 {{pl, r8, r5, r10}, false, al, "pl r8 r5 r10", "pl_r8_r5_r10"}, 209 {{vc, r8, r11, r6}, false, al, "vc r8 r11 r6", "vc_r8_r11_r6"}, 210 {{eq, r0, r0, r5}, false, al, "eq r0 r0 r5", "eq_r0_r0_r5"}, 211 {{ne, r6, r5, r8}, false, al, "ne r6 r5 r8", "ne_r6_r5_r8"}, 212 {{hi, r5, r13, r3}, false, al, "hi r5 r13 r3", "hi_r5_r13_r3"}, 213 {{ne, r11, r14, r14}, false, al, "ne r11 r14 r14", "ne_r11_r14_r14"}, 214 {{mi, r1, r0, r6}, false, al, "mi r1 r0 r6", "mi_r1_r0_r6"}, 215 {{le, r14, r8, r2}, false, al, "le r14 r8 r2", "le_r14_r8_r2"}, 216 {{eq, r9, r6, r5}, false, al, "eq r9 r6 r5", "eq_r9_r6_r5"}, 217 {{eq, r11, r0, r13}, false, al, "eq r11 r0 r13", "eq_r11_r0_r13"}, 218 {{pl, r4, r5, r14}, false, al, "pl r4 r5 r14", "pl_r4_r5_r14"}, 219 {{cs, r13, r5, r13}, false, al, "cs r13 r5 r13", "cs_r13_r5_r13"}, 220 {{mi, r0, r13, r8}, false, al, "mi r0 r13 r8", "mi_r0_r13_r8"}, 221 {{lt, r2, r13, r3}, false, al, "lt r2 r13 r3", "lt_r2_r13_r3"}, 222 {{ls, r8, r1, r11}, false, al, "ls r8 r1 r11", "ls_r8_r1_r11"}, 223 {{vc, r14, r11, r8}, false, al, "vc r14 r11 r8", "vc_r14_r11_r8"}, 224 {{lt, r4, r13, r12}, false, al, "lt r4 r13 r12", "lt_r4_r13_r12"}, 225 {{eq, r2, r1, r14}, false, al, "eq r2 r1 r14", "eq_r2_r1_r14"}, 226 {{eq, r9, r4, r14}, false, al, "eq r9 r4 r14", "eq_r9_r4_r14"}, 227 {{hi, r10, r6, r13}, false, al, "hi r10 r6 r13", "hi_r10_r6_r13"}, 228 {{ge, r12, r9, r4}, false, al, "ge r12 r9 r4", "ge_r12_r9_r4"}, 229 {{le, r9, r11, r14}, false, al, "le r9 r11 r14", "le_r9_r11_r14"}, 230 {{ls, r0, r9, r5}, false, al, "ls r0 r9 r5", "ls_r0_r9_r5"}, 231 {{mi, r2, r3, r8}, false, al, "mi r2 r3 r8", "mi_r2_r3_r8"}, 232 {{ne, r14, r10, r14}, false, al, "ne r14 r10 r14", "ne_r14_r10_r14"}, 233 {{eq, r6, r2, r10}, false, al, "eq r6 r2 r10", "eq_r6_r2_r10"}, 234 {{lt, r11, r0, r12}, false, al, "lt r11 r0 r12", "lt_r11_r0_r12"}, 235 {{ne, r1, r12, r10}, false, al, "ne r1 r12 r10", "ne_r1_r12_r10"}, 236 {{cc, r1, r0, r2}, false, al, "cc r1 r0 r2", "cc_r1_r0_r2"}, 237 {{al, r5, r5, r7}, false, al, "al r5 r5 r7", "al_r5_r5_r7"}, 238 {{hi, r7, r13, r1}, false, al, "hi r7 r13 r1", "hi_r7_r13_r1"}, 239 {{cs, r4, r4, r9}, false, al, "cs r4 r4 r9", "cs_r4_r4_r9"}, 240 {{eq, r14, r4, r14}, false, al, "eq r14 r4 r14", "eq_r14_r4_r14"}, 241 {{vs, r10, r5, r14}, false, al, "vs r10 r5 r14", "vs_r10_r5_r14"}, 242 {{gt, r4, r3, r11}, false, al, "gt r4 r3 r11", "gt_r4_r3_r11"}, 243 {{ne, r14, r10, r12}, false, al, "ne r14 r10 r12", "ne_r14_r10_r12"}, 244 {{vs, r2, r11, r0}, false, al, "vs r2 r11 r0", "vs_r2_r11_r0"}, 245 {{ge, r5, r12, r7}, false, al, "ge r5 r12 r7", "ge_r5_r12_r7"}, 246 {{mi, r7, r14, r6}, false, al, "mi r7 r14 r6", "mi_r7_r14_r6"}, 247 {{gt, r8, r3, r8}, false, al, "gt r8 r3 r8", "gt_r8_r3_r8"}, 248 {{hi, r9, r14, r3}, false, al, "hi r9 r14 r3", "hi_r9_r14_r3"}, 249 {{vc, r2, r11, r2}, false, al, "vc r2 r11 r2", "vc_r2_r11_r2"}, 250 {{hi, r11, r7, r12}, false, al, "hi r11 r7 r12", "hi_r11_r7_r12"}, 251 {{cs, r6, r4, r11}, false, al, "cs r6 r4 r11", "cs_r6_r4_r11"}, 252 {{cs, r12, r5, r9}, false, al, "cs r12 r5 r9", "cs_r12_r5_r9"}, 253 {{ls, r5, r10, r5}, false, al, "ls r5 r10 r5", "ls_r5_r10_r5"}, 254 {{ls, r0, r9, r13}, false, al, "ls r0 r9 r13", "ls_r0_r9_r13"}, 255 {{lt, r3, r3, r5}, false, al, "lt r3 r3 r5", "lt_r3_r3_r5"}, 256 {{mi, r0, r12, r8}, false, al, "mi r0 r12 r8", "mi_r0_r12_r8"}, 257 {{pl, r3, r12, r12}, false, al, "pl r3 r12 r12", "pl_r3_r12_r12"}, 258 {{eq, r8, r12, r5}, false, al, "eq r8 r12 r5", "eq_r8_r12_r5"}, 259 {{cc, r7, r8, r1}, false, al, "cc r7 r8 r1", "cc_r7_r8_r1"}, 260 {{hi, r2, r13, r10}, false, al, "hi r2 r13 r10", "hi_r2_r13_r10"}, 261 {{al, r7, r10, r10}, false, al, "al r7 r10 r10", "al_r7_r10_r10"}, 262 {{vc, r1, r12, r2}, false, al, "vc r1 r12 r2", "vc_r1_r12_r2"}, 263 {{cc, r8, r5, r8}, false, al, "cc r8 r5 r8", "cc_r8_r5_r8"}, 264 {{ls, r3, r7, r9}, false, al, "ls r3 r7 r9", "ls_r3_r7_r9"}, 265 {{al, r8, r10, r8}, false, al, "al r8 r10 r8", "al_r8_r10_r8"}, 266 {{lt, r4, r12, r10}, false, al, "lt r4 r12 r10", "lt_r4_r12_r10"}, 267 {{ge, r10, r5, r11}, false, al, "ge r10 r5 r11", "ge_r10_r5_r11"}, 268 {{ls, r3, r14, r4}, false, al, "ls r3 r14 r4", "ls_r3_r14_r4"}, 269 {{hi, r3, r6, r12}, false, al, "hi r3 r6 r12", "hi_r3_r6_r12"}, 270 {{hi, r6, r0, r4}, false, al, "hi r6 r0 r4", "hi_r6_r0_r4"}, 271 {{al, r11, r6, r0}, false, al, "al r11 r6 r0", "al_r11_r6_r0"}, 272 {{mi, r3, r1, r9}, false, al, "mi r3 r1 r9", "mi_r3_r1_r9"}, 273 {{mi, r12, r13, r0}, false, al, "mi r12 r13 r0", "mi_r12_r13_r0"}, 274 {{le, r1, r2, r5}, false, al, "le r1 r2 r5", "le_r1_r2_r5"}, 275 {{hi, r4, r3, r14}, false, al, "hi r4 r3 r14", "hi_r4_r3_r14"}, 276 {{eq, r6, r11, r11}, false, al, "eq r6 r11 r11", "eq_r6_r11_r11"}, 277 {{cc, r14, r11, r14}, false, al, "cc r14 r11 r14", "cc_r14_r11_r14"}, 278 {{hi, r4, r10, r0}, false, al, "hi r4 r10 r0", "hi_r4_r10_r0"}, 279 {{cc, r7, r11, r1}, false, al, "cc r7 r11 r1", "cc_r7_r11_r1"}, 280 {{mi, r14, r6, r10}, false, al, "mi r14 r6 r10", "mi_r14_r6_r10"}, 281 {{eq, r2, r0, r11}, false, al, "eq r2 r0 r11", "eq_r2_r0_r11"}, 282 {{mi, r13, r5, r12}, false, al, "mi r13 r5 r12", "mi_r13_r5_r12"}, 283 {{eq, r2, r12, r5}, false, al, "eq r2 r12 r5", "eq_r2_r12_r5"}, 284 {{le, r12, r0, r2}, false, al, "le r12 r0 r2", "le_r12_r0_r2"}, 285 {{vc, r10, r10, r9}, false, al, "vc r10 r10 r9", "vc_r10_r10_r9"}, 286 {{ls, r11, r11, r8}, false, al, "ls r11 r11 r8", "ls_r11_r11_r8"}, 287 {{hi, r10, r11, r9}, false, al, "hi r10 r11 r9", "hi_r10_r11_r9"}, 288 {{vs, r7, r12, r14}, false, al, "vs r7 r12 r14", "vs_r7_r12_r14"}, 289 {{gt, r11, r14, r12}, false, al, "gt r11 r14 r12", "gt_r11_r14_r12"}, 290 {{vs, r0, r12, r8}, false, al, "vs r0 r12 r8", "vs_r0_r12_r8"}, 291 {{al, r0, r5, r7}, false, al, "al r0 r5 r7", "al_r0_r5_r7"}, 292 {{hi, r5, r13, r8}, false, al, "hi r5 r13 r8", "hi_r5_r13_r8"}, 293 {{le, r9, r9, r7}, false, al, "le r9 r9 r7", "le_r9_r9_r7"}, 294 {{cc, r4, r9, r5}, false, al, "cc r4 r9 r5", "cc_r4_r9_r5"}, 295 {{vs, r8, r1, r3}, false, al, "vs r8 r1 r3", "vs_r8_r1_r3"}, 296 {{cc, r0, r10, r12}, false, al, "cc r0 r10 r12", "cc_r0_r10_r12"}, 297 {{eq, r7, r14, r0}, false, al, "eq r7 r14 r0", "eq_r7_r14_r0"}, 298 {{vs, r12, r9, r11}, false, al, "vs r12 r9 r11", "vs_r12_r9_r11"}, 299 {{gt, r5, r9, r11}, false, al, "gt r5 r9 r11", "gt_r5_r9_r11"}, 300 {{cs, r14, r13, r7}, false, al, "cs r14 r13 r7", "cs_r14_r13_r7"}, 301 {{mi, r11, r3, r10}, false, al, "mi r11 r3 r10", "mi_r11_r3_r10"}, 302 {{hi, r11, r8, r12}, false, al, "hi r11 r8 r12", "hi_r11_r8_r12"}, 303 {{cs, r3, r8, r13}, false, al, "cs r3 r8 r13", "cs_r3_r8_r13"}, 304 {{pl, r10, r12, r6}, false, al, "pl r10 r12 r6", "pl_r10_r12_r6"}, 305 {{vc, r7, r3, r2}, false, al, "vc r7 r3 r2", "vc_r7_r3_r2"}, 306 {{mi, r9, r0, r8}, false, al, "mi r9 r0 r8", "mi_r9_r0_r8"}, 307 {{eq, r2, r13, r7}, false, al, "eq r2 r13 r7", "eq_r2_r13_r7"}, 308 {{ne, r2, r14, r0}, false, al, "ne r2 r14 r0", "ne_r2_r14_r0"}, 309 {{vs, r4, r10, r0}, false, al, "vs r4 r10 r0", "vs_r4_r10_r0"}, 310 {{ls, r0, r2, r2}, false, al, "ls r0 r2 r2", "ls_r0_r2_r2"}, 311 {{cc, r1, r6, r0}, false, al, "cc r1 r6 r0", "cc_r1_r6_r0"}, 312 {{lt, r12, r0, r8}, false, al, "lt r12 r0 r8", "lt_r12_r0_r8"}, 313 {{cc, r9, r3, r14}, false, al, "cc r9 r3 r14", "cc_r9_r3_r14"}, 314 {{vs, r7, r9, r1}, false, al, "vs r7 r9 r1", "vs_r7_r9_r1"}, 315 {{eq, r11, r9, r14}, false, al, "eq r11 r9 r14", "eq_r11_r9_r14"}, 316 {{pl, r6, r10, r4}, false, al, "pl r6 r10 r4", "pl_r6_r10_r4"}, 317 {{ne, r8, r5, r6}, false, al, "ne r8 r5 r6", "ne_r8_r5_r6"}, 318 {{cs, r0, r6, r2}, false, al, "cs r0 r6 r2", "cs_r0_r6_r2"}, 319 {{eq, r11, r12, r4}, false, al, "eq r11 r12 r4", "eq_r11_r12_r4"}, 320 {{lt, r14, r3, r14}, false, al, "lt r14 r3 r14", "lt_r14_r3_r14"}, 321 {{le, r7, r12, r14}, false, al, "le r7 r12 r14", "le_r7_r12_r14"}, 322 {{hi, r2, r9, r9}, false, al, "hi r2 r9 r9", "hi_r2_r9_r9"}, 323 {{ne, r8, r1, r0}, false, al, "ne r8 r1 r0", "ne_r8_r1_r0"}, 324 {{cc, r5, r11, r2}, false, al, "cc r5 r11 r2", "cc_r5_r11_r2"}, 325 {{hi, r0, r1, r2}, false, al, "hi r0 r1 r2", "hi_r0_r1_r2"}, 326 {{al, r4, r9, r4}, false, al, "al r4 r9 r4", "al_r4_r9_r4"}, 327 {{cs, r12, r7, r14}, false, al, "cs r12 r7 r14", "cs_r12_r7_r14"}, 328 {{cc, r4, r12, r10}, false, al, "cc r4 r12 r10", "cc_r4_r12_r10"}, 329 {{al, r3, r5, r10}, false, al, "al r3 r5 r10", "al_r3_r5_r10"}, 330 {{mi, r5, r3, r7}, false, al, "mi r5 r3 r7", "mi_r5_r3_r7"}, 331 {{ls, r10, r6, r2}, false, al, "ls r10 r6 r2", "ls_r10_r6_r2"}, 332 {{mi, r0, r12, r11}, false, al, "mi r0 r12 r11", "mi_r0_r12_r11"}, 333 {{vc, r12, r5, r6}, false, al, "vc r12 r5 r6", "vc_r12_r5_r6"}, 334 {{cs, r3, r9, r4}, false, al, "cs r3 r9 r4", "cs_r3_r9_r4"}, 335 {{ls, r4, r9, r11}, false, al, "ls r4 r9 r11", "ls_r4_r9_r11"}, 336 {{le, r14, r8, r13}, false, al, "le r14 r8 r13", "le_r14_r8_r13"}, 337 {{gt, r4, r10, r8}, false, al, "gt r4 r10 r8", "gt_r4_r10_r8"}, 338 {{al, r6, r9, r9}, false, al, "al r6 r9 r9", "al_r6_r9_r9"}, 339 {{ne, r8, r5, r12}, false, al, "ne r8 r5 r12", "ne_r8_r5_r12"}, 340 {{ne, r0, r4, r8}, false, al, "ne r0 r4 r8", "ne_r0_r4_r8"}, 341 {{mi, r7, r13, r3}, false, al, "mi r7 r13 r3", "mi_r7_r13_r3"}, 342 {{cc, r11, r7, r0}, false, al, "cc r11 r7 r0", "cc_r11_r7_r0"}, 343 {{hi, r1, r0, r12}, false, al, "hi r1 r0 r12", "hi_r1_r0_r12"}, 344 {{lt, r8, r9, r3}, false, al, "lt r8 r9 r3", "lt_r8_r9_r3"}, 345 {{al, r0, r2, r1}, false, al, "al r0 r2 r1", "al_r0_r2_r1"}, 346 {{vs, r4, r3, r14}, false, al, "vs r4 r3 r14", "vs_r4_r3_r14"}, 347 {{ge, r2, r11, r1}, false, al, "ge r2 r11 r1", "ge_r2_r11_r1"}, 348 {{lt, r12, r9, r6}, false, al, "lt r12 r9 r6", "lt_r12_r9_r6"}, 349 {{ls, r8, r2, r7}, false, al, "ls r8 r2 r7", "ls_r8_r2_r7"}, 350 {{le, r8, r13, r3}, false, al, "le r8 r13 r3", "le_r8_r13_r3"}, 351 {{eq, r11, r13, r14}, false, al, "eq r11 r13 r14", "eq_r11_r13_r14"}, 352 {{lt, r1, r6, r13}, false, al, "lt r1 r6 r13", "lt_r1_r6_r13"}, 353 {{cs, r3, r8, r11}, false, al, "cs r3 r8 r11", "cs_r3_r8_r11"}, 354 {{pl, r12, r5, r4}, false, al, "pl r12 r5 r4", "pl_r12_r5_r4"}, 355 {{eq, r8, r7, r2}, false, al, "eq r8 r7 r2", "eq_r8_r7_r2"}, 356 {{ls, r2, r12, r2}, false, al, "ls r2 r12 r2", "ls_r2_r12_r2"}, 357 {{le, r14, r2, r3}, false, al, "le r14 r2 r3", "le_r14_r2_r3"}, 358 {{ge, r10, r11, r6}, false, al, "ge r10 r11 r6", "ge_r10_r11_r6"}, 359 {{hi, r0, r2, r2}, false, al, "hi r0 r2 r2", "hi_r0_r2_r2"}, 360 {{ge, r2, r0, r2}, false, al, "ge r2 r0 r2", "ge_r2_r0_r2"}, 361 {{vs, r11, r14, r0}, false, al, "vs r11 r14 r0", "vs_r11_r14_r0"}, 362 {{lt, r2, r0, r1}, false, al, "lt r2 r0 r1", "lt_r2_r0_r1"}, 363 {{cs, r2, r5, r11}, false, al, "cs r2 r5 r11", "cs_r2_r5_r11"}, 364 {{ls, r7, r14, r5}, false, al, "ls r7 r14 r5", "ls_r7_r14_r5"}, 365 {{pl, r0, r0, r3}, false, al, "pl r0 r0 r3", "pl_r0_r0_r3"}, 366 {{ge, r6, r8, r8}, false, al, "ge r6 r8 r8", "ge_r6_r8_r8"}, 367 {{le, r11, r1, r10}, false, al, "le r11 r1 r10", "le_r11_r1_r10"}, 368 {{vs, r5, r2, r7}, false, al, "vs r5 r2 r7", "vs_r5_r2_r7"}, 369 {{ne, r4, r4, r8}, false, al, "ne r4 r4 r8", "ne_r4_r4_r8"}, 370 {{cc, r9, r14, r13}, false, al, "cc r9 r14 r13", "cc_r9_r14_r13"}, 371 {{hi, r14, r6, r3}, false, al, "hi r14 r6 r3", "hi_r14_r6_r3"}, 372 {{al, r0, r8, r0}, false, al, "al r0 r8 r0", "al_r0_r8_r0"}, 373 {{lt, r6, r11, r1}, false, al, "lt r6 r11 r1", "lt_r6_r11_r1"}, 374 {{ge, r7, r6, r12}, false, al, "ge r7 r6 r12", "ge_r7_r6_r12"}, 375 {{cs, r4, r6, r14}, false, al, "cs r4 r6 r14", "cs_r4_r6_r14"}, 376 {{cs, r7, r6, r7}, false, al, "cs r7 r6 r7", "cs_r7_r6_r7"}, 377 {{cs, r3, r7, r10}, false, al, "cs r3 r7 r10", "cs_r3_r7_r10"}, 378 {{ne, r0, r2, r1}, false, al, "ne r0 r2 r1", "ne_r0_r2_r1"}, 379 {{vs, r9, r10, r13}, false, al, "vs r9 r10 r13", "vs_r9_r10_r13"}, 380 {{vc, r11, r14, r12}, false, al, "vc r11 r14 r12", "vc_r11_r14_r12"}, 381 {{ge, r14, r8, r7}, false, al, "ge r14 r8 r7", "ge_r14_r8_r7"}, 382 {{lt, r13, r0, r11}, false, al, "lt r13 r0 r11", "lt_r13_r0_r11"}, 383 {{lt, r14, r13, r4}, false, al, "lt r14 r13 r4", "lt_r14_r13_r4"}, 384 {{al, r1, r10, r9}, false, al, "al r1 r10 r9", "al_r1_r10_r9"}, 385 {{ge, r11, r14, r11}, false, al, "ge r11 r14 r11", "ge_r11_r14_r11"}, 386 {{cs, r11, r4, r11}, false, al, "cs r11 r4 r11", "cs_r11_r4_r11"}, 387 {{ge, r0, r14, r7}, false, al, "ge r0 r14 r7", "ge_r0_r14_r7"}, 388 {{mi, r1, r2, r9}, false, al, "mi r1 r2 r9", "mi_r1_r2_r9"}, 389 {{eq, r5, r12, r3}, false, al, "eq r5 r12 r3", "eq_r5_r12_r3"}, 390 {{ge, r1, r5, r12}, false, al, "ge r1 r5 r12", "ge_r1_r5_r12"}, 391 {{lt, r10, r11, r4}, false, al, "lt r10 r11 r4", "lt_r10_r11_r4"}, 392 {{le, r1, r1, r5}, false, al, "le r1 r1 r5", "le_r1_r1_r5"}, 393 {{al, r9, r1, r8}, false, al, "al r9 r1 r8", "al_r9_r1_r8"}, 394 {{ne, r6, r8, r4}, false, al, "ne r6 r8 r4", "ne_r6_r8_r4"}, 395 {{ge, r12, r2, r9}, false, al, "ge r12 r2 r9", "ge_r12_r2_r9"}, 396 {{pl, r4, r3, r10}, false, al, "pl r4 r3 r10", "pl_r4_r3_r10"}, 397 {{eq, r14, r4, r11}, false, al, "eq r14 r4 r11", "eq_r14_r4_r11"}, 398 {{cc, r9, r7, r6}, false, al, "cc r9 r7 r6", "cc_r9_r7_r6"}, 399 {{ge, r12, r4, r5}, false, al, "ge r12 r4 r5", "ge_r12_r4_r5"}, 400 {{hi, r2, r3, r4}, false, al, "hi r2 r3 r4", "hi_r2_r3_r4"}, 401 {{cs, r0, r3, r1}, false, al, "cs r0 r3 r1", "cs_r0_r3_r1"}, 402 {{hi, r6, r2, r8}, false, al, "hi r6 r2 r8", "hi_r6_r2_r8"}, 403 {{cc, r3, r14, r13}, false, al, "cc r3 r14 r13", "cc_r3_r14_r13"}, 404 {{gt, r11, r4, r7}, false, al, "gt r11 r4 r7", "gt_r11_r4_r7"}, 405 {{hi, r5, r0, r12}, false, al, "hi r5 r0 r12", "hi_r5_r0_r12"}, 406 {{gt, r0, r14, r14}, false, al, "gt r0 r14 r14", "gt_r0_r14_r14"}, 407 {{hi, r9, r0, r10}, false, al, "hi r9 r0 r10", "hi_r9_r0_r10"}, 408 {{vc, r7, r11, r8}, false, al, "vc r7 r11 r8", "vc_r7_r11_r8"}, 409 {{pl, r11, r9, r6}, false, al, "pl r11 r9 r6", "pl_r11_r9_r6"}, 410 {{al, r3, r3, r7}, false, al, "al r3 r3 r7", "al_r3_r3_r7"}, 411 {{mi, r5, r7, r9}, false, al, "mi r5 r7 r9", "mi_r5_r7_r9"}, 412 {{cc, r11, r2, r4}, false, al, "cc r11 r2 r4", "cc_r11_r2_r4"}, 413 {{cc, r9, r13, r10}, false, al, "cc r9 r13 r10", "cc_r9_r13_r10"}, 414 {{al, r5, r2, r6}, false, al, "al r5 r2 r6", "al_r5_r2_r6"}, 415 {{ge, r9, r4, r6}, false, al, "ge r9 r4 r6", "ge_r9_r4_r6"}, 416 {{ls, r3, r3, r4}, false, al, "ls r3 r3 r4", "ls_r3_r3_r4"}, 417 {{ge, r14, r1, r8}, false, al, "ge r14 r1 r8", "ge_r14_r1_r8"}, 418 {{ls, r7, r12, r7}, false, al, "ls r7 r12 r7", "ls_r7_r12_r7"}, 419 {{al, r11, r10, r5}, false, al, "al r11 r10 r5", "al_r11_r10_r5"}, 420 {{al, r7, r4, r6}, false, al, "al r7 r4 r6", "al_r7_r4_r6"}, 421 {{vs, r12, r4, r10}, false, al, "vs r12 r4 r10", "vs_r12_r4_r10"}, 422 {{eq, r4, r4, r4}, false, al, "eq r4 r4 r4", "eq_r4_r4_r4"}, 423 {{vs, r6, r6, r12}, false, al, "vs r6 r6 r12", "vs_r6_r6_r12"}, 424 {{pl, r9, r3, r5}, false, al, "pl r9 r3 r5", "pl_r9_r3_r5"}, 425 {{eq, r6, r5, r13}, false, al, "eq r6 r5 r13", "eq_r6_r5_r13"}, 426 {{cc, r8, r2, r12}, false, al, "cc r8 r2 r12", "cc_r8_r2_r12"}, 427 {{le, r4, r2, r0}, false, al, "le r4 r2 r0", "le_r4_r2_r0"}, 428 {{lt, r7, r9, r8}, false, al, "lt r7 r9 r8", "lt_r7_r9_r8"}, 429 {{le, r4, r7, r11}, false, al, "le r4 r7 r11", "le_r4_r7_r11"}, 430 {{eq, r5, r7, r5}, false, al, "eq r5 r7 r5", "eq_r5_r7_r5"}, 431 {{vc, r10, r7, r12}, false, al, "vc r10 r7 r12", "vc_r10_r7_r12"}, 432 {{eq, r7, r10, r6}, false, al, "eq r7 r10 r6", "eq_r7_r10_r6"}, 433 {{pl, r1, r12, r2}, false, al, "pl r1 r12 r2", "pl_r1_r12_r2"}, 434 {{le, r14, r6, r6}, false, al, "le r14 r6 r6", "le_r14_r6_r6"}, 435 {{ne, r3, r8, r8}, false, al, "ne r3 r8 r8", "ne_r3_r8_r8"}, 436 {{eq, r4, r12, r8}, false, al, "eq r4 r12 r8", "eq_r4_r12_r8"}, 437 {{ge, r11, r2, r3}, false, al, "ge r11 r2 r3", "ge_r11_r2_r3"}, 438 {{hi, r12, r6, r11}, false, al, "hi r12 r6 r11", "hi_r12_r6_r11"}, 439 {{cs, r4, r5, r10}, false, al, "cs r4 r5 r10", "cs_r4_r5_r10"}, 440 {{ge, r10, r2, r10}, false, al, "ge r10 r2 r10", "ge_r10_r2_r10"}, 441 {{ge, r5, r14, r6}, false, al, "ge r5 r14 r6", "ge_r5_r14_r6"}, 442 {{gt, r13, r7, r5}, false, al, "gt r13 r7 r5", "gt_r13_r7_r5"}, 443 {{ge, r13, r4, r12}, false, al, "ge r13 r4 r12", "ge_r13_r4_r12"}, 444 {{lt, r8, r10, r14}, false, al, "lt r8 r10 r14", "lt_r8_r10_r14"}, 445 {{le, r4, r3, r13}, false, al, "le r4 r3 r13", "le_r4_r3_r13"}, 446 {{pl, r0, r9, r0}, false, al, "pl r0 r9 r0", "pl_r0_r9_r0"}, 447 {{eq, r2, r3, r1}, false, al, "eq r2 r3 r1", "eq_r2_r3_r1"}, 448 {{vc, r0, r0, r3}, false, al, "vc r0 r0 r3", "vc_r0_r0_r3"}, 449 {{mi, r10, r8, r11}, false, al, "mi r10 r8 r11", "mi_r10_r8_r11"}, 450 {{mi, r5, r14, r14}, false, al, "mi r5 r14 r14", "mi_r5_r14_r14"}, 451 {{gt, r5, r11, r2}, false, al, "gt r5 r11 r2", "gt_r5_r11_r2"}, 452 {{al, r4, r7, r11}, false, al, "al r4 r7 r11", "al_r4_r7_r11"}}; 453 454 // These headers each contain an array of `TestResult` with the reference output 455 // values. The reference arrays are names `kReference{mnemonic}`. 456 #include "aarch32/traces/assembler-cond-rd-rn-rm-mul-a32.h" 457 #include "aarch32/traces/assembler-cond-rd-rn-rm-muls-a32.h" 458 #include "aarch32/traces/assembler-cond-rd-rn-rm-qadd-a32.h" 459 #include "aarch32/traces/assembler-cond-rd-rn-rm-qadd16-a32.h" 460 #include "aarch32/traces/assembler-cond-rd-rn-rm-qadd8-a32.h" 461 #include "aarch32/traces/assembler-cond-rd-rn-rm-qasx-a32.h" 462 #include "aarch32/traces/assembler-cond-rd-rn-rm-qdadd-a32.h" 463 #include "aarch32/traces/assembler-cond-rd-rn-rm-qdsub-a32.h" 464 #include "aarch32/traces/assembler-cond-rd-rn-rm-qsax-a32.h" 465 #include "aarch32/traces/assembler-cond-rd-rn-rm-qsub-a32.h" 466 #include "aarch32/traces/assembler-cond-rd-rn-rm-qsub16-a32.h" 467 #include "aarch32/traces/assembler-cond-rd-rn-rm-qsub8-a32.h" 468 #include "aarch32/traces/assembler-cond-rd-rn-rm-sadd16-a32.h" 469 #include "aarch32/traces/assembler-cond-rd-rn-rm-sadd8-a32.h" 470 #include "aarch32/traces/assembler-cond-rd-rn-rm-sasx-a32.h" 471 #include "aarch32/traces/assembler-cond-rd-rn-rm-sdiv-a32.h" 472 #include "aarch32/traces/assembler-cond-rd-rn-rm-sel-a32.h" 473 #include "aarch32/traces/assembler-cond-rd-rn-rm-shadd16-a32.h" 474 #include "aarch32/traces/assembler-cond-rd-rn-rm-shadd8-a32.h" 475 #include "aarch32/traces/assembler-cond-rd-rn-rm-shasx-a32.h" 476 #include "aarch32/traces/assembler-cond-rd-rn-rm-shsax-a32.h" 477 #include "aarch32/traces/assembler-cond-rd-rn-rm-shsub16-a32.h" 478 #include "aarch32/traces/assembler-cond-rd-rn-rm-shsub8-a32.h" 479 #include "aarch32/traces/assembler-cond-rd-rn-rm-smmul-a32.h" 480 #include "aarch32/traces/assembler-cond-rd-rn-rm-smmulr-a32.h" 481 #include "aarch32/traces/assembler-cond-rd-rn-rm-smuad-a32.h" 482 #include "aarch32/traces/assembler-cond-rd-rn-rm-smuadx-a32.h" 483 #include "aarch32/traces/assembler-cond-rd-rn-rm-smulbb-a32.h" 484 #include "aarch32/traces/assembler-cond-rd-rn-rm-smulbt-a32.h" 485 #include "aarch32/traces/assembler-cond-rd-rn-rm-smultb-a32.h" 486 #include "aarch32/traces/assembler-cond-rd-rn-rm-smultt-a32.h" 487 #include "aarch32/traces/assembler-cond-rd-rn-rm-smulwb-a32.h" 488 #include "aarch32/traces/assembler-cond-rd-rn-rm-smulwt-a32.h" 489 #include "aarch32/traces/assembler-cond-rd-rn-rm-smusd-a32.h" 490 #include "aarch32/traces/assembler-cond-rd-rn-rm-smusdx-a32.h" 491 #include "aarch32/traces/assembler-cond-rd-rn-rm-ssax-a32.h" 492 #include "aarch32/traces/assembler-cond-rd-rn-rm-ssub16-a32.h" 493 #include "aarch32/traces/assembler-cond-rd-rn-rm-ssub8-a32.h" 494 #include "aarch32/traces/assembler-cond-rd-rn-rm-uadd16-a32.h" 495 #include "aarch32/traces/assembler-cond-rd-rn-rm-uadd8-a32.h" 496 #include "aarch32/traces/assembler-cond-rd-rn-rm-uasx-a32.h" 497 #include "aarch32/traces/assembler-cond-rd-rn-rm-udiv-a32.h" 498 #include "aarch32/traces/assembler-cond-rd-rn-rm-uhadd16-a32.h" 499 #include "aarch32/traces/assembler-cond-rd-rn-rm-uhadd8-a32.h" 500 #include "aarch32/traces/assembler-cond-rd-rn-rm-uhasx-a32.h" 501 #include "aarch32/traces/assembler-cond-rd-rn-rm-uhsax-a32.h" 502 #include "aarch32/traces/assembler-cond-rd-rn-rm-uhsub16-a32.h" 503 #include "aarch32/traces/assembler-cond-rd-rn-rm-uhsub8-a32.h" 504 #include "aarch32/traces/assembler-cond-rd-rn-rm-uqadd16-a32.h" 505 #include "aarch32/traces/assembler-cond-rd-rn-rm-uqadd8-a32.h" 506 #include "aarch32/traces/assembler-cond-rd-rn-rm-uqasx-a32.h" 507 #include "aarch32/traces/assembler-cond-rd-rn-rm-uqsax-a32.h" 508 #include "aarch32/traces/assembler-cond-rd-rn-rm-uqsub16-a32.h" 509 #include "aarch32/traces/assembler-cond-rd-rn-rm-uqsub8-a32.h" 510 #include "aarch32/traces/assembler-cond-rd-rn-rm-usad8-a32.h" 511 #include "aarch32/traces/assembler-cond-rd-rn-rm-usax-a32.h" 512 #include "aarch32/traces/assembler-cond-rd-rn-rm-usub16-a32.h" 513 #include "aarch32/traces/assembler-cond-rd-rn-rm-usub8-a32.h" 514 515 516 // The maximum number of errors to report in detail for each test. 517 const unsigned kErrorReportLimit = 8; 518 519 typedef void (MacroAssembler::*Fn)(Condition cond, 520 Register rd, 521 Register rn, 522 Register rm); 523 524 void TestHelper(Fn instruction, 525 const char* mnemonic, 526 const TestResult reference[]) { 527 unsigned total_error_count = 0; 528 MacroAssembler masm(BUF_SIZE); 529 530 masm.UseA32(); 531 532 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 533 // Values to pass to the macro-assembler. 534 Condition cond = kTests[i].operands.cond; 535 Register rd = kTests[i].operands.rd; 536 Register rn = kTests[i].operands.rn; 537 Register rm = kTests[i].operands.rm; 538 539 int32_t start = masm.GetCursorOffset(); 540 { 541 // We never generate more that 4 bytes, as IT instructions are only 542 // allowed for narrow encodings. 543 ExactAssemblyScope scope(&masm, 4, ExactAssemblyScope::kMaximumSize); 544 if (kTests[i].in_it_block) { 545 masm.it(kTests[i].it_condition); 546 } 547 (masm.*instruction)(cond, rd, rn, rm); 548 } 549 int32_t end = masm.GetCursorOffset(); 550 551 const byte* result_ptr = 552 masm.GetBuffer()->GetOffsetAddress<const byte*>(start); 553 VIXL_ASSERT(start < end); 554 uint32_t result_size = end - start; 555 556 if (Test::generate_test_trace()) { 557 // Print the result bytes. 558 printf("const byte kInstruction_%s_%s[] = {\n", 559 mnemonic, 560 kTests[i].identifier); 561 for (uint32_t j = 0; j < result_size; j++) { 562 if (j == 0) { 563 printf(" 0x%02" PRIx8, result_ptr[j]); 564 } else { 565 printf(", 0x%02" PRIx8, result_ptr[j]); 566 } 567 } 568 // This comment is meant to be used by external tools to validate 569 // the encoding. We can parse the comment to figure out what 570 // instruction this corresponds to. 571 if (kTests[i].in_it_block) { 572 printf(" // It %s; %s %s\n};\n", 573 kTests[i].it_condition.GetName(), 574 mnemonic, 575 kTests[i].operands_description); 576 } else { 577 printf(" // %s %s\n};\n", mnemonic, kTests[i].operands_description); 578 } 579 } else { 580 // Check we've emitted the exact same encoding as present in the 581 // trace file. Only print up to `kErrorReportLimit` errors. 582 if (((result_size != reference[i].size) || 583 (memcmp(result_ptr, reference[i].encoding, reference[i].size) != 584 0)) && 585 (++total_error_count <= kErrorReportLimit)) { 586 printf("Error when testing \"%s\" with operands \"%s\":\n", 587 mnemonic, 588 kTests[i].operands_description); 589 printf(" Expected: "); 590 for (uint32_t j = 0; j < reference[i].size; j++) { 591 if (j == 0) { 592 printf("0x%02" PRIx8, reference[i].encoding[j]); 593 } else { 594 printf(", 0x%02" PRIx8, reference[i].encoding[j]); 595 } 596 } 597 printf("\n"); 598 printf(" Found: "); 599 for (uint32_t j = 0; j < result_size; j++) { 600 if (j == 0) { 601 printf("0x%02" PRIx8, result_ptr[j]); 602 } else { 603 printf(", 0x%02" PRIx8, result_ptr[j]); 604 } 605 } 606 printf("\n"); 607 } 608 } 609 } 610 611 masm.FinalizeCode(); 612 613 if (Test::generate_test_trace()) { 614 // Finalize the trace file by writing the final `TestResult` array 615 // which links all generated instruction encodings. 616 printf("const TestResult kReference%s[] = {\n", mnemonic); 617 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 618 printf(" {\n"); 619 printf(" ARRAY_SIZE(kInstruction_%s_%s),\n", 620 mnemonic, 621 kTests[i].identifier); 622 printf(" kInstruction_%s_%s,\n", mnemonic, kTests[i].identifier); 623 printf(" },\n"); 624 } 625 printf("};\n"); 626 } else { 627 if (total_error_count > kErrorReportLimit) { 628 printf("%u other errors follow.\n", 629 total_error_count - kErrorReportLimit); 630 } 631 // Crash if the test failed. 632 VIXL_CHECK(total_error_count == 0); 633 } 634 } 635 636 // Instantiate tests for each instruction in the list. 637 #define TEST(mnemonic) \ 638 void Test_##mnemonic() { \ 639 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 640 } \ 641 Test test_##mnemonic("AARCH32_ASSEMBLER_COND_RD_RN_RM_" #mnemonic "_A32", \ 642 &Test_##mnemonic); 643 FOREACH_INSTRUCTION(TEST) 644 #undef TEST 645 646 } // namespace 647 #endif 648 649 } // namespace aarch32 650 } // namespace vixl 651
