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     11 
     12 <h1>binop</h1>
     13 
     14 <h2>Purpose</h2>
     15 
     16 <p>
     17 Perform the identified binary operation on the two source registers, storing
     18 the result in the first source register.
     19 </p>
     20 
     21 <h2>Details</h2>
     22 
     23 <table class="instruc">
     24 <thead>
     25 <tr>
     26   <th>Op &amp; Format</th>
     27   <th>Mnemonic / Syntax</th>
     28   <th>Arguments</th>
     29 </tr>
     30 </thead>
     31 <tbody>
     32 <tr>
     33   <td>90..af 23x</td>
     34   <td><i>binop</i> vAA, vBB, vCC<br/>
     35     90: add-int<br/>
     36     91: sub-int<br/>
     37     92: mul-int<br/>
     38     93: div-int<br/>
     39     94: rem-int<br/>
     40     95: and-int<br/>
     41     96: or-int<br/>
     42     97: xor-int<br/>
     43     98: shl-int<br/>
     44     99: shr-int<br/>
     45     9a: ushr-int<br/>
     46     9b: add-long<br/>
     47     9c: sub-long<br/>
     48     9d: mul-long<br/>
     49     9e: div-long<br/>
     50     9f: rem-long<br/>
     51     a0: and-long<br/>
     52     a1: or-long<br/>
     53     a2: xor-long<br/>
     54     a3: shl-long<br/>
     55     a4: shr-long<br/>
     56     a5: ushr-long<br/>
     57     a6: add-float<br/>
     58     a7: sub-float<br/>
     59     a8: mul-float<br/>
     60     a9: div-float<br/>
     61     aa: rem-float<br/>
     62     ab: add-double<br/>
     63     ac: sub-double<br/>
     64     ad: mul-double<br/>
     65     ae: div-double<br/>
     66     af: rem-double
     67   </td>
     68   <td><code>A:</code> destination register or pair (8 bits)<br/>
     69     <code>B:</code> first source register or pair (8 bits)<br/>
     70     <code>C:</code> second source register or pair (8 bits)</td>
     71 </tr>
     72 </tbody>
     73 </table>
     74 
     75 <h2>Constraints</h2>
     76 
     77 <ul>
     78   <li>
     79     All A, B and C must be valid register indices in the current stackframe.
     80   </li>
     81   <li>
     82     For the -long and -double variants, also A+1, B+1 and C+1 must be valid
     83     register indices.
     84   </li>
     85   <li>
     86     Registers vB and vC must be defined. They must both contain values that
     87     match the variant of the instruction (it's probably better to split this up
     88     into multiple pages again).
     89   </li>
     90 </ul>
     91 
     92 <h2>Behavior</h2>
     93 
     94 <ul>
     95   <li>
     96     The given operation &lt;binop&gt; is performed according to the semantics
     97     specified in table XXX.
     98   </li>
     99   <li>
    100     The result is stored in register vA, that is, vA'=&lt;biop&gt; vB.
    101   </li>
    102   <li>
    103     For the -double and -long variants, (vA+1) is also affected.
    104   </li>
    105   <li>
    106     As usual, neighboring registers might get undefined, if vA (and vA+1) were
    107     part of a register pair originally.
    108   </li>
    109 </ul>
    110 
    111 <h2>Exceptions</h2>
    112 
    113 <ul>
    114   <li>
    115     ArithmeticException if an error occurs during the instruction.
    116   </li>
    117 </ul>
    118 
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