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      1 //===------------------------ CalcSpillWeights.cpp ------------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #define DEBUG_TYPE "calcspillweights"
     11 
     12 #include "llvm/Function.h"
     13 #include "llvm/ADT/SmallSet.h"
     14 #include "llvm/CodeGen/CalcSpillWeights.h"
     15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
     16 #include "llvm/CodeGen/MachineFunction.h"
     17 #include "llvm/CodeGen/MachineLoopInfo.h"
     18 #include "llvm/CodeGen/MachineRegisterInfo.h"
     19 #include "llvm/CodeGen/SlotIndexes.h"
     20 #include "llvm/Support/Debug.h"
     21 #include "llvm/Support/raw_ostream.h"
     22 #include "llvm/Target/TargetInstrInfo.h"
     23 #include "llvm/Target/TargetMachine.h"
     24 #include "llvm/Target/TargetRegisterInfo.h"
     25 using namespace llvm;
     26 
     27 char CalculateSpillWeights::ID = 0;
     28 INITIALIZE_PASS_BEGIN(CalculateSpillWeights, "calcspillweights",
     29                 "Calculate spill weights", false, false)
     30 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
     31 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
     32 INITIALIZE_PASS_END(CalculateSpillWeights, "calcspillweights",
     33                 "Calculate spill weights", false, false)
     34 
     35 void CalculateSpillWeights::getAnalysisUsage(AnalysisUsage &au) const {
     36   au.addRequired<LiveIntervals>();
     37   au.addRequired<MachineLoopInfo>();
     38   au.setPreservesAll();
     39   MachineFunctionPass::getAnalysisUsage(au);
     40 }
     41 
     42 bool CalculateSpillWeights::runOnMachineFunction(MachineFunction &fn) {
     43 
     44   DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
     45                << "********** Function: "
     46                << fn.getFunction()->getName() << '\n');
     47 
     48   LiveIntervals &lis = getAnalysis<LiveIntervals>();
     49   VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
     50   for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
     51     LiveInterval &li = *I->second;
     52     if (TargetRegisterInfo::isVirtualRegister(li.reg))
     53       vrai.CalculateWeightAndHint(li);
     54   }
     55   return false;
     56 }
     57 
     58 // Return the preferred allocation register for reg, given a COPY instruction.
     59 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
     60                          const TargetRegisterInfo &tri,
     61                          const MachineRegisterInfo &mri) {
     62   unsigned sub, hreg, hsub;
     63   if (mi->getOperand(0).getReg() == reg) {
     64     sub = mi->getOperand(0).getSubReg();
     65     hreg = mi->getOperand(1).getReg();
     66     hsub = mi->getOperand(1).getSubReg();
     67   } else {
     68     sub = mi->getOperand(1).getSubReg();
     69     hreg = mi->getOperand(0).getReg();
     70     hsub = mi->getOperand(0).getSubReg();
     71   }
     72 
     73   if (!hreg)
     74     return 0;
     75 
     76   if (TargetRegisterInfo::isVirtualRegister(hreg))
     77     return sub == hsub ? hreg : 0;
     78 
     79   const TargetRegisterClass *rc = mri.getRegClass(reg);
     80 
     81   // Only allow physreg hints in rc.
     82   if (sub == 0)
     83     return rc->contains(hreg) ? hreg : 0;
     84 
     85   // reg:sub should match the physreg hreg.
     86   return tri.getMatchingSuperReg(hreg, sub, rc);
     87 }
     88 
     89 void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
     90   MachineRegisterInfo &mri = MF.getRegInfo();
     91   const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo();
     92   MachineBasicBlock *mbb = 0;
     93   MachineLoop *loop = 0;
     94   unsigned loopDepth = 0;
     95   bool isExiting = false;
     96   float totalWeight = 0;
     97   SmallPtrSet<MachineInstr*, 8> visited;
     98 
     99   // Find the best physreg hist and the best virtreg hint.
    100   float bestPhys = 0, bestVirt = 0;
    101   unsigned hintPhys = 0, hintVirt = 0;
    102 
    103   // Don't recompute a target specific hint.
    104   bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
    105 
    106   // Don't recompute spill weight for an unspillable register.
    107   bool Spillable = li.isSpillable();
    108 
    109   for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
    110        MachineInstr *mi = I.skipInstruction();) {
    111     if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
    112       continue;
    113     if (!visited.insert(mi))
    114       continue;
    115 
    116     float weight = 1.0f;
    117     if (Spillable) {
    118       // Get loop info for mi.
    119       if (mi->getParent() != mbb) {
    120         mbb = mi->getParent();
    121         loop = Loops.getLoopFor(mbb);
    122         loopDepth = loop ? loop->getLoopDepth() : 0;
    123         isExiting = loop ? loop->isLoopExiting(mbb) : false;
    124       }
    125 
    126       // Calculate instr weight.
    127       bool reads, writes;
    128       tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
    129       weight = LiveIntervals::getSpillWeight(writes, reads, loopDepth);
    130 
    131       // Give extra weight to what looks like a loop induction variable update.
    132       if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
    133         weight *= 3;
    134 
    135       totalWeight += weight;
    136     }
    137 
    138     // Get allocation hints from copies.
    139     if (noHint || !mi->isCopy())
    140       continue;
    141     unsigned hint = copyHint(mi, li.reg, tri, mri);
    142     if (!hint)
    143       continue;
    144     float hweight = Hint[hint] += weight;
    145     if (TargetRegisterInfo::isPhysicalRegister(hint)) {
    146       if (hweight > bestPhys && LIS.isAllocatable(hint))
    147         bestPhys = hweight, hintPhys = hint;
    148     } else {
    149       if (hweight > bestVirt)
    150         bestVirt = hweight, hintVirt = hint;
    151     }
    152   }
    153 
    154   Hint.clear();
    155 
    156   // Always prefer the physreg hint.
    157   if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
    158     mri.setRegAllocationHint(li.reg, 0, hint);
    159     // Weakly boost the spill weight of hinted registers.
    160     totalWeight *= 1.01F;
    161   }
    162 
    163   // If the live interval was already unspillable, leave it that way.
    164   if (!Spillable)
    165     return;
    166 
    167   // Mark li as unspillable if all live ranges are tiny.
    168   if (li.isZeroLength(LIS.getSlotIndexes())) {
    169     li.markNotSpillable();
    170     return;
    171   }
    172 
    173   // If all of the definitions of the interval are re-materializable,
    174   // it is a preferred candidate for spilling. If none of the defs are
    175   // loads, then it's potentially very cheap to re-materialize.
    176   // FIXME: this gets much more complicated once we support non-trivial
    177   // re-materialization.
    178   bool isLoad = false;
    179   if (LIS.isReMaterializable(li, 0, isLoad)) {
    180     if (isLoad)
    181       totalWeight *= 0.9F;
    182     else
    183       totalWeight *= 0.5F;
    184   }
    185 
    186   li.weight = normalizeSpillWeight(totalWeight, li.getSize());
    187 }
    188 
    189 void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
    190   MachineRegisterInfo &MRI = MF.getRegInfo();
    191   const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
    192   const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
    193   const TargetRegisterClass *OldRC = MRI.getRegClass(reg);
    194   const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
    195 
    196   // Stop early if there is no room to grow.
    197   if (NewRC == OldRC)
    198     return;
    199 
    200   // Accumulate constraints from all uses.
    201   for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(reg),
    202        E = MRI.reg_nodbg_end(); I != E; ++I) {
    203     // TRI doesn't have accurate enough information to model this yet.
    204     if (I.getOperand().getSubReg())
    205       return;
    206     // Inline asm instuctions don't remember their constraints.
    207     if (I->isInlineAsm())
    208       return;
    209     const TargetRegisterClass *OpRC =
    210       TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
    211     if (OpRC)
    212       NewRC = getCommonSubClass(NewRC, OpRC);
    213     if (!NewRC || NewRC == OldRC)
    214       return;
    215   }
    216   DEBUG(dbgs() << "Inflating " << OldRC->getName() << ':' << PrintReg(reg)
    217                << " to " << NewRC->getName() <<".\n");
    218   MRI.setRegClass(reg, NewRC);
    219 }
    220