1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the MachineRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17 #include "llvm/Target/TargetRegisterInfo.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/IndexedMap.h" 20 #include <vector> 21 22 namespace llvm { 23 24 /// MachineRegisterInfo - Keep track of information for virtual and physical 25 /// registers, including vreg register classes, use/def chains for registers, 26 /// etc. 27 class MachineRegisterInfo { 28 /// VRegInfo - Information we keep for each virtual register. 29 /// 30 /// Each element in this list contains the register class of the vreg and the 31 /// start of the use/def list for the register. 32 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 33 VirtReg2IndexFunctor> VRegInfo; 34 35 /// RegAllocHints - This vector records register allocation hints for virtual 36 /// registers. For each virtual register, it keeps a register and hint type 37 /// pair making up the allocation hint. Hint type is target specific except 38 /// for the value 0 which means the second value of the pair is the preferred 39 /// register for allocation. For example, if the hint is <0, 1024>, it means 40 /// the allocator should prefer the physical register allocated to the virtual 41 /// register of the hint. 42 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 43 44 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 45 /// physical registers. 46 MachineOperand **PhysRegUseDefLists; 47 48 /// UsedPhysRegs - This is a bit vector that is computed and set by the 49 /// register allocator, and must be kept up to date by passes that run after 50 /// register allocation (though most don't modify this). This is used 51 /// so that the code generator knows which callee save registers to save and 52 /// for other target specific uses. 53 BitVector UsedPhysRegs; 54 55 /// LiveIns/LiveOuts - Keep track of the physical registers that are 56 /// livein/liveout of the function. Live in values are typically arguments in 57 /// registers, live out values are typically return values in registers. 58 /// LiveIn values are allowed to have virtual registers associated with them, 59 /// stored in the second element. 60 std::vector<std::pair<unsigned, unsigned> > LiveIns; 61 std::vector<unsigned> LiveOuts; 62 63 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 64 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 65 public: 66 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 67 ~MachineRegisterInfo(); 68 69 //===--------------------------------------------------------------------===// 70 // Register Info 71 //===--------------------------------------------------------------------===// 72 73 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 74 /// and uses of a register within the MachineFunction that corresponds to this 75 /// MachineRegisterInfo object. 76 template<bool Uses, bool Defs, bool SkipDebug> 77 class defusechain_iterator; 78 79 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 80 /// register. 81 typedef defusechain_iterator<true,true,false> reg_iterator; 82 reg_iterator reg_begin(unsigned RegNo) const { 83 return reg_iterator(getRegUseDefListHead(RegNo)); 84 } 85 static reg_iterator reg_end() { return reg_iterator(0); } 86 87 /// reg_empty - Return true if there are no instructions using or defining the 88 /// specified register (it may be live-in). 89 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 90 91 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 92 /// of the specified register, skipping those marked as Debug. 93 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 94 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 95 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 96 } 97 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 98 99 /// reg_nodbg_empty - Return true if the only instructions using or defining 100 /// Reg are Debug instructions. 101 bool reg_nodbg_empty(unsigned RegNo) const { 102 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 103 } 104 105 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 106 typedef defusechain_iterator<false,true,false> def_iterator; 107 def_iterator def_begin(unsigned RegNo) const { 108 return def_iterator(getRegUseDefListHead(RegNo)); 109 } 110 static def_iterator def_end() { return def_iterator(0); } 111 112 /// def_empty - Return true if there are no instructions defining the 113 /// specified register (it may be live-in). 114 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 115 116 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 117 typedef defusechain_iterator<true,false,false> use_iterator; 118 use_iterator use_begin(unsigned RegNo) const { 119 return use_iterator(getRegUseDefListHead(RegNo)); 120 } 121 static use_iterator use_end() { return use_iterator(0); } 122 123 /// use_empty - Return true if there are no instructions using the specified 124 /// register. 125 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 126 127 /// hasOneUse - Return true if there is exactly one instruction using the 128 /// specified register. 129 bool hasOneUse(unsigned RegNo) const; 130 131 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 132 /// specified register, skipping those marked as Debug. 133 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 134 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 135 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 136 } 137 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 138 139 /// use_nodbg_empty - Return true if there are no non-Debug instructions 140 /// using the specified register. 141 bool use_nodbg_empty(unsigned RegNo) const { 142 return use_nodbg_begin(RegNo) == use_nodbg_end(); 143 } 144 145 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 146 /// instruction using the specified register. 147 bool hasOneNonDBGUse(unsigned RegNo) const; 148 149 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 150 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 151 /// except that it also changes any definitions of the register as well. 152 void replaceRegWith(unsigned FromReg, unsigned ToReg); 153 154 /// getRegUseDefListHead - Return the head pointer for the register use/def 155 /// list for the specified virtual or physical register. 156 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 157 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 158 return VRegInfo[RegNo].second; 159 return PhysRegUseDefLists[RegNo]; 160 } 161 162 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 163 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 164 return VRegInfo[RegNo].second; 165 return PhysRegUseDefLists[RegNo]; 166 } 167 168 /// getVRegDef - Return the machine instr that defines the specified virtual 169 /// register or null if none is found. This assumes that the code is in SSA 170 /// form, so there should only be one definition. 171 MachineInstr *getVRegDef(unsigned Reg) const; 172 173 /// clearKillFlags - Iterate over all the uses of the given register and 174 /// clear the kill flag from the MachineOperand. This function is used by 175 /// optimization passes which extend register lifetimes and need only 176 /// preserve conservative kill flag information. 177 void clearKillFlags(unsigned Reg) const; 178 179 #ifndef NDEBUG 180 void dumpUses(unsigned RegNo) const; 181 #endif 182 183 //===--------------------------------------------------------------------===// 184 // Virtual Register Info 185 //===--------------------------------------------------------------------===// 186 187 /// getRegClass - Return the register class of the specified virtual register. 188 /// 189 const TargetRegisterClass *getRegClass(unsigned Reg) const { 190 return VRegInfo[Reg].first; 191 } 192 193 /// setRegClass - Set the register class of the specified virtual register. 194 /// 195 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 196 197 /// constrainRegClass - Constrain the register class of the specified virtual 198 /// register to be a common subclass of RC and the current register class. 199 /// Return the new register class, or NULL if no such class exists. 200 /// This should only be used when the constraint is known to be trivial, like 201 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 202 const TargetRegisterClass *constrainRegClass(unsigned Reg, 203 const TargetRegisterClass *RC); 204 205 /// createVirtualRegister - Create and return a new virtual register in the 206 /// function with the specified register class. 207 /// 208 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 209 210 /// getNumVirtRegs - Return the number of virtual registers created. 211 /// 212 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 213 214 /// setRegAllocationHint - Specify a register allocation hint for the 215 /// specified virtual register. 216 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 217 RegAllocHints[Reg].first = Type; 218 RegAllocHints[Reg].second = PrefReg; 219 } 220 221 /// getRegAllocationHint - Return the register allocation hint for the 222 /// specified virtual register. 223 std::pair<unsigned, unsigned> 224 getRegAllocationHint(unsigned Reg) const { 225 return RegAllocHints[Reg]; 226 } 227 228 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 229 /// standard simple hint (Type == 0) is not set. 230 unsigned getSimpleHint(unsigned Reg) const { 231 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 232 return Hint.first ? 0 : Hint.second; 233 } 234 235 236 //===--------------------------------------------------------------------===// 237 // Physical Register Use Info 238 //===--------------------------------------------------------------------===// 239 240 /// isPhysRegUsed - Return true if the specified register is used in this 241 /// function. This only works after register allocation. 242 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 243 244 /// setPhysRegUsed - Mark the specified register used in this function. 245 /// This should only be called during and after register allocation. 246 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 247 248 /// addPhysRegsUsed - Mark the specified registers used in this function. 249 /// This should only be called during and after register allocation. 250 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 251 252 /// setPhysRegUnused - Mark the specified register unused in this function. 253 /// This should only be called during and after register allocation. 254 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 255 256 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 257 /// subregisters. That means that if R is used, so are all subregisters. 258 void closePhysRegsUsed(const TargetRegisterInfo&); 259 260 //===--------------------------------------------------------------------===// 261 // LiveIn/LiveOut Management 262 //===--------------------------------------------------------------------===// 263 264 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 265 /// is an error to add the same register to the same set more than once. 266 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 267 LiveIns.push_back(std::make_pair(Reg, vreg)); 268 } 269 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 270 271 // Iteration support for live in/out sets. These sets are kept in sorted 272 // order by their register number. 273 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 274 livein_iterator; 275 typedef std::vector<unsigned>::const_iterator liveout_iterator; 276 livein_iterator livein_begin() const { return LiveIns.begin(); } 277 livein_iterator livein_end() const { return LiveIns.end(); } 278 bool livein_empty() const { return LiveIns.empty(); } 279 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 280 liveout_iterator liveout_end() const { return LiveOuts.end(); } 281 bool liveout_empty() const { return LiveOuts.empty(); } 282 283 bool isLiveIn(unsigned Reg) const; 284 bool isLiveOut(unsigned Reg) const; 285 286 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 287 /// corresponding live-in physical register. 288 unsigned getLiveInPhysReg(unsigned VReg) const; 289 290 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 291 /// corresponding live-in physical register. 292 unsigned getLiveInVirtReg(unsigned PReg) const; 293 294 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 295 /// into the given entry block. 296 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 297 const TargetRegisterInfo &TRI, 298 const TargetInstrInfo &TII); 299 300 private: 301 void HandleVRegListReallocation(); 302 303 public: 304 /// defusechain_iterator - This class provides iterator support for machine 305 /// operands in the function that use or define a specific register. If 306 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 307 /// returns defs. If neither are true then you are silly and it always 308 /// returns end(). If SkipDebug is true it skips uses marked Debug 309 /// when incrementing. 310 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 311 class defusechain_iterator 312 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 313 MachineOperand *Op; 314 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 315 // If the first node isn't one we're interested in, advance to one that 316 // we are interested in. 317 if (op) { 318 if ((!ReturnUses && op->isUse()) || 319 (!ReturnDefs && op->isDef()) || 320 (SkipDebug && op->isDebug())) 321 ++*this; 322 } 323 } 324 friend class MachineRegisterInfo; 325 public: 326 typedef std::iterator<std::forward_iterator_tag, 327 MachineInstr, ptrdiff_t>::reference reference; 328 typedef std::iterator<std::forward_iterator_tag, 329 MachineInstr, ptrdiff_t>::pointer pointer; 330 331 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 332 defusechain_iterator() : Op(0) {} 333 334 bool operator==(const defusechain_iterator &x) const { 335 return Op == x.Op; 336 } 337 bool operator!=(const defusechain_iterator &x) const { 338 return !operator==(x); 339 } 340 341 /// atEnd - return true if this iterator is equal to reg_end() on the value. 342 bool atEnd() const { return Op == 0; } 343 344 // Iterator traversal: forward iteration only 345 defusechain_iterator &operator++() { // Preincrement 346 assert(Op && "Cannot increment end iterator!"); 347 Op = Op->getNextOperandForReg(); 348 349 // If this is an operand we don't care about, skip it. 350 while (Op && ((!ReturnUses && Op->isUse()) || 351 (!ReturnDefs && Op->isDef()) || 352 (SkipDebug && Op->isDebug()))) 353 Op = Op->getNextOperandForReg(); 354 355 return *this; 356 } 357 defusechain_iterator operator++(int) { // Postincrement 358 defusechain_iterator tmp = *this; ++*this; return tmp; 359 } 360 361 /// skipInstruction - move forward until reaching a different instruction. 362 /// Return the skipped instruction that is no longer pointed to, or NULL if 363 /// already pointing to end(). 364 MachineInstr *skipInstruction() { 365 if (!Op) return 0; 366 MachineInstr *MI = Op->getParent(); 367 do ++*this; 368 while (Op && Op->getParent() == MI); 369 return MI; 370 } 371 372 MachineOperand &getOperand() const { 373 assert(Op && "Cannot dereference end iterator!"); 374 return *Op; 375 } 376 377 /// getOperandNo - Return the operand # of this MachineOperand in its 378 /// MachineInstr. 379 unsigned getOperandNo() const { 380 assert(Op && "Cannot dereference end iterator!"); 381 return Op - &Op->getParent()->getOperand(0); 382 } 383 384 // Retrieve a reference to the current operand. 385 MachineInstr &operator*() const { 386 assert(Op && "Cannot dereference end iterator!"); 387 return *Op->getParent(); 388 } 389 390 MachineInstr *operator->() const { 391 assert(Op && "Cannot dereference end iterator!"); 392 return Op->getParent(); 393 } 394 }; 395 396 }; 397 398 } // End llvm namespace 399 400 #endif 401
