| /external/llvm/lib/CodeGen/ |
| ScheduleDAGEmit.cpp | 45 unsigned Reg = 0;
50 Reg = II->getReg();
54 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
|
| AllocationOrder.h | 57 unsigned Reg = *Pos++;
58 if (Reg != Hint)
59 return Reg;
|
| DeadMachineInstructionElim.cpp | 72 unsigned Reg = MO.getReg();
73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
74 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
108 unsigned Reg = *LOI;
109 if (TargetRegisterInfo::isPhysicalRegister(Reg))
110 LivePhysRegs.set(Reg);
138 unsigned Reg = MO.getReg();
139 if (!TargetRegisterInfo::isVirtualRegister(Reg))
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
[all...] |
| AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| LiveRangeEdit.cpp | 98 if ((*uselessRegs_)[ui]->reg == MO.getReg())
157 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
158 if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
159 LIS.removeInterval(Reg);
170 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
196 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
205 DefMI->addRegisterDead(LI->reg, 0);
246 unsigned Reg = MOI->getReg();
247 if (!TargetRegisterInfo::isVirtualRegister(Reg))
249 LiveInterval &LI = LIS.getInterval(Reg);
[all...] |
| MachineRegisterInfo.cpp | 45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 VRegInfo[Reg].first = RC;
50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
52 const TargetRegisterClass *OldRC = getRegClass(Reg);
59 setRegClass(Reg, NewRC);
73 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
75 // Add a reg, but keep track of whether the vector reallocated or not.
78 VRegInfo.grow(Reg);
79 VRegInfo[Reg].first = RegClass;
80 RegAllocHints.grow(Reg);
[all...] |
| ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx,
62 static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
67 if (MO1.getReg() != Reg)
110 unsigned Reg = MI->getOperand(0).getReg();
111 ImpDefRegs.insert(Reg);
112 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
113 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
139 unsigned Reg = MO.getReg();
140 if (!Reg)
142 if (!ImpDefRegs.count(Reg))
[all...] |
| RegisterScavenging.cpp | 17 #define DEBUG_TYPE "reg-scavenging"
37 void RegScavenger::setUsed(unsigned Reg) {
38 RegsAvailable.reset(Reg);
40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
45 bool RegScavenger::isAliasUsed(unsigned Reg) const {
46 if (isUsed(Reg))
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
112 BV.set(Reg);
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 35 if (unsigned Reg = State.AllocateReg(RegList, 4))
36 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
50 if (unsigned Reg = State.AllocateReg(RegList, 4))
51 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
80 if (Reg == 0) {
94 if (HiRegList[i] == Reg)
101 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
124 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
125 if (Reg == 0
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 130 unsigned Reg = MO.getReg();
133 Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::subreg_32bit);
135 Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::subreg_odd32);
140 O << '%' << getRegisterName(Reg);
|
| SystemZInstrBuilder.h | 41 unsigned Reg;
50 Base.Reg = 0;
59 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
61 // values, this adds: Reg, [0, NoReg] to the instruction.
62 return MIB.addReg(Reg).addImm(0).addReg(0);
71 /// [Reg + Offset], i.e., one with no or index, but with a
76 unsigned Reg, bool isKill, int Offset) {
77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
81 /// [Reg + Reg]
[all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 33 if (!Reg)
35 else if (TargetRegisterInfo::isStackSlot(Reg))
36 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
37 else if (TargetRegisterInfo::isVirtualRegister(Reg))
38 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
39 else if (TRI && Reg < TRI->getNumRegs())
40 OS << '%' << TRI->getName(Reg);
42 OS << "%physreg" << Reg;
55 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
56 assert(isPhysicalRegister(reg) && "reg must be a physical register")
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 120 unsigned Reg = MO.getReg();
121 if (!Reg)
123 for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI)
157 unsigned Reg = isSub
160 if (Reg) {
165 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
275 unsigned Reg = II->first;
277 if (Reg == X86::EAX || Reg == X86::AX ||
278 Reg == X86::AH || Reg == X86::AL
[all...] |
| X86FloatingPoint.cpp | 1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
119 unsigned Reg = *I - X86::FP0;
120 if (Reg < 8)
121 Mask |= 1 << Reg;
226 void pushReg(unsigned Reg) {
227 assert(Reg < NumFPRegs && "Register number out of range!");
230 Stack[StackTop] = Reg;
231 RegMap[Reg] = StackTop++;
272 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
282 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] i
[all...] |
| X86InstrBuilder.h | 45 unsigned Reg;
57 Base.Reg = 0;
65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
93 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
104 /// [Reg + Offset], i.e., one with no scale or index, but with a
109 unsigned Reg, bool isKill, int Offset) {
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 /// [Reg + Reg]
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.h | 23 enum MapKind { Operand, Imm, Reg };
28 Record *Reg; // Physical register.
|
| PseudoLoweringEmitter.cpp | 36 OperandMap[BaseIdx + i].Kind = OpData::Reg;
37 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
192 case OpData::Reg: {
193 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
196 if (Reg->getName() == "zero_reg")
199 o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
|
| /external/qemu/target-i386/ |
| ops_sse_header.h | 21 #define Reg MMXReg
24 #define Reg XMMReg
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 47 unsigned Reg;
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 87 // same class as Reg (P).
91 unsigned Reg,
97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
98 .addReg(Reg) // No kill on two-addr operand
105 if (BF::PRegClass.contains(Reg)) {
108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
109 .addReg(Reg, RegState::Kill)
112 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 169 unsigned Reg = CSI[I].getReg();
170 if (Reg == SPU::R0) continue;
172 MachineLocation CSSrc(Reg);
|
| SPURegisterInfo.cpp | 183 report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
351 unsigned Reg = RS->FindUnusedReg(RC);
352 if (Reg == 0)
353 Reg = RS->scavengeRegister(RC, II, SPAdj);
354 assert( Reg && "Register scavenger failed");
355 return Reg;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 196 unsigned Reg = CSI[i-1].getReg();
198 MBB.addLiveIn(Reg);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 274 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
275 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
277 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
328 unsigned Reg = VA.getLocReg();
330 DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
332 Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
338 MFI->addRetReg(Reg);
|
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 152 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
153 if (!LiveOutRegInfo.inBounds(Reg))
156 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
168 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
171 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
177 LiveOutRegInfo.grow(Reg);
178 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
196 unsigned Reg = It->second;
197 LiveOutRegInfo.grow(Reg);
198 LiveOutRegInfo[Reg].IsValid = false
[all...] |
