1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes an abstract interface used to get information about a 11 // target machines register file. This information is used for a variety of 12 // purposed, especially register allocation. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_MC_MCREGISTERINFO_H 17 #define LLVM_MC_MCREGISTERINFO_H 18 19 #include "llvm/ADT/DenseMap.h" 20 #include <cassert> 21 22 namespace llvm { 23 24 /// MCRegisterDesc - This record contains all of the information known about 25 /// a particular register. The Overlaps field contains a pointer to a zero 26 /// terminated array of registers that this register aliases, starting with 27 /// itself. This is needed for architectures like X86 which have AL alias AX 28 /// alias EAX. The SubRegs field is a zero terminated array of registers that 29 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 30 /// AX. The SuperRegs field is a zero terminated array of registers that are 31 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers 32 /// of AX. 33 /// 34 struct MCRegisterDesc { 35 const char *Name; // Printable name for the reg (for debugging) 36 const unsigned *Overlaps; // Overlapping registers, described above 37 const unsigned *SubRegs; // Sub-register set, described above 38 const unsigned *SuperRegs; // Super-register set, described above 39 }; 40 41 /// MCRegisterInfo base class - We assume that the target defines a static 42 /// array of MCRegisterDesc objects that represent all of the machine 43 /// registers that the target has. As such, we simply have to track a pointer 44 /// to this array so that we can turn register number into a register 45 /// descriptor. 46 /// 47 /// Note this class is designed to be a base class of TargetRegisterInfo, which 48 /// is the interface used by codegen. However, specific targets *should never* 49 /// specialize this class. MCRegisterInfo should only contain getters to access 50 /// TableGen generated physical register data. It must not be extended with 51 /// virtual methods. 52 /// 53 class MCRegisterInfo { 54 private: 55 const MCRegisterDesc *Desc; // Pointer to the descriptor array 56 unsigned NumRegs; // Number of entries in the array 57 unsigned RAReg; // Return address register 58 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping 59 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 60 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping 61 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 62 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 63 64 public: 65 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 66 /// auto-generated routines. *DO NOT USE*. 67 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) { 68 Desc = D; 69 NumRegs = NR; 70 RAReg = RA; 71 } 72 73 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf 74 /// register number mapping. Called by TableGen auto-generated routines. 75 /// *DO NOT USE*. 76 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) { 77 if (isEH) 78 EHL2DwarfRegs[LLVMReg] = DwarfReg; 79 else 80 L2DwarfRegs[LLVMReg] = DwarfReg; 81 } 82 83 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM 84 /// register number mapping. Called by TableGen auto-generated routines. 85 /// *DO NOT USE*. 86 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) { 87 if (isEH) 88 EHDwarf2LRegs[DwarfReg] = LLVMReg; 89 else 90 Dwarf2LRegs[DwarfReg] = LLVMReg; 91 } 92 93 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 94 /// number mapping. By default the SEH register number is just the same 95 /// as the LLVM register number. 96 /// FIXME: TableGen these numbers. Currently this requires target specific 97 /// initialization code. 98 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 99 L2SEHRegs[LLVMReg] = SEHReg; 100 } 101 102 /// getRARegister - This method should return the register where the return 103 /// address can be found. 104 unsigned getRARegister() const { 105 return RAReg; 106 } 107 108 const MCRegisterDesc &operator[](unsigned RegNo) const { 109 assert(RegNo < NumRegs && 110 "Attempting to access record for invalid register number!"); 111 return Desc[RegNo]; 112 } 113 114 /// Provide a get method, equivalent to [], but more useful if we have a 115 /// pointer to this object. 116 /// 117 const MCRegisterDesc &get(unsigned RegNo) const { 118 return operator[](RegNo); 119 } 120 121 /// getAliasSet - Return the set of registers aliased by the specified 122 /// register, or a null list of there are none. The list returned is zero 123 /// terminated. 124 /// 125 const unsigned *getAliasSet(unsigned RegNo) const { 126 // The Overlaps set always begins with Reg itself. 127 return get(RegNo).Overlaps + 1; 128 } 129 130 /// getOverlaps - Return a list of registers that overlap Reg, including 131 /// itself. This is the same as the alias set except Reg is included in the 132 /// list. 133 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 134 /// 135 const unsigned *getOverlaps(unsigned RegNo) const { 136 return get(RegNo).Overlaps; 137 } 138 139 /// getSubRegisters - Return the list of registers that are sub-registers of 140 /// the specified register, or a null list of there are none. The list 141 /// returned is zero terminated and sorted according to super-sub register 142 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 143 /// 144 const unsigned *getSubRegisters(unsigned RegNo) const { 145 return get(RegNo).SubRegs; 146 } 147 148 /// getSuperRegisters - Return the list of registers that are super-registers 149 /// of the specified register, or a null list of there are none. The list 150 /// returned is zero terminated and sorted according to super-sub register 151 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 152 /// 153 const unsigned *getSuperRegisters(unsigned RegNo) const { 154 return get(RegNo).SuperRegs; 155 } 156 157 /// getName - Return the human-readable symbolic target-specific name for the 158 /// specified physical register. 159 const char *getName(unsigned RegNo) const { 160 return get(RegNo).Name; 161 } 162 163 /// getNumRegs - Return the number of registers this target has (useful for 164 /// sizing arrays holding per register information) 165 unsigned getNumRegs() const { 166 return NumRegs; 167 } 168 169 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 170 /// number. Returns -1 if there is no equivalent value. The second 171 /// parameter allows targets to use different numberings for EH info and 172 /// debugging info. 173 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 174 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 175 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum); 176 if (I == M.end()) return -1; 177 return I->second; 178 } 179 180 /// getLLVMRegNum - Map a dwarf register back to a target register. 181 /// 182 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 183 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 184 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum); 185 if (I == M.end()) { 186 assert(0 && "Invalid RegNum"); 187 return -1; 188 } 189 return I->second; 190 } 191 192 /// getSEHRegNum - Map a target register to an equivalent SEH register 193 /// number. Returns LLVM register number if there is no equivalent value. 194 int getSEHRegNum(unsigned RegNum) const { 195 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 196 if (I == L2SEHRegs.end()) return (int)RegNum; 197 return I->second; 198 } 199 }; 200 201 } // End llvm namespace 202 203 #endif 204
