1 //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines a wrapper class for the 'Instruction' TableGen class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef CODEGEN_INSTRUCTION_H 15 #define CODEGEN_INSTRUCTION_H 16 17 #include "llvm/CodeGen/ValueTypes.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/Support/SourceMgr.h" 20 #include <string> 21 #include <vector> 22 #include <utility> 23 24 namespace llvm { 25 class Record; 26 class DagInit; 27 class CodeGenTarget; 28 class StringRef; 29 30 class CGIOperandList { 31 public: 32 class ConstraintInfo { 33 enum { None, EarlyClobber, Tied } Kind; 34 unsigned OtherTiedOperand; 35 public: 36 ConstraintInfo() : Kind(None) {} 37 38 static ConstraintInfo getEarlyClobber() { 39 ConstraintInfo I; 40 I.Kind = EarlyClobber; 41 I.OtherTiedOperand = 0; 42 return I; 43 } 44 45 static ConstraintInfo getTied(unsigned Op) { 46 ConstraintInfo I; 47 I.Kind = Tied; 48 I.OtherTiedOperand = Op; 49 return I; 50 } 51 52 bool isNone() const { return Kind == None; } 53 bool isEarlyClobber() const { return Kind == EarlyClobber; } 54 bool isTied() const { return Kind == Tied; } 55 56 unsigned getTiedOperand() const { 57 assert(isTied()); 58 return OtherTiedOperand; 59 } 60 }; 61 62 /// OperandInfo - The information we keep track of for each operand in the 63 /// operand list for a tablegen instruction. 64 struct OperandInfo { 65 /// Rec - The definition this operand is declared as. 66 /// 67 Record *Rec; 68 69 /// Name - If this operand was assigned a symbolic name, this is it, 70 /// otherwise, it's empty. 71 std::string Name; 72 73 /// PrinterMethodName - The method used to print operands of this type in 74 /// the asmprinter. 75 std::string PrinterMethodName; 76 77 /// EncoderMethodName - The method used to get the machine operand value 78 /// for binary encoding. "getMachineOpValue" by default. 79 std::string EncoderMethodName; 80 81 /// OperandType - A value from MCOI::OperandType representing the type of 82 /// the operand. 83 std::string OperandType; 84 85 /// MIOperandNo - Currently (this is meant to be phased out), some logical 86 /// operands correspond to multiple MachineInstr operands. In the X86 87 /// target for example, one address operand is represented as 4 88 /// MachineOperands. Because of this, the operand number in the 89 /// OperandList may not match the MachineInstr operand num. Until it 90 /// does, this contains the MI operand index of this operand. 91 unsigned MIOperandNo; 92 unsigned MINumOperands; // The number of operands. 93 94 /// DoNotEncode - Bools are set to true in this vector for each operand in 95 /// the DisableEncoding list. These should not be emitted by the code 96 /// emitter. 97 std::vector<bool> DoNotEncode; 98 99 /// MIOperandInfo - Default MI operand type. Note an operand may be made 100 /// up of multiple MI operands. 101 DagInit *MIOperandInfo; 102 103 /// Constraint info for this operand. This operand can have pieces, so we 104 /// track constraint info for each. 105 std::vector<ConstraintInfo> Constraints; 106 107 OperandInfo(Record *R, const std::string &N, const std::string &PMN, 108 const std::string &EMN, const std::string &OT, unsigned MION, 109 unsigned MINO, DagInit *MIOI) 110 : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN), 111 OperandType(OT), MIOperandNo(MION), MINumOperands(MINO), 112 MIOperandInfo(MIOI) {} 113 114 115 /// getTiedOperand - If this operand is tied to another one, return the 116 /// other operand number. Otherwise, return -1. 117 int getTiedRegister() const { 118 for (unsigned j = 0, e = Constraints.size(); j != e; ++j) { 119 const CGIOperandList::ConstraintInfo &CI = Constraints[j]; 120 if (CI.isTied()) return CI.getTiedOperand(); 121 } 122 return -1; 123 } 124 }; 125 126 CGIOperandList(Record *D); 127 128 Record *TheDef; // The actual record containing this OperandList. 129 130 /// NumDefs - Number of def operands declared, this is the number of 131 /// elements in the instruction's (outs) list. 132 /// 133 unsigned NumDefs; 134 135 /// OperandList - The list of declared operands, along with their declared 136 /// type (which is a record). 137 std::vector<OperandInfo> OperandList; 138 139 // Information gleaned from the operand list. 140 bool isPredicable; 141 bool hasOptionalDef; 142 bool isVariadic; 143 144 // Provide transparent accessors to the operand list. 145 bool empty() const { return OperandList.empty(); } 146 unsigned size() const { return OperandList.size(); } 147 const OperandInfo &operator[](unsigned i) const { return OperandList[i]; } 148 OperandInfo &operator[](unsigned i) { return OperandList[i]; } 149 OperandInfo &back() { return OperandList.back(); } 150 const OperandInfo &back() const { return OperandList.back(); } 151 152 153 /// getOperandNamed - Return the index of the operand with the specified 154 /// non-empty name. If the instruction does not have an operand with the 155 /// specified name, throw an exception. 156 unsigned getOperandNamed(StringRef Name) const; 157 158 /// hasOperandNamed - Query whether the instruction has an operand of the 159 /// given name. If so, return true and set OpIdx to the index of the 160 /// operand. Otherwise, return false. 161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const; 162 163 /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar", 164 /// where $foo is a whole operand and $foo.bar refers to a suboperand. 165 /// This throws an exception if the name is invalid. If AllowWholeOp is 166 /// true, references to operands with suboperands are allowed, otherwise 167 /// not. 168 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op, 169 bool AllowWholeOp = true); 170 171 /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a 172 /// flat machineinstr operand #. 173 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const { 174 return OperandList[Op.first].MIOperandNo + Op.second; 175 } 176 177 /// getSubOperandNumber - Unflatten a operand number into an 178 /// operand/suboperand pair. 179 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const { 180 for (unsigned i = 0; ; ++i) { 181 assert(i < OperandList.size() && "Invalid flat operand #"); 182 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op) 183 return std::make_pair(i, Op-OperandList[i].MIOperandNo); 184 } 185 } 186 187 188 /// isFlatOperandNotEmitted - Return true if the specified flat operand # 189 /// should not be emitted with the code emitter. 190 bool isFlatOperandNotEmitted(unsigned FlatOpNo) const { 191 std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo); 192 if (OperandList[Op.first].DoNotEncode.size() > Op.second) 193 return OperandList[Op.first].DoNotEncode[Op.second]; 194 return false; 195 } 196 197 void ProcessDisableEncoding(std::string Value); 198 }; 199 200 201 class CodeGenInstruction { 202 public: 203 Record *TheDef; // The actual record defining this instruction. 204 std::string Namespace; // The namespace the instruction is in. 205 206 /// AsmString - The format string used to emit a .s file for the 207 /// instruction. 208 std::string AsmString; 209 210 /// Operands - This is information about the (ins) and (outs) list specified 211 /// to the instruction. 212 CGIOperandList Operands; 213 214 /// ImplicitDefs/ImplicitUses - These are lists of registers that are 215 /// implicitly defined and used by the instruction. 216 std::vector<Record*> ImplicitDefs, ImplicitUses; 217 218 // Various boolean values we track for the instruction. 219 bool isReturn; 220 bool isBranch; 221 bool isIndirectBranch; 222 bool isCompare; 223 bool isMoveImm; 224 bool isBitcast; 225 bool isBarrier; 226 bool isCall; 227 bool canFoldAsLoad; 228 bool mayLoad, mayStore; 229 bool isPredicable; 230 bool isConvertibleToThreeAddress; 231 bool isCommutable; 232 bool isTerminator; 233 bool isReMaterializable; 234 bool hasDelaySlot; 235 bool usesCustomInserter; 236 bool hasCtrlDep; 237 bool isNotDuplicable; 238 bool hasSideEffects; 239 bool neverHasSideEffects; 240 bool isAsCheapAsAMove; 241 bool hasExtraSrcRegAllocReq; 242 bool hasExtraDefRegAllocReq; 243 bool isCodeGenOnly; 244 bool isPseudo; 245 246 247 CodeGenInstruction(Record *R); 248 249 /// HasOneImplicitDefWithKnownVT - If the instruction has at least one 250 /// implicit def and it has a known VT, return the VT, otherwise return 251 /// MVT::Other. 252 MVT::SimpleValueType 253 HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const; 254 255 256 /// FlattenAsmStringVariants - Flatten the specified AsmString to only 257 /// include text from the specified variant, returning the new string. 258 static std::string FlattenAsmStringVariants(StringRef AsmString, 259 unsigned Variant); 260 }; 261 262 263 /// CodeGenInstAlias - This represents an InstAlias definition. 264 class CodeGenInstAlias { 265 public: 266 Record *TheDef; // The actual record defining this InstAlias. 267 268 /// AsmString - The format string used to emit a .s file for the 269 /// instruction. 270 std::string AsmString; 271 272 /// Result - The result instruction. 273 DagInit *Result; 274 275 /// ResultInst - The instruction generated by the alias (decoded from 276 /// Result). 277 CodeGenInstruction *ResultInst; 278 279 280 struct ResultOperand { 281 private: 282 StringRef Name; 283 Record *R; 284 285 int64_t Imm; 286 public: 287 enum { 288 K_Record, 289 K_Imm, 290 K_Reg 291 } Kind; 292 293 ResultOperand(StringRef N, Record *r) : Name(N), R(r), Kind(K_Record) {} 294 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {} 295 ResultOperand(Record *r) : R(r), Kind(K_Reg) {} 296 297 bool isRecord() const { return Kind == K_Record; } 298 bool isImm() const { return Kind == K_Imm; } 299 bool isReg() const { return Kind == K_Reg; } 300 301 StringRef getName() const { assert(isRecord()); return Name; } 302 Record *getRecord() const { assert(isRecord()); return R; } 303 int64_t getImm() const { assert(isImm()); return Imm; } 304 Record *getRegister() const { assert(isReg()); return R; } 305 }; 306 307 /// ResultOperands - The decoded operands for the result instruction. 308 std::vector<ResultOperand> ResultOperands; 309 310 /// ResultInstOperandIndex - For each operand, this vector holds a pair of 311 /// indices to identify the corresponding operand in the result 312 /// instruction. The first index specifies the operand and the second 313 /// index specifies the suboperand. If there are no suboperands or if all 314 /// of them are matched by the operand, the second value should be -1. 315 std::vector<std::pair<unsigned, int> > ResultInstOperandIndex; 316 317 CodeGenInstAlias(Record *R, CodeGenTarget &T); 318 319 bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, 320 Record *InstOpRec, bool hasSubOps, SMLoc Loc, 321 CodeGenTarget &T, ResultOperand &ResOp); 322 }; 323 } 324 325 #endif 326