1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is responsible for emitting a description of a target 11 // register file for a code generator. It uses instances of the Register, 12 // RegisterAliases, and RegisterClass classes to gather this information. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "RegisterInfoEmitter.h" 17 #include "CodeGenTarget.h" 18 #include "CodeGenRegisters.h" 19 #include "Record.h" 20 #include "llvm/ADT/StringExtras.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Support/Format.h" 23 #include <algorithm> 24 #include <set> 25 using namespace llvm; 26 27 // runEnums - Print out enum values for all of the registers. 28 void 29 RegisterInfoEmitter::runEnums(raw_ostream &OS, 30 CodeGenTarget &Target, CodeGenRegBank &Bank) { 31 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 32 33 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 34 35 EmitSourceFileHeader("Target Register Enum Values", OS); 36 37 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 38 OS << "#undef GET_REGINFO_ENUM\n"; 39 40 OS << "namespace llvm {\n\n"; 41 42 if (!Namespace.empty()) 43 OS << "namespace " << Namespace << " {\n"; 44 OS << "enum {\n NoRegister,\n"; 45 46 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 47 OS << " " << Registers[i]->getName() << " = " << 48 Registers[i]->EnumValue << ",\n"; 49 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 50 "Register enum value mismatch!"); 51 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 52 OS << "};\n"; 53 if (!Namespace.empty()) 54 OS << "}\n"; 55 56 const std::vector<CodeGenRegisterClass> &RegisterClasses = 57 Target.getRegisterClasses(); 58 if (!RegisterClasses.empty()) { 59 OS << "\n// Register classes\n"; 60 if (!Namespace.empty()) 61 OS << "namespace " << Namespace << " {\n"; 62 OS << "enum {\n"; 63 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 64 if (i) OS << ",\n"; 65 OS << " " << RegisterClasses[i].getName() << "RegClassID"; 66 OS << " = " << i; 67 } 68 OS << "\n };\n"; 69 if (!Namespace.empty()) 70 OS << "}\n"; 71 } 72 73 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); 74 // If the only definition is the default NoRegAltName, we don't need to 75 // emit anything. 76 if (RegAltNameIndices.size() > 1) { 77 OS << "\n// Register alternate name indices\n"; 78 if (!Namespace.empty()) 79 OS << "namespace " << Namespace << " {\n"; 80 OS << "enum {\n"; 81 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 82 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 83 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 84 OS << "};\n"; 85 if (!Namespace.empty()) 86 OS << "}\n"; 87 } 88 89 90 OS << "} // End llvm namespace \n"; 91 OS << "#endif // GET_REGINFO_ENUM\n\n"; 92 } 93 94 void 95 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 96 const std::vector<CodeGenRegister*> &Regs, 97 bool isCtor) { 98 99 // Collect all information about dwarf register numbers 100 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 101 DwarfRegNumsMapTy DwarfRegNums; 102 103 // First, just pull all provided information to the map 104 unsigned maxLength = 0; 105 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 106 Record *Reg = Regs[i]->TheDef; 107 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 108 maxLength = std::max((size_t)maxLength, RegNums.size()); 109 if (DwarfRegNums.count(Reg)) 110 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 111 << "specified multiple times\n"; 112 DwarfRegNums[Reg] = RegNums; 113 } 114 115 if (!maxLength) 116 return; 117 118 // Now we know maximal length of number list. Append -1's, where needed 119 for (DwarfRegNumsMapTy::iterator 120 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 121 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 122 I->second.push_back(-1); 123 124 // Emit reverse information about the dwarf register numbers. 125 for (unsigned j = 0; j < 2; ++j) { 126 OS << " switch ("; 127 if (j == 0) 128 OS << "DwarfFlavour"; 129 else 130 OS << "EHFlavour"; 131 OS << ") {\n" 132 << " default:\n" 133 << " assert(0 && \"Unknown DWARF flavour\");\n" 134 << " break;\n"; 135 136 for (unsigned i = 0, e = maxLength; i != e; ++i) { 137 OS << " case " << i << ":\n"; 138 for (DwarfRegNumsMapTy::iterator 139 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 140 int DwarfRegNo = I->second[i]; 141 if (DwarfRegNo < 0) 142 continue; 143 OS << " "; 144 if (!isCtor) 145 OS << "RI->"; 146 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", " 147 << getQualifiedName(I->first) << ", "; 148 if (j == 0) 149 OS << "false"; 150 else 151 OS << "true"; 152 OS << " );\n"; 153 } 154 OS << " break;\n"; 155 } 156 OS << " }\n"; 157 } 158 159 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 160 Record *Reg = Regs[i]->TheDef; 161 const RecordVal *V = Reg->getValue("DwarfAlias"); 162 if (!V || !V->getValue()) 163 continue; 164 165 DefInit *DI = dynamic_cast<DefInit*>(V->getValue()); 166 Record *Alias = DI->getDef(); 167 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 168 } 169 170 // Emit information about the dwarf register numbers. 171 for (unsigned j = 0; j < 2; ++j) { 172 OS << " switch ("; 173 if (j == 0) 174 OS << "DwarfFlavour"; 175 else 176 OS << "EHFlavour"; 177 OS << ") {\n" 178 << " default:\n" 179 << " assert(0 && \"Unknown DWARF flavour\");\n" 180 << " break;\n"; 181 182 for (unsigned i = 0, e = maxLength; i != e; ++i) { 183 OS << " case " << i << ":\n"; 184 // Sort by name to get a stable order. 185 for (DwarfRegNumsMapTy::iterator 186 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 187 int RegNo = I->second[i]; 188 OS << " "; 189 if (!isCtor) 190 OS << "RI->"; 191 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", " 192 << RegNo << ", "; 193 if (j == 0) 194 OS << "false"; 195 else 196 OS << "true"; 197 OS << " );\n"; 198 } 199 OS << " break;\n"; 200 } 201 OS << " }\n"; 202 } 203 } 204 205 // 206 // runMCDesc - Print out MC register descriptions. 207 // 208 void 209 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 210 CodeGenRegBank &RegBank) { 211 EmitSourceFileHeader("MC Register Information", OS); 212 213 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 214 OS << "#undef GET_REGINFO_MC_DESC\n"; 215 216 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps; 217 RegBank.computeOverlaps(Overlaps); 218 219 OS << "namespace llvm {\n\n"; 220 221 const std::string &TargetName = Target.getName(); 222 std::string ClassName = TargetName + "GenMCRegisterInfo"; 223 OS << "struct " << ClassName << " : public MCRegisterInfo {\n" 224 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; 225 OS << "};\n"; 226 227 OS << "\nnamespace {\n"; 228 229 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 230 231 // Emit an overlap list for all registers. 232 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 233 const CodeGenRegister *Reg = Regs[i]; 234 const CodeGenRegister::Set &O = Overlaps[Reg]; 235 // Move Reg to the front so TRI::getAliasSet can share the list. 236 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " 237 << getQualifiedName(Reg->TheDef) << ", "; 238 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); 239 I != E; ++I) 240 if (*I != Reg) 241 OS << getQualifiedName((*I)->TheDef) << ", "; 242 OS << "0 };\n"; 243 } 244 245 // Emit the empty sub-registers list 246 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 247 // Loop over all of the registers which have sub-registers, emitting the 248 // sub-registers list to memory. 249 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 250 const CodeGenRegister &Reg = *Regs[i]; 251 if (Reg.getSubRegs().empty()) 252 continue; 253 // getSubRegs() orders by SubRegIndex. We want a topological order. 254 SetVector<CodeGenRegister*> SR; 255 Reg.addSubRegsPreOrder(SR); 256 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; 257 for (unsigned j = 0, je = SR.size(); j != je; ++j) 258 OS << getQualifiedName(SR[j]->TheDef) << ", "; 259 OS << "0 };\n"; 260 } 261 262 // Emit the empty super-registers list 263 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 264 // Loop over all of the registers which have super-registers, emitting the 265 // super-registers list to memory. 266 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 267 const CodeGenRegister &Reg = *Regs[i]; 268 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); 269 if (SR.empty()) 270 continue; 271 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; 272 for (unsigned j = 0, je = SR.size(); j != je; ++j) 273 OS << getQualifiedName(SR[j]->TheDef) << ", "; 274 OS << "0 };\n"; 275 } 276 OS << "}\n"; // End of anonymous namespace... 277 278 OS << "\nMCRegisterDesc " << TargetName 279 << "RegDesc[] = { // Descriptors\n"; 280 OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; 281 282 // Now that register alias and sub-registers sets have been emitted, emit the 283 // register descriptors now. 284 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 285 const CodeGenRegister &Reg = *Regs[i]; 286 OS << " { \""; 287 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; 288 if (!Reg.getSubRegs().empty()) 289 OS << Reg.getName() << "_SubRegsSet,\t"; 290 else 291 OS << "Empty_SubRegsSet,\t"; 292 if (!Reg.getSuperRegs().empty()) 293 OS << Reg.getName() << "_SuperRegsSet"; 294 else 295 OS << "Empty_SuperRegsSet"; 296 OS << " },\n"; 297 } 298 OS << "};\n\n"; // End of register descriptors... 299 300 // MCRegisterInfo initialization routine. 301 OS << "static inline void Init" << TargetName 302 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 303 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n"; 304 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 305 << Regs.size()+1 << ", RA);\n\n"; 306 307 EmitRegMapping(OS, Regs, false); 308 309 OS << "}\n\n"; 310 311 312 OS << "} // End llvm namespace \n"; 313 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 314 } 315 316 void 317 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 318 CodeGenRegBank &RegBank) { 319 EmitSourceFileHeader("Register Information Header Fragment", OS); 320 321 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 322 OS << "#undef GET_REGINFO_HEADER\n"; 323 324 const std::string &TargetName = Target.getName(); 325 std::string ClassName = TargetName + "GenRegisterInfo"; 326 327 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 328 OS << "#include <string>\n\n"; 329 330 OS << "namespace llvm {\n\n"; 331 332 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 333 << " explicit " << ClassName 334 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n" 335 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 336 << " { return false; }\n" 337 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 338 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" 339 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" 340 << "};\n\n"; 341 342 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 343 if (!SubRegIndices.empty()) { 344 OS << "\n// Subregister indices\n"; 345 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace"); 346 if (!Namespace.empty()) 347 OS << "namespace " << Namespace << " {\n"; 348 OS << "enum {\n NoSubRegister,\n"; 349 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i) 350 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 351 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; 352 OS << "};\n"; 353 if (!Namespace.empty()) 354 OS << "}\n"; 355 } 356 357 const std::vector<CodeGenRegisterClass> &RegisterClasses = 358 Target.getRegisterClasses(); 359 360 if (!RegisterClasses.empty()) { 361 OS << "namespace " << RegisterClasses[0].Namespace 362 << " { // Register classes\n"; 363 364 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 365 const CodeGenRegisterClass &RC = RegisterClasses[i]; 366 const std::string &Name = RC.getName(); 367 368 // Output the register class definition. 369 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 370 << " " << Name << "Class();\n"; 371 if (!RC.AltOrderSelect.empty()) 372 OS << " ArrayRef<unsigned> " 373 "getRawAllocationOrder(const MachineFunction&) const;\n"; 374 OS << " };\n"; 375 376 // Output the extern for the instance. 377 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 378 // Output the extern for the pointer to the instance (should remove). 379 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 380 << Name << "RegClass;\n"; 381 } 382 OS << "} // end of namespace " << TargetName << "\n\n"; 383 } 384 OS << "} // End llvm namespace \n"; 385 OS << "#endif // GET_REGINFO_HEADER\n\n"; 386 } 387 388 // 389 // runTargetDesc - Output the target register and register file descriptions. 390 // 391 void 392 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 393 CodeGenRegBank &RegBank){ 394 EmitSourceFileHeader("Target Register and Register Classes Information", OS); 395 396 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 397 OS << "#undef GET_REGINFO_TARGET_DESC\n"; 398 399 OS << "namespace llvm {\n\n"; 400 401 // Start out by emitting each of the register classes. 402 const std::vector<CodeGenRegisterClass> &RegisterClasses = 403 Target.getRegisterClasses(); 404 405 // Collect all registers belonging to any allocatable class. 406 std::set<Record*> AllocatableRegs; 407 408 // Loop over all of the register classes... emitting each one. 409 OS << "namespace { // Register classes...\n"; 410 411 // Emit the register enum value arrays for each RegisterClass 412 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 413 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 414 ArrayRef<Record*> Order = RC.getOrder(); 415 416 // Collect allocatable registers. 417 if (RC.Allocatable) 418 AllocatableRegs.insert(Order.begin(), Order.end()); 419 420 // Give the register class a legal C name if it's anonymous. 421 std::string Name = RC.getName(); 422 423 // Emit the register list now. 424 OS << " // " << Name << " Register Class...\n" 425 << " static const unsigned " << Name 426 << "[] = {\n "; 427 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 428 Record *Reg = Order[i]; 429 OS << getQualifiedName(Reg) << ", "; 430 } 431 OS << "\n };\n\n"; 432 } 433 434 // Emit the ValueType arrays for each RegisterClass 435 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 436 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 437 438 // Give the register class a legal C name if it's anonymous. 439 std::string Name = RC.getName() + "VTs"; 440 441 // Emit the register list now. 442 OS << " // " << Name 443 << " Register Class Value Types...\n" 444 << " static const EVT " << Name 445 << "[] = {\n "; 446 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 447 OS << getEnumName(RC.VTs[i]) << ", "; 448 OS << "MVT::Other\n };\n\n"; 449 } 450 OS << "} // end anonymous namespace\n\n"; 451 452 // Now that all of the structs have been emitted, emit the instances. 453 if (!RegisterClasses.empty()) { 454 OS << "namespace " << RegisterClasses[0].Namespace 455 << " { // Register class instances\n"; 456 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 457 OS << " " << RegisterClasses[i].getName() << "Class\t" 458 << RegisterClasses[i].getName() << "RegClass;\n"; 459 460 std::map<unsigned, std::set<unsigned> > SuperClassMap; 461 std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 462 OS << "\n"; 463 464 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); 465 466 if (NumSubRegIndices) { 467 // Emit the sub-register classes for each RegisterClass 468 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 469 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 470 std::vector<Record*> SRC(NumSubRegIndices); 471 for (DenseMap<Record*,Record*>::const_iterator 472 i = RC.SubRegClasses.begin(), 473 e = RC.SubRegClasses.end(); i != e; ++i) { 474 // Build SRC array. 475 unsigned idx = RegBank.getSubRegIndexNo(i->first); 476 SRC.at(idx-1) = i->second; 477 478 // Find the register class number of i->second for SuperRegClassMap. 479 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 480 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 481 if (RC2.TheDef == i->second) { 482 SuperRegClassMap[rc2].insert(rc); 483 break; 484 } 485 } 486 } 487 488 // Give the register class a legal C name if it's anonymous. 489 std::string Name = RC.TheDef->getName(); 490 491 OS << " // " << Name 492 << " Sub-register Classes...\n" 493 << " static const TargetRegisterClass* const " 494 << Name << "SubRegClasses[] = {\n "; 495 496 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) { 497 if (idx) 498 OS << ", "; 499 if (SRC[idx]) 500 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass"; 501 else 502 OS << "0"; 503 } 504 OS << "\n };\n\n"; 505 } 506 507 // Emit the super-register classes for each RegisterClass 508 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 509 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 510 511 // Give the register class a legal C name if it's anonymous. 512 std::string Name = RC.TheDef->getName(); 513 514 OS << " // " << Name 515 << " Super-register Classes...\n" 516 << " static const TargetRegisterClass* const " 517 << Name << "SuperRegClasses[] = {\n "; 518 519 bool Empty = true; 520 std::map<unsigned, std::set<unsigned> >::iterator I = 521 SuperRegClassMap.find(rc); 522 if (I != SuperRegClassMap.end()) { 523 for (std::set<unsigned>::iterator II = I->second.begin(), 524 EE = I->second.end(); II != EE; ++II) { 525 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 526 if (!Empty) 527 OS << ", "; 528 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 529 Empty = false; 530 } 531 } 532 533 OS << (!Empty ? ", " : "") << "NULL"; 534 OS << "\n };\n\n"; 535 } 536 } else { 537 // No subregindices in this target 538 OS << " static const TargetRegisterClass* const " 539 << "NullRegClasses[] = { NULL };\n\n"; 540 } 541 542 // Emit the sub-classes array for each RegisterClass 543 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 544 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 545 546 // Give the register class a legal C name if it's anonymous. 547 std::string Name = RC.TheDef->getName(); 548 549 OS << " // " << Name 550 << " Register Class sub-classes...\n" 551 << " static const TargetRegisterClass* const " 552 << Name << "Subclasses[] = {\n "; 553 554 bool Empty = true; 555 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 556 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 557 558 // Sub-classes are used to determine if a virtual register can be used 559 // as an instruction operand, or if it must be copied first. 560 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue; 561 562 if (!Empty) OS << ", "; 563 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 564 Empty = false; 565 566 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 567 SuperClassMap.find(rc2); 568 if (SCMI == SuperClassMap.end()) { 569 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 570 SCMI = SuperClassMap.find(rc2); 571 } 572 SCMI->second.insert(rc); 573 } 574 575 OS << (!Empty ? ", " : "") << "NULL"; 576 OS << "\n };\n\n"; 577 } 578 579 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 580 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 581 582 // Give the register class a legal C name if it's anonymous. 583 std::string Name = RC.TheDef->getName(); 584 585 OS << " // " << Name 586 << " Register Class super-classes...\n" 587 << " static const TargetRegisterClass* const " 588 << Name << "Superclasses[] = {\n "; 589 590 bool Empty = true; 591 std::map<unsigned, std::set<unsigned> >::iterator I = 592 SuperClassMap.find(rc); 593 if (I != SuperClassMap.end()) { 594 for (std::set<unsigned>::iterator II = I->second.begin(), 595 EE = I->second.end(); II != EE; ++II) { 596 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 597 if (!Empty) OS << ", "; 598 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 599 Empty = false; 600 } 601 } 602 603 OS << (!Empty ? ", " : "") << "NULL"; 604 OS << "\n };\n\n"; 605 } 606 607 // Emit methods. 608 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 609 const CodeGenRegisterClass &RC = RegisterClasses[i]; 610 OS << RC.getName() << "Class::" << RC.getName() 611 << "Class() : TargetRegisterClass(" 612 << RC.getName() + "RegClassID" << ", " 613 << '\"' << RC.getName() << "\", " 614 << RC.getName() + "VTs" << ", " 615 << RC.getName() + "Subclasses" << ", " 616 << RC.getName() + "Superclasses" << ", " 617 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null")) 618 << "RegClasses, " 619 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) 620 << "RegClasses, " 621 << RC.SpillSize/8 << ", " 622 << RC.SpillAlignment/8 << ", " 623 << RC.CopyCost << ", " 624 << RC.Allocatable << ", " 625 << RC.getName() << ", " << RC.getName() << " + " 626 << RC.getOrder().size() 627 << ") {}\n"; 628 if (!RC.AltOrderSelect.empty()) { 629 OS << "\nstatic inline unsigned " << RC.getName() 630 << "AltOrderSelect(const MachineFunction &MF) {" 631 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> " 632 << RC.getName() << "Class::" 633 << "getRawAllocationOrder(const MachineFunction &MF) const {\n"; 634 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 635 ArrayRef<Record*> Elems = RC.getOrder(oi); 636 OS << " static const unsigned AltOrder" << oi << "[] = {"; 637 for (unsigned elem = 0; elem != Elems.size(); ++elem) 638 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 639 OS << " };\n"; 640 } 641 OS << " static const ArrayRef<unsigned> Order[] = {\n" 642 << " makeArrayRef(" << RC.getName(); 643 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 644 OS << "),\n makeArrayRef(AltOrder" << oi; 645 OS << ")\n };\n const unsigned Select = " << RC.getName() 646 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 647 << ");\n return Order[Select];\n}\n"; 648 } 649 } 650 651 OS << "}\n"; 652 } 653 654 OS << "\nnamespace {\n"; 655 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 656 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 657 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 658 << "RegClass,\n"; 659 OS << " };\n"; 660 OS << "}\n"; // End of anonymous namespace... 661 662 // Emit extra information about registers. 663 const std::string &TargetName = Target.getName(); 664 OS << "\n static const TargetRegisterInfoDesc " 665 << TargetName << "RegInfoDesc[] = " 666 << "{ // Extra Descriptors\n"; 667 OS << " { 0, 0 },\n"; 668 669 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 670 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 671 const CodeGenRegister &Reg = *Regs[i]; 672 OS << " { "; 673 OS << Reg.CostPerUse << ", " 674 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 675 } 676 OS << " };\n"; // End of register descriptors... 677 678 679 // Calculate the mapping of subregister+index pairs to physical registers. 680 // This will also create further anonymous indexes. 681 unsigned NamedIndices = RegBank.getNumNamedIndices(); 682 683 // Emit SubRegIndex names, skipping 0 684 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 685 OS << "\n static const char *const " << TargetName 686 << "SubRegIndexTable[] = { \""; 687 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 688 OS << SubRegIndices[i]->getName(); 689 if (i+1 != e) 690 OS << "\", \""; 691 } 692 OS << "\" };\n\n"; 693 694 // Emit names of the anonymus subreg indexes. 695 if (SubRegIndices.size() > NamedIndices) { 696 OS << " enum {"; 697 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) { 698 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1; 699 if (i+1 != e) 700 OS << ','; 701 } 702 OS << "\n };\n\n"; 703 } 704 OS << "\n"; 705 706 std::string ClassName = Target.getName() + "GenRegisterInfo"; 707 708 // Emit the subregister + index mapping function based on the information 709 // calculated above. 710 OS << "unsigned " << ClassName 711 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 712 << " switch (RegNo) {\n" 713 << " default:\n return 0;\n"; 714 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 715 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs(); 716 if (SRM.empty()) 717 continue; 718 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; 719 OS << " switch (Index) {\n"; 720 OS << " default: return 0;\n"; 721 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 722 ie = SRM.end(); ii != ie; ++ii) 723 OS << " case " << getQualifiedName(ii->first) 724 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n"; 725 OS << " };\n" << " break;\n"; 726 } 727 OS << " };\n"; 728 OS << " return 0;\n"; 729 OS << "}\n\n"; 730 731 OS << "unsigned " << ClassName 732 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n" 733 << " switch (RegNo) {\n" 734 << " default:\n return 0;\n"; 735 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 736 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs(); 737 if (SRM.empty()) 738 continue; 739 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; 740 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 741 ie = SRM.end(); ii != ie; ++ii) 742 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef) 743 << ") return " << getQualifiedName(ii->first) << ";\n"; 744 OS << " return 0;\n"; 745 } 746 OS << " };\n"; 747 OS << " return 0;\n"; 748 OS << "}\n\n"; 749 750 // Emit composeSubRegIndices 751 OS << "unsigned " << ClassName 752 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" 753 << " switch (IdxA) {\n" 754 << " default:\n return IdxB;\n"; 755 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 756 bool Open = false; 757 for (unsigned j = 0; j != e; ++j) { 758 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i], 759 SubRegIndices[j])) { 760 if (!Open) { 761 OS << " case " << getQualifiedName(SubRegIndices[i]) 762 << ": switch(IdxB) {\n default: return IdxB;\n"; 763 Open = true; 764 } 765 OS << " case " << getQualifiedName(SubRegIndices[j]) 766 << ": return " << getQualifiedName(Comp) << ";\n"; 767 } 768 } 769 if (Open) 770 OS << " }\n"; 771 } 772 OS << " }\n}\n\n"; 773 774 // Emit the constructor of the class... 775 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n"; 776 777 OS << ClassName << "::" << ClassName 778 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n" 779 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 780 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 781 << " " << TargetName << "SubRegIndexTable) {\n" 782 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 783 << Regs.size()+1 << ", RA);\n\n"; 784 785 EmitRegMapping(OS, Regs, true); 786 787 OS << "}\n\n"; 788 789 OS << "} // End llvm namespace \n"; 790 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 791 } 792 793 void RegisterInfoEmitter::run(raw_ostream &OS) { 794 CodeGenTarget Target(Records); 795 CodeGenRegBank &RegBank = Target.getRegBank(); 796 RegBank.computeDerivedInfo(); 797 798 runEnums(OS, Target, RegBank); 799 runMCDesc(OS, Target, RegBank); 800 runTargetHeader(OS, Target, RegBank); 801 runTargetDesc(OS, Target, RegBank); 802 } 803
