| /external/clang/lib/StaticAnalyzer/Checkers/ |
| MallocOverflowSecurityChecker.cpp | 74 BinaryOperatorKind opc = binop->getOpcode(); local
76 if (mulop == NULL && opc == BO_Mul)
78 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl)
85 else if ((opc == BO_Add || opc == BO_Mul)
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 33 unsigned opc = I->getOpcode(); local
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
42 unsigned opc = I->getOpcode(); local
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr1
145 unsigned opc; local
180 unsigned opc; local
[all...] |
| /dalvik/dexopt/ |
| OptMain.cpp | 133 const char* opc; local
136 opc = strstr(dexoptFlagStr, "v="); /* verification */
137 if (opc != NULL) {
138 switch (*(opc+2)) {
146 opc = strstr(dexoptFlagStr, "o="); /* optimization */
147 if (opc != NULL) {
148 switch (*(opc+2)) {
157 opc = strstr(dexoptFlagStr, "m=y"); /* register map */
158 if (opc != NULL) {
162 opc = strstr(dexoptFlagStr, "u="); /* uniprocessor target *
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 241 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 local
244 opc = 2; // 0b0010
249 return ARM_AM::getSOImmVal(Value) | (opc << 21);
254 unsigned opc = 0; local
257 opc = 5;
260 uint32_t out = (opc << 21);
|
| /external/qemu/hw/ |
| bt-hci-csr.c | 184 int opc; local
188 opc = le16_to_cpu(((struct hci_command_hdr *) pkt)->opcode);
189 if (cmd_opcode_ogf(opc) == OGF_VENDOR_CMD) {
190 csrhci_in_packet_vendor(s, cmd_opcode_ocf(opc),
|
| /external/wpa_supplicant_6/wpa_supplicant/src/hlr_auc_gw/ |
| milenage.c | 33 * @opc: OPc = 128-bit value derived from OP and K
42 static int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
50 tmp1[i] = _rand[i] ^ opc[i];
63 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i];
73 tmp1[i] ^= opc[i];
84 * @opc: OPc = 128-bit value derived from OP and K
94 static int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
102 tmp1[i] = _rand[i] ^ opc[i]
356 u8 opc[16]; member in struct:gsm_milenage_test_set
585 u8 opc[16]; member in struct:milenage_test_set
1025 u8 buf[16], buf2[16], buf3[16], buf4[16], buf5[16], opc[16]; local
[all...] |
| hlr_auc_gw.c | 67 /* OPc and AMF parameters for Milenage (Example algorithms for AKA). */
72 u8 opc[16]; member in struct:milenage_parameters
271 /* Parse IMSI Ki OPc AMF SQN */
323 /* OPc */
326 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
331 if (strlen(pos) != 32 || hexstr2bin(pos, m->opc, 16)) {
332 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
423 gsm_milenage(m->opc, m->ki, _rand, sres, kc);
491 milenage_generate(m->opc, m->amf, m->ki, m->sqn, _rand,
564 if (milenage_auts(m->opc, m->ki, _rand, _auts, sqn))
[all...] |
| /dalvik/vm/analysis/ |
| Optimize.cpp | 168 Opcode opc, quickOpc, volatileOpc; local
172 opc = dexOpcodeFromCodeUnit(*insns);
205 switch (opc) {
380 switch (opc) {
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleSValBuilder.cpp | 342 BinaryOperator::Opcode opc = symIntExpr->getOpcode(); local
343 switch (opc) {
374 opc = NegateComparison(opc);
376 return makeNonLoc(symIntExpr->getLHS(), opc,
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 321 unsigned opc; // target opcode member in struct:llvm::TargetLowering::IntrinsicInfo
[all...] |
| /external/wpa_supplicant_8/hostapd/ |
| hlr_auc_gw.c | 68 /* OPc and AMF parameters for Milenage (Example algorithms for AKA). */
73 u8 opc[16]; member in struct:milenage_parameters
272 /* Parse IMSI Ki OPc AMF SQN */
324 /* OPc */
327 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
332 if (strlen(pos) != 32 || hexstr2bin(pos, m->opc, 16)) {
333 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
424 gsm_milenage(m->opc, m->ki, _rand, sres, kc);
492 milenage_generate(m->opc, m->amf, m->ki, m->sqn, _rand,
565 if (milenage_auts(m->opc, m->ki, _rand, _auts, sqn))
[all...] |
| /external/freetype/src/truetype/ |
| ttobjs.h | 178 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
|
| /external/wpa_supplicant_6/wpa_supplicant/src/eap_peer/ |
| eap_aka.c | 160 u8 opc[16], k[16], sqn[6]; local
177 if (hexstr2bin(pos, opc, 16))
187 return milenage_check(opc, k, sqn, data->rand, data->autn,
[all...] |
| eap_sim.c | 172 u8 opc[16], k[16]; local
190 if (hexstr2bin(pos, opc, 16))
194 if (gsm_milenage(opc, k, data->rand[i],
|
| /external/wpa_supplicant_8/src/eap_peer/ |
| eap_aka.c | 158 u8 opc[16], k[16], sqn[6]; local
175 if (hexstr2bin(pos, opc, 16))
185 return milenage_check(opc, k, sqn, data->rand, data->autn,
[all...] |
| eap_sim.c | 171 u8 opc[16], k[16]; local
189 if (hexstr2bin(pos, opc, 16))
193 if (gsm_milenage(opc, k, data->rand[i],
|
| /frameworks/base/core/jni/ |
| AndroidRuntime.cpp | 581 const char* opc; local
584 opc = strstr(dexoptFlagsBuf, "v="); /* verification */
585 if (opc != NULL) {
586 switch (*(opc+2)) {
599 opc = strstr(dexoptFlagsBuf, "o="); /* optimization */
600 if (opc != NULL) {
601 switch (*(opc+2)) {
615 opc = strstr(dexoptFlagsBuf, "m=y"); /* register map */
616 if (opc != NULL) {
[all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.c | 298 #define TO_CPSR(opc) \
299 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
385 int cond, int opc, int rd, int rn, int rm, int shift)
387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
411 int cond, int opc, int rd, int rn, int im)
413 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
435 int opc = ARITH_MOV; local
[all...] |
| /external/qemu/tcg/ |
| tcg.c | 73 #include "tcg-opc.h"
2024 TCGOpcode opc; local
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_amd64_defs.c | 2308 UInt \/*irno,*\/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local
[all...] |
| host_x86_defs.c | 1994 UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 3116 unsigned opc = fieldFromInstruction32(Insn, 4, 28); local
[all...] |
| /external/llvm/lib/VMCore/ |
| Constants.cpp | 1231 Instruction::CastOps opc = Instruction::CastOps(oc); local
[all...] |
| /external/qemu/tcg/i386/ |
| tcg-target.c | 351 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
355 if (opc & P_DATA16) {
357 assert((opc & P_REXW) == 0);
360 if (opc & P_ADDR32) {
365 rex |= (opc & P_REXW) >> 8; /* REX.W */
375 rex |= opc & (r >= 4 ? P_REXB_R : 0);
376 rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
382 if (opc & P_EXT) {
385 tcg_out8(s, opc);
388 static void tcg_out_opc(TCGContext *s, int opc)
518 int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); local
568 int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); local
575 int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0); local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : local
428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
640 unsigned opc = N->getOpcode(); local
642 switch (opc) {
716 bool isFPCmp, unsigned Opc) {
755 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
757 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
[all...] |
