/external/llvm/include/llvm/MC/ |
MCInstrItineraries.h | 197 /// index DefIdx can be bypassed when it's read by an instruction of 199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, 203 if ((FirstDefIdx + DefIdx) >= LastDefIdx) 205 if (Forwardings[FirstDefIdx + DefIdx] == 0) 213 return Forwardings[FirstDefIdx + DefIdx] == 220 int getOperandLatency(unsigned DefClass, unsigned DefIdx, 225 int DefCycle = getOperandCycle(DefClass, DefIdx); 235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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/external/llvm/lib/Target/ |
TargetInstrInfo.cpp | 66 const MachineInstr *DefMI, unsigned DefIdx, 73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 78 SDNode *DefNode, unsigned DefIdx, 88 return ItinData->getOperandCycle(DefClass, DefIdx); 90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 115 unsigned DefIdx) const { 120 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.h | 125 unsigned DefIdx; 143 return DefIdx-1;
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ScheduleDAGSDNodes.cpp | 507 DefIdx = 0; 513 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { 521 for (;DefIdx < NodeNumDefs; ++DefIdx) { 522 if (!Node->hasAnyUseOfValue(DefIdx)) 524 ValueType = Node->getValueType(DefIdx); 525 ++DefIdx; 587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 209 const MachineInstr *DefMI, unsigned DefIdx, 213 SDNode *DefNode, unsigned DefIdx, 225 unsigned DefIdx, unsigned DefAlign) const; 229 unsigned DefIdx, unsigned DefAlign) const; 240 unsigned DefIdx, unsigned DefAlign, 252 const MachineInstr *DefMI, unsigned DefIdx, 255 const MachineInstr *DefMI, unsigned DefIdx) const;
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ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
LiveRangeEdit.cpp | 122 SlotIndex DefIdx; 124 DefIdx = lis.getInstructionIndex(RM.OrigMI); 126 DefIdx = RM.ParentVNI->def; 127 RM.OrigMI = lis.getInstructionFromIndex(DefIdx); 136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
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RegisterCoalescer.cpp | 659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 660 assert(DefIdx != -1); 662 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 768 SlotIndex DefIdx = UseIdx.getDefIndex(); 769 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); 772 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); 773 assert(DVNI->def == DefIdx); [all...] |
ScheduleDAGInstrs.cpp | 600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); 601 if (DefIdx != -1) { 602 const MachineOperand &MO = DefMI->getOperand(DefIdx); 604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) { 611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI); 625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx, 634 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
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MachineInstr.cpp | 869 unsigned DefIdx; 870 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 871 OpIdx = DefIdx; [all...] |
InlineSpiller.cpp | [all...] |
MachineVerifier.cpp | 634 unsigned defIdx; 635 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) { 637 unsigned DefReg = MI->getOperand(defIdx).getReg(); 713 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex(); 716 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 718 if (VNI->def != DefIdx && !MO->isEarlyClobber()) { 721 << DefIdx << " in " << LI << '\n'; 725 *OS << DefIdx << " is not live in " << LI << '\n'; [all...] |
RegAllocFast.cpp | 692 unsigned DefIdx = 0; 693 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 695 << DefIdx << ".\n"); [all...] |
VirtRegRewriter.cpp | [all...] |
MachineLICM.cpp | 195 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, [all...] |
LiveIntervalAnalysis.cpp | 537 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_); 538 if (DefIdx != -1) { 539 if (mi->isRegTiedToUseOperand(DefIdx)) { 656 SlotIndex defIdx = getMBBStartIdx(MBB); 657 assert(getInstructionFromIndex(defIdx) == 0 && 660 interval.getNextValue(defIdx, 0, VNInfoAllocator); [all...] |
/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | 644 const MachineInstr *DefMI, unsigned DefIdx, 648 SDNode *DefNode, unsigned DefIdx, 673 const MachineInstr *DefMI, unsigned DefIdx, [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 358 const MachineInstr *DefMI, unsigned DefIdx,
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X86InstrInfo.cpp | [all...] |