| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
139 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
141 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
143 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeTypes.cpp | [all...] |
| TargetLowering.cpp | 691 EVT DestVT = TLI->getRegisterType(NewVT);
692 RegisterVT = DestVT;
693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
[all...] |
| LegalizeTypes.h | 148 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
[all...] |
| LegalizeVectorTypes.cpp | 207 EVT DestVT = N->getValueType(0).getVectorElementType();
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
