| /external/llvm/lib/Target/CellSPU/ |
| SPUSubtarget.h | 42 InstrItineraryData InstrItins;
75 return InstrItins;
|
| SPUTargetMachine.h | 39 InstrItineraryData InstrItins;
80 return &InstrItins;
|
| SPUSubtarget.cpp | 41 InstrItins = getInstrItineraryForCPU(default_cpu);
|
| SPUTargetMachine.cpp | 45 InstrItins(Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaSubtarget.cpp | 34 InstrItins = getInstrItineraryForCPU(CPUName);
|
| AlphaSubtarget.h | 32 InstrItineraryData InstrItins;
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeSubtarget.cpp | 45 InstrItins = getInstrItineraryForCPU(CPUName);
52 InstrItins.IssueWidth = 1;
|
| MBlazeSubtarget.h | 39 InstrItineraryData InstrItins;
62 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| MBlazeTargetMachine.h | 41 InstrItineraryData InstrItins;
52 { return &InstrItins; }
|
| MBlazeTargetMachine.cpp | 44 InstrItins(Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMSubtarget.cpp | 100 InstrItins = getInstrItineraryForCPU(CPUString);
196 for (const InstrItinerary *itin = InstrItins.Itineraries;
198 const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
201 InstrItins.IssueWidth = 0;
203 ++InstrItins.IssueWidth;
207 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
|
| ARMSubtarget.h | 154 InstrItineraryData InstrItins;
254 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| ARMTargetMachine.h | 39 InstrItineraryData InstrItins;
49 return &InstrItins;
|
| ARMTargetMachine.cpp | 45 InstrItins(Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.h | 57 InstrItineraryData InstrItins;
103 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| PPCTargetMachine.h | 40 InstrItineraryData InstrItins;
65 return &InstrItins;
|
| PPCSubtarget.cpp | 95 InstrItins = getInstrItineraryForCPU(CPUName);
|
| PPCTargetMachine.cpp | 38 InstrItins(Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsSubtarget.cpp | 40 InstrItins = getInstrItineraryForCPU(CPUName);
|
| MipsSubtarget.h | 88 InstrItineraryData InstrItins;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 39 const InstrItineraryData *InstrItins;
|
| ScheduleDAGSDNodes.cpp | 48 InstrItins(mf.getTarget().getInstrItineraryData()) {}
561 if (!InstrItins || InstrItins->isEmpty()) {
575 SU->Latency += TII->getInstrLatency(InstrItins, N);
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
|
| /external/llvm/lib/CodeGen/ |
| ScheduleDAGInstrs.cpp | 38 InstrItins(mf.getTarget().getInstrItineraryData()),
574 if (!InstrItins || InstrItins->isEmpty()) {
582 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
588 if (!InstrItins || InstrItins->isEmpty())
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
631 if (!InstrItins || InstrItins->isEmpty())
634 Latency = InstrItins->getOperandCycle(DefClass, DefIdx)
[all...] |
| ScheduleDAGInstrs.h | 105 const InstrItineraryData *InstrItins;
|
| MachineLICM.cpp | 71 const InstrItineraryData *InstrItins;
321 InstrItins = TM->getInstrItineraryData();
[all...] |
