/external/llvm/include/llvm/Analysis/ |
ConstantsScanner.h | 28 unsigned OpIdx; // Operand index 33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() && 35 return isa<Constant>(InstI->getOperand(OpIdx)); 39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) { 47 : InstI(inst_end(F)), OpIdx(0) { 50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx && 56 return cast<Constant>(InstI->getOperand(OpIdx)); 61 ++OpIdx; 64 while (OpIdx < NumOperands && !isAtConstant()) [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, [all...] |
/external/llvm/lib/Target/ARM/ |
ARMCodeEmitter.cpp | 103 unsigned OpIdx); 156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 249 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 251 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 291 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 293 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 295 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 297 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) [all...] |
ARMExpandPseudoInsts.cpp | 419 unsigned OpIdx = 0; 421 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 422 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 433 MIB.addOperand(MI.getOperand(OpIdx++)); 436 MIB.addOperand(MI.getOperand(OpIdx++)); 437 MIB.addOperand(MI.getOperand(OpIdx++)); 440 MIB.addOperand(MI.getOperand(OpIdx++)); 447 SrcOpIdx = OpIdx++; 450 MIB.addOperand(MI.getOperand(OpIdx++)); 451 MIB.addOperand(MI.getOperand(OpIdx++)) [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
ProcessImplicitDefs.h | 34 unsigned OpIdx,
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MachineInstr.h | 393 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 394 /// getOperand(OpIdx) does not belong to an inline asm operand group. 397 /// containing OpIdx. 402 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const; 405 /// operand OpIdx. For normal instructions, this is derived from the 412 getRegClassConstraint(unsigned OpIdx,
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/external/llvm/utils/TableGen/ |
CodeEmitterGen.cpp | 107 unsigned OpIdx; 108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { 110 OpIdx = CGI.Operands[OpIdx].MIOperandNo; 111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && 118 OpIdx = NumberedOp++; 121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); 132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); 139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
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CodeGenInstruction.cpp | 135 unsigned OpIdx; 136 if (hasOperandNamed(Name, OpIdx)) return OpIdx; 142 /// given name. If so, return true and set OpIdx to the index of the 144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { 148 OpIdx = i; 171 unsigned OpIdx = getOperandNamed(OpName); 175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && 181 return std::make_pair(OpIdx, 0U); 185 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo [all...] |
CodeGenInstruction.h | 159 /// given name. If so, return true and set OpIdx to the index of the 161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
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/external/llvm/lib/CodeGen/ |
ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx, 51 switch(OpIdx) { 263 unsigned OpIdx = Ops[j]; 264 RMI->RemoveOperand(OpIdx-j);
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MachineInstr.cpp | 829 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 832 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 835 if (OpIdx < InlineAsm::MIOp_FirstOperand) 847 if (i + NumOps > OpIdx) { 858 MachineInstr::getRegClassConstraint(unsigned OpIdx, 863 return TII->getRegClass(getDesc(), OpIdx, TRI); 865 if (!getOperand(OpIdx).isReg()) 870 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx) [all...] |
DwarfEHPrepare.cpp | 190 unsigned OpIdx = Sel->getNumArgOperands() - 1; 191 GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx)); 193 Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer());
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LiveIntervalAnalysis.cpp | [all...] |
MachineLICM.cpp | 230 unsigned Reg, unsigned OpIdx, 669 unsigned Reg, unsigned OpIdx, [all...] |
RegisterCoalescer.cpp | 724 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); 725 NewMI->getOperand(OpIdx).setIsKill(); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.h | 104 unsigned OpIdx, SDep& dep) const;
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ScheduleDAGSDNodes.cpp | 579 unsigned OpIdx, SDep& dep) const{ 587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 590 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); 591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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LegalizeVectorTypes.cpp | [all...] |
/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
MBlazeMCCodeEmitter.cpp | 51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const { 52 return getMachineOpValue(MI, MI.getOperand(OpIdx));
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/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |