/external/llvm/lib/Target/PTX/ |
PTXISelLowering.cpp | 75 // select_cc => setcc 92 // customise setcc to use bitwise logic if possible 94 setOperationAction(ISD::SETCC, MVT::i1, Custom); 113 case ISD::SETCC: 148 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer"); 166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 328 // Much like the scalar select and setcc, each bit in the condition selects 338 // SetCC operator - This evaluates to a true value iff the condition is 344 SETCC, 492 // compare, rather than as a combined SetCC node. The operands in order are [all...] |
SelectionDAG.h | 562 /// getSetCC - Helper function to make it easier to build SetCC's if you just 571 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag 52 SETCC,
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MSP430ISelLowering.cpp | 115 setOperationAction(ISD::SETCC, MVT::i8, Custom); 116 setOperationAction(ISD::SETCC, MVT::i16, Custom); 188 case ISD::SETCC: return LowerSETCC(Op, DAG); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 194 case ISD::SETCC: 252 else if (Node->getOpcode() == ISD::SETCC) 481 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
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LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 256 // Turn it into a scalar SETCC. 257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 283 // Turn it into a scalar SETCC. 284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 435 case ISD::SETCC: [all...] |
DAGCombiner.cpp | 495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 496 // that selects between the values 1 and 0, making it equivalent to a setcc. 502 if (N.getOpcode() == ISD::SETCC) { 521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only [all...] |
LegalizeFloatTypes.cpp | 591 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; 611 /// shared among BR_CC, SELECT_CC, and SETCC handlers. 618 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!"); 675 default: assert(false && "Do not know how to soften this setcc!"); 686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), 689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS, [all...] |
LegalizeDAG.cpp | 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 46 /// will attempt merge setcc and brc instructions into brcc's. [all...] |
TargetLowering.cpp | [all...] |
LegalizeIntegerTypes.cpp | 69 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 518 // Get the SETCC result using the canonical SETCC type. 519 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), 524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 774 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break [all...] |
SelectionDAG.cpp | 224 /// 'op' is a valid SetCC operation. 244 default: llvm_unreachable("Illegal integer setcc operation!"); 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 275 // Canonicalize illegal integer setcc's. 289 // Cannot fold a signed setcc with an unsigned setcc. 295 // Canonicalize illegal integer setcc's. [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 117 setOperationAction(ISD::SETCC, MVT::i32, Expand); 118 setOperationAction(ISD::SETCC, MVT::i64, Expand); 119 setOperationAction(ISD::SETCC, MVT::f32, Expand); 120 setOperationAction(ISD::SETCC, MVT::f64, Expand); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 182 // X86 is weird, it always uses i8 for shift amounts and setcc results. 424 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 425 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 426 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 427 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 428 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 429 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 432 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); [all...] |
X86ISelLowering.h | 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 91 SETCC, 93 // Same as SETCC except it's materialized with a sbb and the value is all 97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 583 /// getSetCCResultType - Return the value type to use for ISD::SETCC. [all...] |
/external/llvm/lib/Target/Alpha/ |
AlphaISelDAGToDAG.cpp | 302 case ISD::SETCC:
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AlphaISelLowering.cpp | 129 setOperationAction(ISD::SETCC, MVT::f32, Promote); [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 313 setOperationAction(ISD::SETCC, MVT::i8, Legal); 314 setOperationAction(ISD::SETCC, MVT::i16, Legal); 315 setOperationAction(ISD::SETCC, MVT::i32, Legal); 316 setOperationAction(ISD::SETCC, MVT::i64, Legal); 317 setOperationAction(ISD::SETCC, MVT::f64, Custom); 511 // Return the Cell SPU's SETCC result type 515 // i8, i16 and i32 are valid SETCC result types [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 731 // Sparc has no select or setcc: expand to SELECT_CC. 735 setOperationAction(ISD::SETCC, MVT::i32, Expand); 736 setOperationAction(ISD::SETCC, MVT::f32, Expand); 737 setOperationAction(ISD::SETCC, MVT::f64, Expand); [all...] |
/external/llvm/lib/Target/Blackfin/ |
BlackfinISelLowering.cpp | 76 setOperationAction(ISD::SETCC, MVT::i16, Promote); 140 // SETCC always sets the CC register. Technically that is an i1 register, but
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/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 90 // setcc operations results (slt, sgt, ...). 118 // Used by legalize types to correctly generate the setcc result. 119 // Without this, every float setcc comes with a AND/OR with the result, 122 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 221 setTargetDAGCombine(ISD::SETCC); 491 // Creates and returns an FPCmp node from a setcc node. 492 // Returns Op if setcc is not a floating point comparison. 494 // must be a SETCC node 495 if (Op.getOpcode() != ISD::SETCC) 651 case ISD::SETCC [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 60 // setcc operations results (slt, sgt, ...). 138 // Used by legalize types to correctly generate the setcc result. 139 // Without this, every float setcc comes with a AND/OR with the result, 142 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 362 // setcc r1, r2, r3 [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 573 /// associated with the SetCC condition, and whether or not the field is 617 // We can codegen setcc op, imm very efficiently compared to a brcond. 619 // setcc op, 0 649 } else if (Imm == ~0U) { // setcc op, -1 819 case ISD::SETCC: [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 685 setOperationAction(ISD::SETCC, MVT::i32, Expand); 686 setOperationAction(ISD::SETCC, MVT::f32, Expand); 687 setOperationAction(ISD::SETCC, MVT::f64, Expand); [all...] |