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      1 //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef ARMSUBTARGET_H
     15 #define ARMSUBTARGET_H
     16 
     17 #include "MCTargetDesc/ARMMCTargetDesc.h"
     18 #include "llvm/Target/TargetSubtargetInfo.h"
     19 #include "llvm/MC/MCInstrItineraries.h"
     20 #include "llvm/ADT/Triple.h"
     21 #include <string>
     22 
     23 #define GET_SUBTARGETINFO_HEADER
     24 #include "ARMGenSubtargetInfo.inc"
     25 
     26 namespace llvm {
     27 class GlobalValue;
     28 class StringRef;
     29 
     30 class ARMSubtarget : public ARMGenSubtargetInfo {
     31 protected:
     32   enum ARMProcFamilyEnum {
     33     Others, CortexA8, CortexA9
     34   };
     35 
     36   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
     37   ARMProcFamilyEnum ARMProcFamily;
     38 
     39   /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
     40   /// Specify whether target support specific ARM ISA variants.
     41   bool HasV4TOps;
     42   bool HasV5TOps;
     43   bool HasV5TEOps;
     44   bool HasV6Ops;
     45   bool HasV6T2Ops;
     46   bool HasV7Ops;
     47 
     48   /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
     49   /// supported.
     50   bool HasVFPv2;
     51   bool HasVFPv3;
     52   bool HasNEON;
     53 
     54   /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
     55   /// specified. Use the method useNEONForSinglePrecisionFP() to
     56   /// determine if NEON should actually be used.
     57   bool UseNEONForSinglePrecisionFP;
     58 
     59   /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
     60   /// whether the FP VML[AS] instructions are slow (if so, don't use them).
     61   bool SlowFPVMLx;
     62 
     63   /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
     64   /// forwarding to allow mul + mla being issued back to back.
     65   bool HasVMLxForwarding;
     66 
     67   /// SlowFPBrcc - True if floating point compare + branch is slow.
     68   bool SlowFPBrcc;
     69 
     70   /// InThumbMode - True if compiling for Thumb, false for ARM.
     71   bool InThumbMode;
     72 
     73   /// HasThumb2 - True if Thumb2 instructions are supported.
     74   bool HasThumb2;
     75 
     76   /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
     77   /// v6m, v7m for example.
     78   bool IsMClass;
     79 
     80   /// NoARM - True if subtarget does not support ARM mode execution.
     81   bool NoARM;
     82 
     83   /// PostRAScheduler - True if using post-register-allocation scheduler.
     84   bool PostRAScheduler;
     85 
     86   /// IsR9Reserved - True if R9 is a not available as general purpose register.
     87   bool IsR9Reserved;
     88 
     89   /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
     90   /// imms (including global addresses).
     91   bool UseMovt;
     92 
     93   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
     94   /// must be able to synthesize call stubs for interworking between ARM and
     95   /// Thumb.
     96   bool SupportsTailCall;
     97 
     98   /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
     99   /// only so far)
    100   bool HasFP16;
    101 
    102   /// HasD16 - True if subtarget is limited to 16 double precision
    103   /// FP registers for VFPv3.
    104   bool HasD16;
    105 
    106   /// HasHardwareDivide - True if subtarget supports [su]div
    107   bool HasHardwareDivide;
    108 
    109   /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
    110   /// instructions.
    111   bool HasT2ExtractPack;
    112 
    113   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
    114   /// instructions.
    115   bool HasDataBarrier;
    116 
    117   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
    118   /// over 16-bit ones.
    119   bool Pref32BitThumb;
    120 
    121   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
    122   /// that partially update CPSR and add false dependency on the previous
    123   /// CPSR setting instruction.
    124   bool AvoidCPSRPartialUpdate;
    125 
    126   /// HasMPExtension - True if the subtarget supports Multiprocessing
    127   /// extension (ARMv7 only).
    128   bool HasMPExtension;
    129 
    130   /// FPOnlySP - If true, the floating point unit only supports single
    131   /// precision.
    132   bool FPOnlySP;
    133 
    134   /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
    135   /// accesses for some types.  For details, see
    136   /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
    137   bool AllowsUnalignedMem;
    138 
    139   /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
    140   /// and such) instructions in Thumb2 code.
    141   bool Thumb2DSP;
    142 
    143   /// stackAlignment - The minimum alignment known to hold of the stack frame on
    144   /// entry to the function and which must be maintained by every function.
    145   unsigned stackAlignment;
    146 
    147   /// CPUString - String name of used CPU.
    148   std::string CPUString;
    149 
    150   /// TargetTriple - What processor and OS we're targeting.
    151   Triple TargetTriple;
    152 
    153   /// Selected instruction itineraries (one entry per itinerary class.)
    154   InstrItineraryData InstrItins;
    155 
    156  public:
    157   enum {
    158     isELF, isDarwin
    159   } TargetType;
    160 
    161   enum {
    162     ARM_ABI_APCS,
    163     ARM_ABI_AAPCS // ARM EABI
    164   } TargetABI;
    165 
    166   /// This constructor initializes the data members to match that
    167   /// of the specified triple.
    168   ///
    169   ARMSubtarget(const std::string &TT, const std::string &CPU,
    170                const std::string &FS);
    171 
    172   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
    173   /// that still makes it profitable to inline the call.
    174   unsigned getMaxInlineSizeThreshold() const {
    175     // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
    176     // Change this once Thumb1 ldmia / stmia support is added.
    177     return isThumb1Only() ? 0 : 64;
    178   }
    179   /// ParseSubtargetFeatures - Parses features string setting specified
    180   /// subtarget options.  Definition of function is auto generated by tblgen.
    181   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
    182 
    183   void computeIssueWidth();
    184 
    185   bool hasV4TOps()  const { return HasV4TOps;  }
    186   bool hasV5TOps()  const { return HasV5TOps;  }
    187   bool hasV5TEOps() const { return HasV5TEOps; }
    188   bool hasV6Ops()   const { return HasV6Ops;   }
    189   bool hasV6T2Ops() const { return HasV6T2Ops; }
    190   bool hasV7Ops()   const { return HasV7Ops;  }
    191 
    192   bool isCortexA8() const { return ARMProcFamily == CortexA8; }
    193   bool isCortexA9() const { return ARMProcFamily == CortexA9; }
    194 
    195   bool hasARMOps() const { return !NoARM; }
    196 
    197   bool hasVFP2() const { return HasVFPv2; }
    198   bool hasVFP3() const { return HasVFPv3; }
    199   bool hasNEON() const { return HasNEON;  }
    200   bool useNEONForSinglePrecisionFP() const {
    201     return hasNEON() && UseNEONForSinglePrecisionFP; }
    202 
    203   bool hasDivide() const { return HasHardwareDivide; }
    204   bool hasT2ExtractPack() const { return HasT2ExtractPack; }
    205   bool hasDataBarrier() const { return HasDataBarrier; }
    206   bool useFPVMLx() const { return !SlowFPVMLx; }
    207   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
    208   bool isFPBrccSlow() const { return SlowFPBrcc; }
    209   bool isFPOnlySP() const { return FPOnlySP; }
    210   bool prefers32BitThumb() const { return Pref32BitThumb; }
    211   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
    212   bool hasMPExtension() const { return HasMPExtension; }
    213   bool hasThumb2DSP() const { return Thumb2DSP; }
    214 
    215   bool hasFP16() const { return HasFP16; }
    216   bool hasD16() const { return HasD16; }
    217 
    218   const Triple &getTargetTriple() const { return TargetTriple; }
    219 
    220   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
    221   bool isTargetNaCl() const {
    222     return TargetTriple.getOS() == Triple::NativeClient;
    223   }
    224   bool isTargetELF() const { return !isTargetDarwin(); }
    225 
    226   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
    227   bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
    228 
    229   bool isThumb() const { return InThumbMode; }
    230   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
    231   bool isThumb2() const { return InThumbMode && HasThumb2; }
    232   bool hasThumb2() const { return HasThumb2; }
    233   bool isMClass() const { return IsMClass; }
    234   bool isARClass() const { return !IsMClass; }
    235 
    236   bool isR9Reserved() const { return IsR9Reserved; }
    237 
    238   bool useMovt() const { return UseMovt && hasV6T2Ops(); }
    239   bool supportsTailCall() const { return SupportsTailCall; }
    240 
    241   bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
    242 
    243   const std::string & getCPUString() const { return CPUString; }
    244 
    245   unsigned getMispredictionPenalty() const;
    246 
    247   /// enablePostRAScheduler - True at 'More' optimization.
    248   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
    249                              TargetSubtargetInfo::AntiDepBreakMode& Mode,
    250                              RegClassVector& CriticalPathRCs) const;
    251 
    252   /// getInstrItins - Return the instruction itineraies based on subtarget
    253   /// selection.
    254   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
    255 
    256   /// getStackAlignment - Returns the minimum alignment known to hold of the
    257   /// stack frame on entry to the function and which must be maintained by every
    258   /// function for this subtarget.
    259   unsigned getStackAlignment() const { return stackAlignment; }
    260 
    261   /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
    262   /// symbol.
    263   bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
    264 };
    265 } // End llvm namespace
    266 
    267 #endif  // ARMSUBTARGET_H
    268