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Searched
refs:isUse
(Results
1 - 25
of
45
) sorted by null
1
2
/external/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp
223
if (MO.
isUse
()) {
245
assert(Reg.
isUse
() && "JMPL first operand is not a use.");
252
assert(RegOrImm.
isUse
() && "JMPLrr second operand is not a use.");
273
if (MO.
isUse
())
/external/llvm/include/llvm/CodeGen/
MachineRegisterInfo.h
361
if ((!ReturnUses && op->
isUse
()) ||
393
while (Op && ((!ReturnUses && Op->
isUse
()) ||
MachineOperand.h
231
bool
isUse
() const {
277
return !isUndef() && (
isUse
() || getSubReg());
LiveIntervalAnalysis.h
76
static float getSpillWeight(bool isDef, bool
isUse
, unsigned loopDepth);
/external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp
94
if (!MO.isReg() || !MO.isImplicit() || MO.
isUse
())
104
(MI->getOperand(2).isReg() && MI->getOperand(2).
isUse
()) &&
Spiller.cpp
113
hasUse |= mi->getOperand(i).
isUse
();
130
if (mop.
isUse
() && !mi->isRegTiedToDefOperand(mopIdx)) {
TwoAddressInstructionPass.cpp
199
if (MO.
isUse
() && MOReg != SavedReg)
355
if (MO.
isUse
() && DI->second < LastUse)
381
if (MO.
isUse
() && DI->second > LastUseDist) {
459
if (!MO.isReg() || !MO.
isUse
() || MO.getReg() != Reg)
785
if (MO.
isUse
() && MO.isKill())
[
all
...]
RegAllocFast.cpp
215
if (MO.
isUse
() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
562
if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).
isUse
())
595
if (MO.
isUse
())
691
if (MO.
isUse
()) {
[
all
...]
TargetInstrInfoImpl.cpp
338
assert(MI->getOperand(Ops[i]).
isUse
() && "Folding load into def!");
413
if (MO.
isUse
()) {
445
if (MO.
isUse
())
DeadMachineInstructionElim.cpp
182
if (MO.isReg() && MO.
isUse
()) {
ScheduleDAGInstrs.h
79
if (!MO.isReg() || !MO.
isUse
())
MachineInstr.cpp
870
if (getOperand(OpIdx).
isUse
() && isRegTiedToDefOperand(OpIdx, &DefIdx))
897
if (!MO.isReg() || !MO.
isUse
())
929
if (MO.
isUse
()
[
all
...]
RegisterScavenging.cpp
163
if (MO.
isUse
()) {
189
if (MO.
isUse
()) {
CriticalAntiDepBreaker.cpp
235
if (MO.
isUse
() && Special) {
294
if (!MO.
isUse
()) continue;
588
if (MO.
isUse
() && TRI->regsOverlap(AntiDepReg, Reg)) {
MachineCSE.cpp
116
if (!MO.isReg() || !MO.
isUse
())
170
if (MO.
isUse
())
302
if (MO.isReg() && MO.
isUse
() &&
MachineSink.cpp
441
if (MO.
isUse
()) {
466
if (MO.
isUse
()) continue;
BranchFolding.cpp
150
if (!MO.isReg() || !MO.
isUse
())
[
all
...]
VirtRegRewriter.cpp
78
if (MO.
isUse
() && !MO.isUndef() &&
548
if (!MO.isReg() || !MO.
isUse
() || !MO.isKill() || MO.isUndef())
610
if (MO.
isUse
())
634
if (!MO.isReg() || !MO.
isUse
() || MO.isUndef())
695
assert(MO.
isUse
());
[
all
...]
PostRASchedulerList.cpp
480
if (!MO.isReg() || !MO.
isUse
()) continue;
516
if (!MO.isReg() || !MO.
isUse
() || MO.isUndef()) continue;
InlineSpiller.cpp
843
if (MO.isReg() && MO.
isUse
() && MO.getReg() == VirtReg.reg)
872
if (MO.
isUse
() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
[
all
...]
ProcessImplicitDefs.cpp
178
if (MOJ.isReg() && MOJ.
isUse
() && MOJ.getReg() == Reg)
RenderMachineFunction.cpp
563
if (i.
isUse
() || i.isDef()) {
568
if (i.
isUse
()) {
591
} else if (i.
isUse
() && mi->readsRegister(li->reg)) {
[
all
...]
MachineLICM.cpp
821
if (MO.
isUse
()) {
849
if (!MO.
isUse
())
[
all
...]
/external/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp
209
if (MO.
isUse
()) {
240
else if (MO.
isUse
())
/external/llvm/lib/Target/ARM/
Thumb2ITBlockPass.cpp
69
if (MO.
isUse
())
Completed in 3834 milliseconds
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