| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 184 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1));
217 if (Op1 && Op1->getOpcode() == Opcode) {
219 Value *B = Op1->getOperand(0);
220 Value *C = Op1->getOperand(1);
259 if (Op1 && Op1->getOpcode() == Opcode) {
261 Value *B = Op1->getOperand(0);
262 Value *C = Op1->getOperand(1);
280 if (Op0 && Op1 &
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/VMCore/ |
| Instructions.cpp | 61 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) {
62 if (Op1->getType() != Op2->getType())
69 VectorType *ET = dyn_cast<VectorType>(Op1->getType());
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 640 SDValue Op1 = basePtr.getOperand(1);
642 if (isa<ConstantSDNode>(Op1)) {
646 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
652 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
