| /external/llvm/lib/Target/ARM/ |
| ARMSubtarget.h | 122 /// that partially update CPSR and add false dependency on the previous
123 /// CPSR setting instruction.
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| ARMInstrThumb.td | 408 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
460 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
857 let isCommutable = 1, Uses = [CPSR] in
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| ARMBaseInstrInfo.cpp | 493 // FIXME: This confuses implicit_def with optional CPSR def.
501 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
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| ARMInstrInfo.td | 78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
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| ARMRegisterInfo.td | 184 def CPSR : ARMReg<0, "cpsr">;
349 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
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| ARMFastISel.cpp | 207 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
220 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
221 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
226 // Look to see if our OptionalDef is defining CPSR or CCR.
230 if (MO.getReg() == ARM::CPSR)
231 *CPSR = true;
254 // CPSR defs that need to be added before the remaining operands. See s_cc_out
267 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
268 bool CPSR = false
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| ARMInstrThumb2.td | 490 /// changed to modify CPSR.
607 /// instruction modifies the CPSR register.
610 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
611 let hasPostISelHook = 1, Defs = [CPSR] in {
619 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
624 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
632 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
639 let hasPostISelHook = 1, Defs = [CPSR] in {
645 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
651 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm
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| ARMBaseInstrInfo.h | 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
345 /// CPSR def operand.
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| ARMISelLowering.cpp | [all...] |
| ARMCodeEmitter.cpp | 818 // Encode S bit if MI modifies CPSR.
846 // Encode S bit if MI modifies CPSR.
871 // Encode S bit if MI modifies CPSR.
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| Thumb2InstrInfo.cpp | 574 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
592 NMI->definesRegister(ARM::CPSR))
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| README-Thumb.txt | 232 to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
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| /prebuilt/android-arm/gdbserver/ |
| gdbserver | |
| /external/valgrind/main/VEX/priv/ |
| guest_arm_defs.h | 80 they appear in the CPSR, viz bits 31:28 for N Z V C respectively.
116 /* Flags masks. Defines positions of flags bits in the CPSR. */
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| /ndk/docs/ |
| NDK-STACK.html | 26 I/DEBUG ( 31): ip 0000959c sp be956cc8 lr 00008403 pc 0000841e cpsr 60000030
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| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.c | 22 unsigned int cpsr; \
28 "mrs %1,cpsr;" \
29 : "=&r" (out), "=&r" (cpsr) \
33 printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
36 cpsr & 0xffff0000, \
37 ((1<<31) & cpsr) ? 'N' : ' ', \
38 ((1<<30) & cpsr) ? 'Z' : ' ', \
39 ((1<<29) & cpsr) ? 'C' : ' ', \
40 ((1<<28) & cpsr) ? 'V' : ' ' \
50 unsigned int cpsr; \
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| v6media.c | 21 unsigned int cpsr; \
32 "mrs %1,cpsr;" \
33 : "=&r" (out), "=&r" (cpsr) \
37 printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
40 cpsr & 0xffff0000, \
41 ((1<<31) & cpsr) ? 'N' : ' ', \
42 ((1<<30) & cpsr) ? 'Z' : ' ', \
43 ((1<<29) & cpsr) ? 'C' : ' ', \
44 ((1<<28) & cpsr) ? 'V' : ' ', \
45 ((1<<27) & cpsr) ? 'Q' : ' ',
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| /external/v8/src/arm/ |
| constants-arm.h | 281 CPSR = 0 << 22,
304 CPSR_c = CPSR | 1 << 16,
305 CPSR_x = CPSR | 1 << 17,
306 CPSR_s = CPSR | 1 << 18,
307 CPSR_f = CPSR | 1 << 19,
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| simulator-arm.h | 317 // There is currently no way to read the CPSR directly, and thus read the Q
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| /external/qemu/target-arm/ |
| machine.c | 126 /* Avoid mode switch when restoring CPSR. */
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| /sdk/emulator/qtools/ |
| armdis.cpp | 544 sprintf(ptr, "mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
573 cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val);
580 cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 673 O << "CPSR";
701 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
702 "Expect ARM CPSR register!");
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| /system/core/debuggerd/arm/ |
| machine.c | 353 " ip %08x sp %08x lr %08x pc %08x cpsr %08x\n",
|
| /external/qemu/ |
| gdbstub.c | 751 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
815 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
860 the FPA registers appear in between core integer regs and the CPSR.
886 /* CPSR */
922 /* CPSR */
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 562 // implicitly set CPSR. Since it's not represented in the encoding, the
563 // auto-generated decoder won't inject the CPSR operand. We need to fix
573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
682 I->setReg(ARM::CPSR);
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