| /external/llvm/lib/Target/X86/ |
| README-SSE.txt | 77 Think about doing i64 math in SSE regs on x86-32.
451 define i64 @ccosf(float %z.0, float %z.1) nounwind readonly {
454 %tmp20 = tail call i64 @ccoshf( float %tmp6, float %z.0 ) nounwind readonly
455 ret i64 %tmp20
457 declare i64 @ccoshf(float %z.0, float %z.1) nounwind readonly
492 <2 x i64> extract is substantially worse than <2 x f64>, even if the destination
516 to <2 x i64> ops being so bad.
865 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
874 %tmp19 = bitcast double %tmp18 to i64 ; <i64> [#uses=1
[all...] |
| X86ISelDAGToDAG.cpp | 661 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
723 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
[all...] |
| X86InstrArithmetic.td | 512 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
516 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
520 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
524 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
528 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
529 /// since the immediate fields of i64 instructions is a 32-bit sign extended
534 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
535 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
562 /// the 0x40 REX prefix. This is set for i64 types.
578 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| 2009-08-04-CoalescerBug.ll | 8 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
|
| /external/llvm/test/Transforms/PhaseOrdering/ |
| 2010-03-22-empty-baseclass.ll | 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
41 %10 = call i32 @puts(i8* getelementptr inbounds ([25 x i8]* @.str, i64 0, i64 0)) ; <i32> [#uses=0]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
[all...] |
| LegalizeTypesGeneric.cpp | 98 // Handle cases like i64 = BITCAST v1i64 on x86, where the operand
176 // <3 x i64> -> <6 x i32>.
276 // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
310 // For example <3 x i64> -> <6 x i32>.
|
| /external/clang/test/CodeGenCXX/ |
| visibility.cpp | 26 // CHECK: @_ZGVZN6Test193fooIiEEvvE1a = linkonce_odr global i64
28 // CHECK-HIDDEN: @_ZGVZN6Test193fooIiEEvvE1a = linkonce_odr hidden global i64
|
| /external/llvm/lib/Target/PTX/ |
| PTXISelDAGToDAG.cpp | 124 else if (Type == MVT::i64)
162 else if (Type == MVT::i64)
|
| PTXTargetMachine.cpp | 67 "e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
69 "e-p:64:64-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
|
| PTXInstrInfo.td | 625 //def : Pat<(i64 (anyext RegI16:$a)), (CVT_u64_u16 RegI16:$a)>;
626 //def : Pat<(i64 (anyext RegI32:$a)), (CVT_u64_u32 RegI32:$a)>;
[all...] |
| PTXRegisterInfo.td | 34 def RegI64 : RegisterClass<"PTX", [i64], 64, (add DUMMY_REG)>;
|
| PTXSelectionDAGInfo.cpp | 61 EVT PointerType = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
|
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.cpp | 115 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
160 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
|
| /external/valgrind/main/none/tests/amd64/ |
| rcl-amd64.c | 4 #define I64(C) "rcrq %%rbx\n" "rclq $" #C ",%%rax\n" "rclq %%rbx\n"
12 asm(I64(C) : "+a"(a), "+b"(b) : /* */); \
|
| /external/llvm/docs/ |
| LangRef.html | 516 %cast210 = <a href="#i_getelementptr">getelementptr</a> [13 x i8]* @.LC0, i64 0, i64 0 <i>; i8*</i>
[all...] |
| /external/chromium/base/win/ |
| scoped_variant.h | 100 void Set(int64 i64);
|
| /external/dbus/dbus/ |
| dbus-marshal-basic.h | 173 dbus_int64_t i64; /**< as int64 */ member in union:__anon5452
|
| /external/libyuv/files/source/ |
| rotate_neon.s | 267 vst1.i64 {d8, d9, d10, d11}, [r0]!
268 vst1.i64 {d12, d13, d14, d15}, [r0]!
274 vld1.i64 {d8, d9, d10, d11}, [r0]!
275 vld1.i64 {d12, d13, d14, d15}, [r0]!
|
| /external/llvm/include/llvm/Support/ |
| DataTypes.h.cmake | 164 # define INT64_C(C) C##i64
|
| DataTypes.h.in | 164 # define INT64_C(C) C##i64
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
238 // i64 conversions are done via library routines even when generating VFP
250 // i64 conversions are done via library routines even when generating VFP
549 // i64 operation support.
550 setOperationAction(ISD::MUL, MVT::i64, Expand);
563 setOperationAction(ISD::SRL, MVT::i64, Custom);
564 setOperationAction(ISD::SRA, MVT::i64, Custom);
627 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
628 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
629 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.h | 66 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; }
|
| /external/llvm/lib/Target/CellSPU/ |
| README.txt | 47 * i64 support (see i64operations.c test harness):
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 60 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; }
|
