| /external/llvm/test/CodeGen/X86/ |
| fold-pcmpeqd-2.ll | 18 %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 99 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
142 setOperationAction(ISD::SDIV, MVT::i64, Expand);
143 setOperationAction(ISD::SREM, MVT::i64, Expand);
144 setOperationAction(ISD::UDIV, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
157 setOperationAction(ISD::ROTL, MVT::i64, Expand);
163 setOperationAction(ISD::ROTR, MVT::i64, Expand);
236 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16;
[all...] |
| /cts/tests/tests/renderscript/src/android/renderscript/cts/ |
| AllocationTest.java | 127 createTypedHelper(Element.I64(mRS));
166 createSizedHelper(Element.I64(mRS));
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 241 MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
362 Reg = getX86SubSuperRegister(Reg, MVT::i64);
|
| /external/llvm/lib/Transforms/Instrumentation/ |
| GCOVProfiling.cpp | 532 // emit [(succs * preds) x i64*], logically [succ x [pred x i64*]].
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 26 // i64 and larger types when i64 is legal and the value has few bits set. It
|
| /external/llvm/test/CodeGen/Generic/ |
| APIntLoadStore.ll | 128 @i64_l = external global i64 ; <i64*> [#uses=1]
129 @i64_s = external global i64 ; <i64*> [#uses=1]
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 56 case MVT::i64: return "MVT::i64";
|
| /external/qemu/distrib/sdl-1.2.12/src/stdlib/ |
| SDL_string.c | 812 if ( SDL_strncmp(fmt, "I64", 3) == 0 ) {
1161 if ( SDL_strncmp(fmt, "I64", 3) == 0 ) {
[all...] |
| /ndk/sources/host-tools/make-3.81/ |
| readme.vms | 3 Changes are based on GNU make 3.80. Latest changes are for OpenVMS/I64
6 This version was tested on OpenVMS/I64 V8.2 (field test) with hp C
|
| /external/icu4c/common/ |
| putil.c | 160 int64_t i64; /* This must be defined first in order to allow the initialization to work. This is a C89 feature. */ member in union:__anon6099
344 return (UBool)((convertedNumber.i64 & U_INT64_MAX) > gInf.i64);
370 return (UBool)((convertedNumber.i64 & U_INT64_MAX) == gInf.i64);
[all...] |
| /external/llvm/docs/ |
| TestingGuide.html | 544 define void @inc4(i64* %p) {
548 %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1)
[all...] |
| /external/llvm/lib/VMCore/ |
| ConstantFold.cpp | [all...] |
| /external/llvm/include/llvm/ |
| Constants.h | 607 /// independent way (Note: the return type is an i64).
612 /// type is an i64).
617 /// target independent way (Note: the return type is an i64).
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2009-07-18-RewriterBug.ll | [all...] |
| vldlane.ll | 494 define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
497 %tmp63 = extractvalue [6 x i64] %b, 5
498 %tmp64 = zext i64 %tmp63 to i128
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2009-08-04-ScavengerAssert.ll | 10 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
|
| /external/clang/lib/Basic/ |
| TargetInfo.cpp | 67 "i64:64:64-f32:32:32-f64:64:64-n32";
|
| /external/clang/www/demo/ |
| index.cgi | 98 $input =~ s@\b(void|i8|i1|i16|i32|i64|float|double|type|label|opaque)\b@<span class="llvm_type">$1</span>@g;
|
| /external/flac/libFLAC/ |
| lpc.c | 289 if(sumo > 2147483647I64 || sumo < -2147483648I64)
820 if(sumo > 2147483647I64 || sumo < -2147483648I64)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetData.h | 158 /// i64 is not native on most 32-bit CPUs and i37 is not native on any known
|
| /external/llvm/lib/CodeGen/ |
| GCStrategy.cpp | 229 // libcalls upon lowering (e.g., div i64 on a 32-bit platform), so instead
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.td | 263 def Accu : RegisterClass<"BF", [i64], 64, (add A0, A1)>;
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 131 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 114 setOperationAction(ISD::MULHS, MVT::i64, Expand);
116 setOperationAction(ISD::MULHU, MVT::i64, Expand);
135 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
136 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
[all...] |
