| /external/llvm/lib/Target/X86/ |
| X86InstrCompiler.td | [all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 233 //! Emit the instruction sequence for i64 srl
753 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
756 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
775 if (Op0.getOpcode() == ISD::SRL)
789 } else if (Opc == ISD::SRL) {
[all...] |
| SPUISelLowering.cpp | 245 setOperationAction(ISD::SRL, MVT::i8, Custom);
250 setOperationAction(ISD::SRL, MVT::i64, Legal);
[all...] |
| /external/icu4c/config/ |
| icu-config.1.in | 8 .\" Modified by Steven R. Loomis <srl@jtcsv.com>.
|
| /external/icu4c/test/intltest/ |
| dadrfmt.cpp | 10 * 07/09/2007 srl Copied from dadrcoll.cpp
|
| dadrcal.cpp | 10 * 07/09/2007 srl Copied from dadrcoll.cpp
|
| /external/icu4c/tools/ |
| icu-svnprops-check.py | 80 # new additions 2007-dec-5 srl
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 177 srl(object, object, kPageSizeBits);
550 srl(rd, rs, 0);
552 srl(at, rs, rt.imm32_);
672 srl(rt, rt, 32 - size);
689 srl(t8, rt, pos + size);
697 srl(t8, t8, 32 - pos);
705 srl(t8, t8, 32 - size - pos);
844 srl(dest, scratch2, HeapNumber::kExponentShift);
876 srl(scratch, scratch, 1);
[all...] |
| disasm-mips.cc | 606 case SRL:
608 Format(instr, "srl 'rd, 'rt, 'sa");
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 70 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.td | 395 def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIC_SHT>;
398 def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>;
628 def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
629 "srl $dst, $src", [], IIC_ALU>;
751 def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>;
[all...] |
| MBlazeInstrFormats.td | 27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 602 SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
605 SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
606 SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
[all...] |
| AlphaISelDAGToDAG.cpp | 359 if (N->getOperand(0).getOpcode() == ISD::SRL &&
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 716 def : Pat<(srl G8RC:$rS, GPRC:$rB),
721 // SHL/SRL
724 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
[all...] |
| PPCInstrAltivec.td | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.td | 455 defm SRL : F3_12<"srl", 0b100110, srl>;
[all...] |
| /external/icu4c/common/ |
| umutex.c | 15 * 04/07/99 srl updated
|
| /external/icu4c/i18n/ |
| japancal.cpp | 10 * 05/16/2003 srl copied from buddhcal.cpp
|
| /external/libffi/src/mips/ |
| o32.S | 80 SRL t2, t0, 4 # shift our arg info
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 912 return SelectBinaryOp(I, ISD::SRL);
[all...] |
| /external/llvm/lib/TableGen/ |
| TGLexer.cpp | 465 .Case("srl", tgtok::XSRL)
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.td | 699 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
702 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha512-s390x.pl | 71 $SHR="srl"; # logical right shift
|
