| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| SelectionDAGBuilder.h | 385 void visit(unsigned Opcode, const User &I);
476 void visitBinary(const User &I, unsigned OpCode);
477 void visitShift(const User &I, unsigned Opcode);
|
| SelectionDAGISel.cpp | [all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| CodegenDriver.cpp | 88 switch (mir->dalvikInsn.opcode) {
134 switch (mir->dalvikInsn.opcode) {
178 Opcode opcode = mir->dalvikInsn.opcode; local
180 switch (opcode) {
208 static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpcode opcode,
212 insn->opcode = opcode;
247 TemplateOpcode opcode = TEMPLATE_MEM_OP_DECODE local
891 Opcode opcode = mir->dalvikInsn.opcode; local
1658 Opcode opcode = mir->dalvikInsn.opcode; local
1733 Opcode opcode = mir->dalvikInsn.opcode; local
2001 Opcode opcode = mir->dalvikInsn.opcode; local
2720 Opcode opcode = mir->dalvikInsn.opcode; local
2745 Opcode opcode = mir->dalvikInsn.opcode; local
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 601 unsigned Opcode = LU->getOpcode();
605 if (Opcode == Instruction::Add ||
606 Opcode == Instruction::Sub ||
607 Opcode == Instruction::And ||
608 Opcode == Instruction::Or ||
609 Opcode == Instruction::Mul) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 140 /// opcode.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86FastISel.cpp | 178 // Get opcode and regclass of the output for the given load instruction.
236 // Get opcode and regclass of the output for the given store instruction.
320 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
339 unsigned Opcode = Instruction::UserOp1;
346 Opcode = I->getOpcode();
350 Opcode = C->getOpcode();
360 switch (Opcode) {
599 unsigned Opcode = Instruction::UserOp1;
601 Opcode = I->getOpcode();
604 Opcode = C->getOpcode()
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| /dalvik/vm/compiler/ |
| SSATransformation.cpp | 489 phi->dalvikInsn.opcode = (Opcode)kMirOpPhi;
510 if (mir->dalvikInsn.opcode != (Opcode)kMirOpPhi)
|
| Dataflow.cpp | 25 * instructions, where extended opcode at the MIR level are appended
1593 Opcode opcode = insn->opcode; local
1594 int dfAttributes = dvmCompilerDataFlowAttributes[opcode];
1599 if ((int)opcode >= (int)kMirOpFirst) {
1600 if ((int)opcode == (int)kMirOpPhi) {
1604 sprintf(buffer, "Opcode %#x", opcode);
1608 strcpy(buffer, dexGetOpcodeName(opcode));
1695 int opcode = insn->opcode; local
[all...] |
| /external/llvm/lib/MC/ |
| MCExpr.cpp | 73 default: assert(0 && "Invalid opcode!");
94 default: assert(0 && "Invalid opcode!");
145 const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS,
150 const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr,
|
| /dalvik/vm/compiler/codegen/arm/FP/ |
| Thumb2VFP.cpp | 28 switch (mir->dalvikInsn.opcode) {
70 switch (mir->dalvikInsn.opcode) {
113 Opcode opcode = mir->dalvikInsn.opcode; local
122 switch (opcode) {
218 switch(mir->dalvikInsn.opcode) {
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 193 /// getOpcode - Returns the opcode of this MachineInstr.
195 int getOpcode() const { return MCID->Opcode; }
243 /// opcode and same operands as) the specified instruction.
529 /// setDesc - Replace the instruction descriptor (thus opcode) of
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 109 // third operand encodes the shift opcode and the imm if a reg isn't present.
577 AMSubMode getLoadStoreMultipleSubMode(int Opcode);
|
| /external/llvm/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 125 /// version and return the Opcode since the two have the same Asm format string.
145 // Keeps track of the last opcode in the filtered bucket.
285 void insnWithID(insn_t &Insn, unsigned Opcode) const {
286 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
293 const std::string &nameWithID(unsigned Opcode) const {
294 return AllInstructions[Opcode]->TheDef->getName();
328 // decoded bits in order to verify that the instruction matches the Opcode.
682 // decoded bits in order to verify that the instruction matches the Opcode.
[all...] |
| DAGISelMatcher.h | 59 CheckOpcode, // Fail if not opcode.
60 SwitchOpcode, // Dispatch based on opcode.
447 /// specified opcode, if not it fails to match.
449 const SDNodeInfo &Opcode;
451 CheckOpcodeMatcher(const SDNodeInfo &opcode)
452 : Matcher(CheckOpcode), Opcode(opcode) {}
454 const SDNodeInfo &getOpcode() const { return Opcode; }
469 /// SwitchOpcodeMatcher - Switch based on the current node's opcode, dispatching
470 /// to one matcher per opcode. If the opcode doesn't match any of the cases
[all...] |
| /external/webkit/Source/JavaScriptCore/ |
| Android.mk | 40 bytecode/Opcode.cpp \
|
| /external/llvm/examples/Kaleidoscope/Chapter7/ |
| toy.cpp | 134 char Opcode;
137 UnaryExprAST(char opcode, ExprAST *operand)
138 : Opcode(opcode), Operand(operand) {}
640 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 383 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
392 // VEX_R: opcode externsion equivalent to REX.R in
414 // VEX_W: opcode specific (use like REX.W, or used for
415 // opcode extension, or ignored, depending on the opcode byte)
421 // 0b00001: implied 0F leading opcode
422 // 0b00010: implied 0F 38 leading opcode bytes
423 // 0b00011: implied 0F 3A leading opcode bytes
439 // VEX_PP: opcode extension providing equivalent
449 // Encode the operand size opcode prefix as needed
[all...] |
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | 828 MCBinaryExpr::Opcode &Kind) {
911 MCBinaryExpr::Opcode Kind = MCBinaryExpr::Add;
927 MCBinaryExpr::Opcode Dummy;
[all...] |
| /external/llvm/lib/Target/CBackend/ |
| CBackend.cpp | 187 void writeOperandWithCast(Value* Operand, unsigned Opcode);
212 void printCast(unsigned opcode, Type *SrcTy, Type *DstTy);
214 void printConstantWithCast(Constant *CPV, unsigned Opcode);
715 llvm_unreachable("Invalid cast opcode");
745 llvm_unreachable("Invalid cast opcode");
857 default: llvm_unreachable("Illegal opcode here!");
[all...] |
| /external/llvm/lib/VMCore/ |
| Constants.cpp | 1289 Instruction::CastOps opcode = local
[all...] |
| /dalvik/vm/analysis/ |
| VfyBasicBlock.cpp | 409 Opcode opcode = dexOpcodeFromCodeUnit(meth->insns[idx]); local
410 OpcodeFlags opFlags = dexGetFlagsFromOpcode(opcode);
445 } else if (opcode == OP_NOP && isDataChunk(meth->insns[nextIdx])) {
|
| /external/javassist/src/main/javassist/bytecode/ |
| CodeAttribute.java | 35 public class CodeAttribute extends AttributeInfo implements Opcode {
444 code[where] = (byte)Opcode.LDC_W;
487 int opcode = ci.byteAt(index); local
488 if (opcode < ILOAD)
490 else if (opcode < IASTORE) {
491 if (opcode < ILOAD_0) {
493 shiftIndex8(ci, index, opcode, lessThan, delta);
495 else if (opcode < IALOAD) {
497 shiftIndex0(ci, index, opcode, lessThan, delta, ILOAD_0, ILOAD);
499 else if (opcode < ISTORE
[all...] |
