1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMSubtarget.h" 15 #include "ARMBaseRegisterInfo.h" 16 #include "llvm/GlobalValue.h" 17 #include "llvm/Target/TargetSubtargetInfo.h" 18 #include "llvm/Support/CommandLine.h" 19 #include "llvm/ADT/SmallVector.h" 20 21 #define GET_SUBTARGETINFO_TARGET_DESC 22 #define GET_SUBTARGETINFO_CTOR 23 #include "ARMGenSubtargetInfo.inc" 24 25 using namespace llvm; 26 27 static cl::opt<bool> 28 ReserveR9("arm-reserve-r9", cl::Hidden, 29 cl::desc("Reserve R9, making it unavailable as GPR")); 30 31 static cl::opt<bool> 32 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden); 33 34 static cl::opt<bool> 35 StrictAlign("arm-strict-align", cl::Hidden, 36 cl::desc("Disallow all unaligned memory accesses")); 37 38 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, 39 const std::string &FS) 40 : ARMGenSubtargetInfo(TT, CPU, FS) 41 , ARMProcFamily(Others) 42 , HasV4TOps(false) 43 , HasV5TOps(false) 44 , HasV5TEOps(false) 45 , HasV6Ops(false) 46 , HasV6T2Ops(false) 47 , HasV7Ops(false) 48 , HasVFPv2(false) 49 , HasVFPv3(false) 50 , HasNEON(false) 51 , UseNEONForSinglePrecisionFP(false) 52 , SlowFPVMLx(false) 53 , HasVMLxForwarding(false) 54 , SlowFPBrcc(false) 55 , InThumbMode(false) 56 , HasThumb2(false) 57 , IsMClass(false) 58 , NoARM(false) 59 , PostRAScheduler(false) 60 , IsR9Reserved(ReserveR9) 61 , UseMovt(false) 62 , SupportsTailCall(false) 63 , HasFP16(false) 64 , HasD16(false) 65 , HasHardwareDivide(false) 66 , HasT2ExtractPack(false) 67 , HasDataBarrier(false) 68 , Pref32BitThumb(false) 69 , AvoidCPSRPartialUpdate(false) 70 , HasMPExtension(false) 71 , FPOnlySP(false) 72 , AllowsUnalignedMem(false) 73 , Thumb2DSP(false) 74 , stackAlignment(4) 75 , CPUString(CPU) 76 , TargetTriple(TT) 77 , TargetABI(ARM_ABI_APCS) { 78 // Determine default and user specified characteristics 79 if (CPUString.empty()) 80 CPUString = "generic"; 81 82 // Insert the architecture feature derived from the target triple into the 83 // feature string. This is important for setting features that are implied 84 // based on the architecture version. 85 std::string ArchFS = ARM_MC::ParseARMTriple(TT); 86 if (!FS.empty()) { 87 if (!ArchFS.empty()) 88 ArchFS = ArchFS + "," + FS; 89 else 90 ArchFS = FS; 91 } 92 ParseSubtargetFeatures(CPUString, ArchFS); 93 94 // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a 95 // ARM version or CPU and then remove this. 96 if (!HasV6T2Ops && hasThumb2()) 97 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; 98 99 // Initialize scheduling itinerary for the specified CPU. 100 InstrItins = getInstrItineraryForCPU(CPUString); 101 102 // After parsing Itineraries, set ItinData.IssueWidth. 103 computeIssueWidth(); 104 105 if (TT.find("eabi") != std::string::npos) 106 TargetABI = ARM_ABI_AAPCS; 107 108 if (isAAPCS_ABI()) 109 stackAlignment = 8; 110 111 if (!isTargetDarwin()) 112 UseMovt = hasV6T2Ops(); 113 else { 114 IsR9Reserved = ReserveR9 | !HasV6Ops; 115 UseMovt = DarwinUseMOVT && hasV6T2Ops(); 116 const Triple &T = getTargetTriple(); 117 SupportsTailCall = T.getOS() == Triple::IOS && !T.isOSVersionLT(5, 0); 118 } 119 120 if (!isThumb() || hasThumb2()) 121 PostRAScheduler = true; 122 123 // v6+ may or may not support unaligned mem access depending on the system 124 // configuration. 125 if (!StrictAlign && hasV6Ops() && isTargetDarwin()) 126 AllowsUnalignedMem = true; 127 } 128 129 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol. 130 bool 131 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, 132 Reloc::Model RelocM) const { 133 if (RelocM == Reloc::Static) 134 return false; 135 136 // Materializable GVs (in JIT lazy compilation mode) do not require an extra 137 // load from stub. 138 bool isDecl = GV->hasAvailableExternallyLinkage(); 139 if (GV->isDeclaration() && !GV->isMaterializable()) 140 isDecl = true; 141 142 if (!isTargetDarwin()) { 143 // Extra load is needed for all externally visible. 144 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility()) 145 return false; 146 return true; 147 } else { 148 if (RelocM == Reloc::PIC_) { 149 // If this is a strong reference to a definition, it is definitely not 150 // through a stub. 151 if (!isDecl && !GV->isWeakForLinker()) 152 return false; 153 154 // Unless we have a symbol with hidden visibility, we have to go through a 155 // normal $non_lazy_ptr stub because this symbol might be resolved late. 156 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 157 return true; 158 159 // If symbol visibility is hidden, we have a stub for common symbol 160 // references and external declarations. 161 if (isDecl || GV->hasCommonLinkage()) 162 // Hidden $non_lazy_ptr reference. 163 return true; 164 165 return false; 166 } else { 167 // If this is a strong reference to a definition, it is definitely not 168 // through a stub. 169 if (!isDecl && !GV->isWeakForLinker()) 170 return false; 171 172 // Unless we have a symbol with hidden visibility, we have to go through a 173 // normal $non_lazy_ptr stub because this symbol might be resolved late. 174 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference. 175 return true; 176 } 177 } 178 179 return false; 180 } 181 182 unsigned ARMSubtarget::getMispredictionPenalty() const { 183 // If we have a reasonable estimate of the pipeline depth, then we can 184 // estimate the penalty of a misprediction based on that. 185 if (isCortexA8()) 186 return 13; 187 else if (isCortexA9()) 188 return 8; 189 190 // Otherwise, just return a sensible default. 191 return 10; 192 } 193 194 void ARMSubtarget::computeIssueWidth() { 195 unsigned allStage1Units = 0; 196 for (const InstrItinerary *itin = InstrItins.Itineraries; 197 itin->FirstStage != ~0U; ++itin) { 198 const InstrStage *IS = InstrItins.Stages + itin->FirstStage; 199 allStage1Units |= IS->getUnits(); 200 } 201 InstrItins.IssueWidth = 0; 202 while (allStage1Units) { 203 ++InstrItins.IssueWidth; 204 // clear the lowest bit 205 allStage1Units ^= allStage1Units & ~(allStage1Units - 1); 206 } 207 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); 208 } 209 210 bool ARMSubtarget::enablePostRAScheduler( 211 CodeGenOpt::Level OptLevel, 212 TargetSubtargetInfo::AntiDepBreakMode& Mode, 213 RegClassVector& CriticalPathRCs) const { 214 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 215 CriticalPathRCs.clear(); 216 CriticalPathRCs.push_back(&ARM::GPRRegClass); 217 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; 218 } 219
