1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class prints an ARM MCInst to a .s file. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "asm-printer" 15 #include "ARMInstPrinter.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "MCTargetDesc/ARMAddressingModes.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCAsmInfo.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/Support/raw_ostream.h" 23 using namespace llvm; 24 25 #define GET_INSTRUCTION_NAME 26 #include "ARMGenAsmWriter.inc" 27 28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. 29 /// 30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0. 31 static unsigned translateShiftImm(unsigned imm) { 32 if (imm == 0) 33 return 32; 34 return imm; 35 } 36 37 38 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, 39 const MCSubtargetInfo &STI) : 40 MCInstPrinter(MAI) { 41 // Initialize the set of available features. 42 setAvailableFeatures(STI.getFeatureBits()); 43 } 44 45 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const { 46 return getInstructionName(Opcode); 47 } 48 49 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 50 OS << getRegisterName(RegNo); 51 } 52 53 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 54 StringRef Annot) { 55 unsigned Opcode = MI->getOpcode(); 56 57 // Check for MOVs and print canonical forms, instead. 58 if (Opcode == ARM::MOVsr) { 59 // FIXME: Thumb variants? 60 const MCOperand &Dst = MI->getOperand(0); 61 const MCOperand &MO1 = MI->getOperand(1); 62 const MCOperand &MO2 = MI->getOperand(2); 63 const MCOperand &MO3 = MI->getOperand(3); 64 65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 66 printSBitModifierOperand(MI, 6, O); 67 printPredicateOperand(MI, 4, O); 68 69 O << '\t' << getRegisterName(Dst.getReg()) 70 << ", " << getRegisterName(MO1.getReg()); 71 72 O << ", " << getRegisterName(MO2.getReg()); 73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 74 printAnnotation(O, Annot); 75 return; 76 } 77 78 if (Opcode == ARM::MOVsi) { 79 // FIXME: Thumb variants? 80 const MCOperand &Dst = MI->getOperand(0); 81 const MCOperand &MO1 = MI->getOperand(1); 82 const MCOperand &MO2 = MI->getOperand(2); 83 84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 85 printSBitModifierOperand(MI, 5, O); 86 printPredicateOperand(MI, 3, O); 87 88 O << '\t' << getRegisterName(Dst.getReg()) 89 << ", " << getRegisterName(MO1.getReg()); 90 91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 92 printAnnotation(O, Annot); 93 return; 94 } 95 96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 97 printAnnotation(O, Annot); 98 return; 99 } 100 101 102 // A8.6.123 PUSH 103 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) && 104 MI->getOperand(0).getReg() == ARM::SP) { 105 O << '\t' << "push"; 106 printPredicateOperand(MI, 2, O); 107 if (Opcode == ARM::t2STMDB_UPD) 108 O << ".w"; 109 O << '\t'; 110 printRegisterList(MI, 4, O); 111 printAnnotation(O, Annot); 112 return; 113 } 114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && 115 MI->getOperand(3).getImm() == -4) { 116 O << '\t' << "push"; 117 printPredicateOperand(MI, 4, O); 118 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; 119 printAnnotation(O, Annot); 120 return; 121 } 122 123 // A8.6.122 POP 124 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) && 125 MI->getOperand(0).getReg() == ARM::SP) { 126 O << '\t' << "pop"; 127 printPredicateOperand(MI, 2, O); 128 if (Opcode == ARM::t2LDMIA_UPD) 129 O << ".w"; 130 O << '\t'; 131 printRegisterList(MI, 4, O); 132 printAnnotation(O, Annot); 133 return; 134 } 135 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP && 136 MI->getOperand(4).getImm() == 4) { 137 O << '\t' << "pop"; 138 printPredicateOperand(MI, 5, O); 139 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}"; 140 printAnnotation(O, Annot); 141 return; 142 } 143 144 145 // A8.6.355 VPUSH 146 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) && 147 MI->getOperand(0).getReg() == ARM::SP) { 148 O << '\t' << "vpush"; 149 printPredicateOperand(MI, 2, O); 150 O << '\t'; 151 printRegisterList(MI, 4, O); 152 printAnnotation(O, Annot); 153 return; 154 } 155 156 // A8.6.354 VPOP 157 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) && 158 MI->getOperand(0).getReg() == ARM::SP) { 159 O << '\t' << "vpop"; 160 printPredicateOperand(MI, 2, O); 161 O << '\t'; 162 printRegisterList(MI, 4, O); 163 printAnnotation(O, Annot); 164 return; 165 } 166 167 if (Opcode == ARM::tLDMIA) { 168 bool Writeback = true; 169 unsigned BaseReg = MI->getOperand(0).getReg(); 170 for (unsigned i = 3; i < MI->getNumOperands(); ++i) { 171 if (MI->getOperand(i).getReg() == BaseReg) 172 Writeback = false; 173 } 174 175 O << "\tldm"; 176 177 printPredicateOperand(MI, 1, O); 178 O << '\t' << getRegisterName(BaseReg); 179 if (Writeback) O << "!"; 180 O << ", "; 181 printRegisterList(MI, 3, O); 182 printAnnotation(O, Annot); 183 return; 184 } 185 186 // Thumb1 NOP 187 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 && 188 MI->getOperand(1).getReg() == ARM::R8) { 189 O << "\tnop"; 190 printPredicateOperand(MI, 2, O); 191 printAnnotation(O, Annot); 192 return; 193 } 194 195 printInstruction(MI, O); 196 printAnnotation(O, Annot); 197 } 198 199 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 200 raw_ostream &O) { 201 const MCOperand &Op = MI->getOperand(OpNo); 202 if (Op.isReg()) { 203 unsigned Reg = Op.getReg(); 204 O << getRegisterName(Reg); 205 } else if (Op.isImm()) { 206 O << '#' << Op.getImm(); 207 } else { 208 assert(Op.isExpr() && "unknown operand kind in printOperand"); 209 // If a symbolic branch target was added as a constant expression then print 210 // that address in hex. 211 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 212 int64_t Address; 213 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) { 214 O << "0x"; 215 O.write_hex(Address); 216 } 217 else { 218 // Otherwise, just print the expression. 219 O << *Op.getExpr(); 220 } 221 } 222 } 223 224 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, 225 raw_ostream &O) { 226 const MCOperand &MO1 = MI->getOperand(OpNum); 227 if (MO1.isExpr()) 228 O << *MO1.getExpr(); 229 else if (MO1.isImm()) 230 O << "[pc, #" << MO1.getImm() << "]"; 231 else 232 llvm_unreachable("Unknown LDR label operand?"); 233 } 234 235 // so_reg is a 4-operand unit corresponding to register forms of the A5.1 236 // "Addressing Mode 1 - Data-processing operands" forms. This includes: 237 // REG 0 0 - e.g. R5 238 // REG REG 0,SH_OPC - e.g. R5, ROR R3 239 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 240 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, 241 raw_ostream &O) { 242 const MCOperand &MO1 = MI->getOperand(OpNum); 243 const MCOperand &MO2 = MI->getOperand(OpNum+1); 244 const MCOperand &MO3 = MI->getOperand(OpNum+2); 245 246 O << getRegisterName(MO1.getReg()); 247 248 // Print the shift opc. 249 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); 250 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 251 if (ShOpc == ARM_AM::rrx) 252 return; 253 254 O << ' ' << getRegisterName(MO2.getReg()); 255 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 256 } 257 258 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, 259 raw_ostream &O) { 260 const MCOperand &MO1 = MI->getOperand(OpNum); 261 const MCOperand &MO2 = MI->getOperand(OpNum+1); 262 263 O << getRegisterName(MO1.getReg()); 264 265 // Print the shift opc. 266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); 267 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 268 if (ShOpc == ARM_AM::rrx) 269 return; 270 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 271 } 272 273 274 //===--------------------------------------------------------------------===// 275 // Addressing Mode #2 276 //===--------------------------------------------------------------------===// 277 278 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 279 raw_ostream &O) { 280 const MCOperand &MO1 = MI->getOperand(Op); 281 const MCOperand &MO2 = MI->getOperand(Op+1); 282 const MCOperand &MO3 = MI->getOperand(Op+2); 283 284 O << "[" << getRegisterName(MO1.getReg()); 285 286 if (!MO2.getReg()) { 287 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0. 288 O << ", #" 289 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 290 << ARM_AM::getAM2Offset(MO3.getImm()); 291 O << "]"; 292 return; 293 } 294 295 O << ", " 296 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 297 << getRegisterName(MO2.getReg()); 298 299 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) 300 O << ", " 301 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm())) 302 << " #" << ShImm; 303 O << "]"; 304 } 305 306 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op, 307 raw_ostream &O) { 308 const MCOperand &MO1 = MI->getOperand(Op); 309 const MCOperand &MO2 = MI->getOperand(Op+1); 310 const MCOperand &MO3 = MI->getOperand(Op+2); 311 312 O << "[" << getRegisterName(MO1.getReg()) << "], "; 313 314 if (!MO2.getReg()) { 315 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm()); 316 O << '#' 317 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 318 << ImmOffs; 319 return; 320 } 321 322 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) 323 << getRegisterName(MO2.getReg()); 324 325 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) 326 O << ", " 327 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm())) 328 << " #" << ShImm; 329 } 330 331 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op, 332 raw_ostream &O) { 333 const MCOperand &MO1 = MI->getOperand(Op); 334 const MCOperand &MO2 = MI->getOperand(Op+1); 335 O << "[" << getRegisterName(MO1.getReg()) << ", " 336 << getRegisterName(MO2.getReg()) << "]"; 337 } 338 339 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op, 340 raw_ostream &O) { 341 const MCOperand &MO1 = MI->getOperand(Op); 342 const MCOperand &MO2 = MI->getOperand(Op+1); 343 O << "[" << getRegisterName(MO1.getReg()) << ", " 344 << getRegisterName(MO2.getReg()) << ", lsl #1]"; 345 } 346 347 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, 348 raw_ostream &O) { 349 const MCOperand &MO1 = MI->getOperand(Op); 350 351 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 352 printOperand(MI, Op, O); 353 return; 354 } 355 356 const MCOperand &MO3 = MI->getOperand(Op+2); 357 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); 358 359 if (IdxMode == ARMII::IndexModePost) { 360 printAM2PostIndexOp(MI, Op, O); 361 return; 362 } 363 printAM2PreOrOffsetIndexOp(MI, Op, O); 364 } 365 366 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, 367 unsigned OpNum, 368 raw_ostream &O) { 369 const MCOperand &MO1 = MI->getOperand(OpNum); 370 const MCOperand &MO2 = MI->getOperand(OpNum+1); 371 372 if (!MO1.getReg()) { 373 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); 374 O << '#' 375 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 376 << ImmOffs; 377 return; 378 } 379 380 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) 381 << getRegisterName(MO1.getReg()); 382 383 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm())) 384 O << ", " 385 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm())) 386 << " #" << ShImm; 387 } 388 389 //===--------------------------------------------------------------------===// 390 // Addressing Mode #3 391 //===--------------------------------------------------------------------===// 392 393 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op, 394 raw_ostream &O) { 395 const MCOperand &MO1 = MI->getOperand(Op); 396 const MCOperand &MO2 = MI->getOperand(Op+1); 397 const MCOperand &MO3 = MI->getOperand(Op+2); 398 399 O << "[" << getRegisterName(MO1.getReg()) << "], "; 400 401 if (MO2.getReg()) { 402 O << (char)ARM_AM::getAM3Op(MO3.getImm()) 403 << getRegisterName(MO2.getReg()); 404 return; 405 } 406 407 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 408 O << '#' 409 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 410 << ImmOffs; 411 } 412 413 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, 414 raw_ostream &O) { 415 const MCOperand &MO1 = MI->getOperand(Op); 416 const MCOperand &MO2 = MI->getOperand(Op+1); 417 const MCOperand &MO3 = MI->getOperand(Op+2); 418 419 O << '[' << getRegisterName(MO1.getReg()); 420 421 if (MO2.getReg()) { 422 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 423 << getRegisterName(MO2.getReg()) << ']'; 424 return; 425 } 426 427 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) 428 O << ", #" 429 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) 430 << ImmOffs; 431 O << ']'; 432 } 433 434 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op, 435 raw_ostream &O) { 436 const MCOperand &MO3 = MI->getOperand(Op+2); 437 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm()); 438 439 if (IdxMode == ARMII::IndexModePost) { 440 printAM3PostIndexOp(MI, Op, O); 441 return; 442 } 443 printAM3PreOrOffsetIndexOp(MI, Op, O); 444 } 445 446 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, 447 unsigned OpNum, 448 raw_ostream &O) { 449 const MCOperand &MO1 = MI->getOperand(OpNum); 450 const MCOperand &MO2 = MI->getOperand(OpNum+1); 451 452 if (MO1.getReg()) { 453 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) 454 << getRegisterName(MO1.getReg()); 455 return; 456 } 457 458 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); 459 O << '#' 460 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) 461 << ImmOffs; 462 } 463 464 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, 465 unsigned OpNum, 466 raw_ostream &O) { 467 const MCOperand &MO = MI->getOperand(OpNum); 468 unsigned Imm = MO.getImm(); 469 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff); 470 } 471 472 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, 473 raw_ostream &O) { 474 const MCOperand &MO1 = MI->getOperand(OpNum); 475 const MCOperand &MO2 = MI->getOperand(OpNum+1); 476 477 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg()); 478 } 479 480 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, 481 unsigned OpNum, 482 raw_ostream &O) { 483 const MCOperand &MO = MI->getOperand(OpNum); 484 unsigned Imm = MO.getImm(); 485 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2); 486 } 487 488 489 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, 490 raw_ostream &O) { 491 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) 492 .getImm()); 493 O << ARM_AM::getAMSubModeStr(Mode); 494 } 495 496 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, 497 raw_ostream &O) { 498 const MCOperand &MO1 = MI->getOperand(OpNum); 499 const MCOperand &MO2 = MI->getOperand(OpNum+1); 500 501 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 502 printOperand(MI, OpNum, O); 503 return; 504 } 505 506 O << "[" << getRegisterName(MO1.getReg()); 507 508 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 509 unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); 510 if (ImmOffs || Op == ARM_AM::sub) { 511 O << ", #" 512 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) 513 << ImmOffs * 4; 514 } 515 O << "]"; 516 } 517 518 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, 519 raw_ostream &O) { 520 const MCOperand &MO1 = MI->getOperand(OpNum); 521 const MCOperand &MO2 = MI->getOperand(OpNum+1); 522 523 O << "[" << getRegisterName(MO1.getReg()); 524 if (MO2.getImm()) { 525 // FIXME: Both darwin as and GNU as violate ARM docs here. 526 O << ", :" << (MO2.getImm() << 3); 527 } 528 O << "]"; 529 } 530 531 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum, 532 raw_ostream &O) { 533 const MCOperand &MO1 = MI->getOperand(OpNum); 534 O << "[" << getRegisterName(MO1.getReg()) << "]"; 535 } 536 537 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, 538 unsigned OpNum, 539 raw_ostream &O) { 540 const MCOperand &MO = MI->getOperand(OpNum); 541 if (MO.getReg() == 0) 542 O << "!"; 543 else 544 O << ", " << getRegisterName(MO.getReg()); 545 } 546 547 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, 548 unsigned OpNum, 549 raw_ostream &O) { 550 const MCOperand &MO = MI->getOperand(OpNum); 551 uint32_t v = ~MO.getImm(); 552 int32_t lsb = CountTrailingZeros_32(v); 553 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; 554 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); 555 O << '#' << lsb << ", #" << width; 556 } 557 558 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, 559 raw_ostream &O) { 560 unsigned val = MI->getOperand(OpNum).getImm(); 561 O << ARM_MB::MemBOptToString(val); 562 } 563 564 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum, 565 raw_ostream &O) { 566 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); 567 bool isASR = (ShiftOp & (1 << 5)) != 0; 568 unsigned Amt = ShiftOp & 0x1f; 569 if (isASR) 570 O << ", asr #" << (Amt == 0 ? 32 : Amt); 571 else if (Amt) 572 O << ", lsl #" << Amt; 573 } 574 575 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, 576 raw_ostream &O) { 577 unsigned Imm = MI->getOperand(OpNum).getImm(); 578 if (Imm == 0) 579 return; 580 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); 581 O << ", lsl #" << Imm; 582 } 583 584 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, 585 raw_ostream &O) { 586 unsigned Imm = MI->getOperand(OpNum).getImm(); 587 // A shift amount of 32 is encoded as 0. 588 if (Imm == 0) 589 Imm = 32; 590 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); 591 O << ", asr #" << Imm; 592 } 593 594 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, 595 raw_ostream &O) { 596 O << "{"; 597 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { 598 if (i != OpNum) O << ", "; 599 O << getRegisterName(MI->getOperand(i).getReg()); 600 } 601 O << "}"; 602 } 603 604 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, 605 raw_ostream &O) { 606 const MCOperand &Op = MI->getOperand(OpNum); 607 if (Op.getImm()) 608 O << "be"; 609 else 610 O << "le"; 611 } 612 613 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum, 614 raw_ostream &O) { 615 const MCOperand &Op = MI->getOperand(OpNum); 616 O << ARM_PROC::IModToString(Op.getImm()); 617 } 618 619 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum, 620 raw_ostream &O) { 621 const MCOperand &Op = MI->getOperand(OpNum); 622 unsigned IFlags = Op.getImm(); 623 for (int i=2; i >= 0; --i) 624 if (IFlags & (1 << i)) 625 O << ARM_PROC::IFlagsToString(1 << i); 626 627 if (IFlags == 0) 628 O << "none"; 629 } 630 631 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, 632 raw_ostream &O) { 633 const MCOperand &Op = MI->getOperand(OpNum); 634 unsigned SpecRegRBit = Op.getImm() >> 4; 635 unsigned Mask = Op.getImm() & 0xf; 636 637 if (getAvailableFeatures() & ARM::FeatureMClass) { 638 switch (Op.getImm()) { 639 default: assert(0 && "Unexpected mask value!"); 640 case 0: O << "apsr"; return; 641 case 1: O << "iapsr"; return; 642 case 2: O << "eapsr"; return; 643 case 3: O << "xpsr"; return; 644 case 5: O << "ipsr"; return; 645 case 6: O << "epsr"; return; 646 case 7: O << "iepsr"; return; 647 case 8: O << "msp"; return; 648 case 9: O << "psp"; return; 649 case 16: O << "primask"; return; 650 case 17: O << "basepri"; return; 651 case 18: O << "basepri_max"; return; 652 case 19: O << "faultmask"; return; 653 case 20: O << "control"; return; 654 } 655 } 656 657 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as 658 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. 659 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { 660 O << "APSR_"; 661 switch (Mask) { 662 default: assert(0); 663 case 4: O << "g"; return; 664 case 8: O << "nzcvq"; return; 665 case 12: O << "nzcvqg"; return; 666 } 667 llvm_unreachable("Unexpected mask value!"); 668 } 669 670 if (SpecRegRBit) 671 O << "SPSR"; 672 else 673 O << "CPSR"; 674 675 if (Mask) { 676 O << '_'; 677 if (Mask & 8) O << 'f'; 678 if (Mask & 4) O << 's'; 679 if (Mask & 2) O << 'x'; 680 if (Mask & 1) O << 'c'; 681 } 682 } 683 684 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, 685 raw_ostream &O) { 686 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 687 if (CC != ARMCC::AL) 688 O << ARMCondCodeToString(CC); 689 } 690 691 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, 692 unsigned OpNum, 693 raw_ostream &O) { 694 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); 695 O << ARMCondCodeToString(CC); 696 } 697 698 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, 699 raw_ostream &O) { 700 if (MI->getOperand(OpNum).getReg()) { 701 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && 702 "Expect ARM CPSR register!"); 703 O << 's'; 704 } 705 } 706 707 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, 708 raw_ostream &O) { 709 O << MI->getOperand(OpNum).getImm(); 710 } 711 712 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, 713 raw_ostream &O) { 714 O << "p" << MI->getOperand(OpNum).getImm(); 715 } 716 717 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, 718 raw_ostream &O) { 719 O << "c" << MI->getOperand(OpNum).getImm(); 720 } 721 722 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum, 723 raw_ostream &O) { 724 O << "{" << MI->getOperand(OpNum).getImm() << "}"; 725 } 726 727 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, 728 raw_ostream &O) { 729 llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); 730 } 731 732 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, 733 raw_ostream &O) { 734 O << "#" << MI->getOperand(OpNum).getImm() * 4; 735 } 736 737 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, 738 raw_ostream &O) { 739 unsigned Imm = MI->getOperand(OpNum).getImm(); 740 O << "#" << (Imm == 0 ? 32 : Imm); 741 } 742 743 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, 744 raw_ostream &O) { 745 // (3 - the number of trailing zeros) is the number of then / else. 746 unsigned Mask = MI->getOperand(OpNum).getImm(); 747 unsigned CondBit0 = Mask >> 4 & 1; 748 unsigned NumTZ = CountTrailingZeros_32(Mask); 749 assert(NumTZ <= 3 && "Invalid IT mask!"); 750 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 751 bool T = ((Mask >> Pos) & 1) == CondBit0; 752 if (T) 753 O << 't'; 754 else 755 O << 'e'; 756 } 757 } 758 759 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, 760 raw_ostream &O) { 761 const MCOperand &MO1 = MI->getOperand(Op); 762 const MCOperand &MO2 = MI->getOperand(Op + 1); 763 764 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 765 printOperand(MI, Op, O); 766 return; 767 } 768 769 O << "[" << getRegisterName(MO1.getReg()); 770 if (unsigned RegNum = MO2.getReg()) 771 O << ", " << getRegisterName(RegNum); 772 O << "]"; 773 } 774 775 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, 776 unsigned Op, 777 raw_ostream &O, 778 unsigned Scale) { 779 const MCOperand &MO1 = MI->getOperand(Op); 780 const MCOperand &MO2 = MI->getOperand(Op + 1); 781 782 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 783 printOperand(MI, Op, O); 784 return; 785 } 786 787 O << "[" << getRegisterName(MO1.getReg()); 788 if (unsigned ImmOffs = MO2.getImm()) 789 O << ", #" << ImmOffs * Scale; 790 O << "]"; 791 } 792 793 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI, 794 unsigned Op, 795 raw_ostream &O) { 796 printThumbAddrModeImm5SOperand(MI, Op, O, 1); 797 } 798 799 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI, 800 unsigned Op, 801 raw_ostream &O) { 802 printThumbAddrModeImm5SOperand(MI, Op, O, 2); 803 } 804 805 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI, 806 unsigned Op, 807 raw_ostream &O) { 808 printThumbAddrModeImm5SOperand(MI, Op, O, 4); 809 } 810 811 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, 812 raw_ostream &O) { 813 printThumbAddrModeImm5SOperand(MI, Op, O, 4); 814 } 815 816 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 817 // register with shift forms. 818 // REG 0 0 - e.g. R5 819 // REG IMM, SH_OPC - e.g. R5, LSL #3 820 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, 821 raw_ostream &O) { 822 const MCOperand &MO1 = MI->getOperand(OpNum); 823 const MCOperand &MO2 = MI->getOperand(OpNum+1); 824 825 unsigned Reg = MO1.getReg(); 826 O << getRegisterName(Reg); 827 828 // Print the shift opc. 829 assert(MO2.isImm() && "Not a valid t2_so_reg value!"); 830 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); 831 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); 832 if (ShOpc != ARM_AM::rrx) 833 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 834 } 835 836 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, 837 raw_ostream &O) { 838 const MCOperand &MO1 = MI->getOperand(OpNum); 839 const MCOperand &MO2 = MI->getOperand(OpNum+1); 840 841 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. 842 printOperand(MI, OpNum, O); 843 return; 844 } 845 846 O << "[" << getRegisterName(MO1.getReg()); 847 848 int32_t OffImm = (int32_t)MO2.getImm(); 849 bool isSub = OffImm < 0; 850 // Special value for #-0. All others are normal. 851 if (OffImm == INT32_MIN) 852 OffImm = 0; 853 if (isSub) 854 O << ", #-" << -OffImm; 855 else if (OffImm > 0) 856 O << ", #" << OffImm; 857 O << "]"; 858 } 859 860 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, 861 unsigned OpNum, 862 raw_ostream &O) { 863 const MCOperand &MO1 = MI->getOperand(OpNum); 864 const MCOperand &MO2 = MI->getOperand(OpNum+1); 865 866 O << "[" << getRegisterName(MO1.getReg()); 867 868 int32_t OffImm = (int32_t)MO2.getImm(); 869 // Don't print +0. 870 if (OffImm == INT32_MIN) 871 O << ", #-0"; 872 else if (OffImm < 0) 873 O << ", #-" << -OffImm; 874 else if (OffImm > 0) 875 O << ", #" << OffImm; 876 O << "]"; 877 } 878 879 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, 880 unsigned OpNum, 881 raw_ostream &O) { 882 const MCOperand &MO1 = MI->getOperand(OpNum); 883 const MCOperand &MO2 = MI->getOperand(OpNum+1); 884 885 O << "[" << getRegisterName(MO1.getReg()); 886 887 int32_t OffImm = (int32_t)MO2.getImm() / 4; 888 // Don't print +0. 889 if (OffImm < 0) 890 O << ", #-" << -OffImm * 4; 891 else if (OffImm > 0) 892 O << ", #" << OffImm * 4; 893 O << "]"; 894 } 895 896 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI, 897 unsigned OpNum, 898 raw_ostream &O) { 899 const MCOperand &MO1 = MI->getOperand(OpNum); 900 const MCOperand &MO2 = MI->getOperand(OpNum+1); 901 902 O << "[" << getRegisterName(MO1.getReg()); 903 if (MO2.getImm()) 904 O << ", #" << MO2.getImm() * 4; 905 O << "]"; 906 } 907 908 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, 909 unsigned OpNum, 910 raw_ostream &O) { 911 const MCOperand &MO1 = MI->getOperand(OpNum); 912 int32_t OffImm = (int32_t)MO1.getImm(); 913 // Don't print +0. 914 if (OffImm < 0) 915 O << ", #-" << -OffImm; 916 else 917 O << ", #" << OffImm; 918 } 919 920 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, 921 unsigned OpNum, 922 raw_ostream &O) { 923 const MCOperand &MO1 = MI->getOperand(OpNum); 924 int32_t OffImm = (int32_t)MO1.getImm() / 4; 925 // Don't print +0. 926 if (OffImm != 0) { 927 O << ", "; 928 if (OffImm < 0) 929 O << "#-" << -OffImm * 4; 930 else if (OffImm > 0) 931 O << "#" << OffImm * 4; 932 } 933 } 934 935 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, 936 unsigned OpNum, 937 raw_ostream &O) { 938 const MCOperand &MO1 = MI->getOperand(OpNum); 939 const MCOperand &MO2 = MI->getOperand(OpNum+1); 940 const MCOperand &MO3 = MI->getOperand(OpNum+2); 941 942 O << "[" << getRegisterName(MO1.getReg()); 943 944 assert(MO2.getReg() && "Invalid so_reg load / store address!"); 945 O << ", " << getRegisterName(MO2.getReg()); 946 947 unsigned ShAmt = MO3.getImm(); 948 if (ShAmt) { 949 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); 950 O << ", lsl #" << ShAmt; 951 } 952 O << "]"; 953 } 954 955 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 956 raw_ostream &O) { 957 const MCOperand &MO = MI->getOperand(OpNum); 958 O << '#' << ARM_AM::getFPImmFloat(MO.getImm()); 959 } 960 961 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, 962 raw_ostream &O) { 963 unsigned EncodedImm = MI->getOperand(OpNum).getImm(); 964 unsigned EltBits; 965 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); 966 O << "#0x" << utohexstr(Val); 967 } 968 969 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, 970 raw_ostream &O) { 971 unsigned Imm = MI->getOperand(OpNum).getImm(); 972 O << "#" << Imm + 1; 973 } 974 975 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, 976 raw_ostream &O) { 977 unsigned Imm = MI->getOperand(OpNum).getImm(); 978 if (Imm == 0) 979 return; 980 O << ", ror #"; 981 switch (Imm) { 982 default: assert (0 && "illegal ror immediate!"); 983 case 1: O << "8"; break; 984 case 2: O << "16"; break; 985 case 3: O << "24"; break; 986 } 987 } 988 989 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 990 raw_ostream &O) { 991 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 992 } 993 994 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, 995 raw_ostream &O) { 996 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}"; 997 } 998
