| /external/llvm/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 102 unsigned DestReg, unsigned SrcReg,
104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
105 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg)
110 if (BF::D16RegClass.contains(DestReg, SrcReg)) {
111 BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg)
117 if (BF::DRegClass.contains(DestReg)) {
119 BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg)
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
125 BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg)
[all...] |
| BlackfinInstrInfo.h | 51 unsigned DestReg, unsigned SrcReg,
69 unsigned DestReg, int FrameIndex,
73 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 37 unsigned DestReg, unsigned SrcReg,
39 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
41 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
76 unsigned DestReg, int FI,
80 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
81 isARMLowRegister(DestReg))) && "Unknown regclass!");
84 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
85 isARMLowRegister(DestReg))) {
97 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| Thumb1InstrInfo.h | 42 unsigned DestReg, unsigned SrcReg,
52 unsigned DestReg, int FrameIndex,
|
| Thumb2InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
|
| Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| Thumb2RegisterInfo.h | 36 unsigned DestReg, unsigned SubIdx, int Val,
|
| Thumb2InstrInfo.cpp | 109 unsigned DestReg, unsigned SrcReg,
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
149 unsigned DestReg, int FI,
166 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
171 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
176 unsigned DestReg, unsigned BaseReg, int NumBytes,
184 if (DestReg != ARM::SP && DestReg != BaseReg &
[all...] |
| Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx,
78 .addReg(DestReg, getDefRegState(true), SubIdx)
85 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
92 unsigned DestReg, unsigned BaseReg,
98 bool isHigh = !isARMLowRegister(DestReg) ||
109 unsigned LdReg = DestReg;
110 if (DestReg == ARM::SP) {
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
133 if (DestReg == ARM::SP || isSub)
165 /// a destreg = basereg + immediate in Thumb code
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 312 unsigned DestReg, unsigned SrcReg,
315 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
317 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
319 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
321 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
323 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
325 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
332 BuildMI(MBB, I, DL, MCID, DestReg)
335 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
507 unsigned DestReg, int FrameIdx
[all...] |
| PPCInstrInfo.h | 76 unsigned DestReg, int FrameIdx,
117 unsigned DestReg, unsigned SrcReg,
128 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaInstrInfo.h | 47 unsigned DestReg, unsigned SrcReg,
57 unsigned DestReg, int FrameIndex,
|
| AlphaInstrInfo.cpp | 123 unsigned DestReg, unsigned SrcReg,
125 if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
126 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
129 } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
130 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
133 } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
134 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
174 unsigned DestReg, int FrameIdx,
177 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
183 BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.h | 49 unsigned DestReg, unsigned SrcReg,
62 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
68 unsigned DestReg, int FrameIdx,
|
| MSP430InstrInfo.cpp | 66 unsigned DestReg, int FrameIdx,
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
93 unsigned DestReg, unsigned SrcReg,
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
|
| SparcInstrInfo.cpp | 271 unsigned DestReg, unsigned SrcReg,
273 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
274 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
276 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
277 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
279 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
280 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
310 unsigned DestReg, int FI,
317 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
319 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg,
81 unsigned DestReg, int FrameIdx,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,
|
| XCoreInstrInfo.cpp | 336 unsigned DestReg, unsigned SrcReg,
338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
353 if (DestReg == XCore::SP && GRSrc) {
378 unsigned DestReg, int FrameIndex,
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 104 unsigned DestReg, unsigned SrcReg,
108 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
121 if (Mips::CCRRegClass.contains(DestReg))
123 else if (Mips::FGR32RegClass.contains(DestReg))
125 else if (DestReg == Mips::HI)
126 Opc = Mips::MTHI, DestReg = 0;
127 else if (DestReg == Mips::LO)
128 Opc = Mips::MTLO, DestReg = 0;
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
132 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)
[all...] |
| MipsInstrInfo.h | 160 unsigned DestReg, unsigned SrcReg,
170 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/CodeGen/ |
| StrongPHIElimination.cpp | 244 unsigned DestReg = BBI->getOperand(0).getReg();
245 addReg(DestReg);
252 unionRegs(DestReg, SrcReg);
288 unsigned DestReg = BBI->getOperand(0).getReg();
289 addReg(DestReg);
294 unionRegs(DestReg, SrcReg);
318 unsigned DestReg = PHI->getOperand(0).getReg();
319 if (!InsertedDestCopies.count(DestReg))
320 MergeLIsAndRename(DestReg, NewReg);
341 unsigned DestReg = I->first
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 193 unsigned DestReg) {
195 .addReg(DestReg, RegState::Define);
206 unsigned DestReg) {
209 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
242 unsigned DestReg) {
243 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
|
