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      1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Mips implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsInstrInfo.h"
     15 #include "MipsTargetMachine.h"
     16 #include "MipsMachineFunction.h"
     17 #include "InstPrinter/MipsInstPrinter.h"
     18 #include "llvm/CodeGen/MachineInstrBuilder.h"
     19 #include "llvm/CodeGen/MachineRegisterInfo.h"
     20 #include "llvm/Support/ErrorHandling.h"
     21 #include "llvm/Support/TargetRegistry.h"
     22 #include "llvm/ADT/STLExtras.h"
     23 
     24 #define GET_INSTRINFO_CTOR
     25 #include "MipsGenInstrInfo.inc"
     26 
     27 using namespace llvm;
     28 
     29 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
     30   : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     31     TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
     32     RI(*TM.getSubtargetImpl(), *this) {}
     33 
     34 
     35 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
     36   return RI;
     37 }
     38 
     39 static bool isZeroImm(const MachineOperand &op) {
     40   return op.isImm() && op.getImm() == 0;
     41 }
     42 
     43 /// isLoadFromStackSlot - If the specified machine instruction is a direct
     44 /// load from a stack slot, return the virtual or physical register number of
     45 /// the destination along with the FrameIndex of the loaded stack slot.  If
     46 /// not, return 0.  This predicate must return 0 if the instruction has
     47 /// any side effects other than loading from the stack slot.
     48 unsigned MipsInstrInfo::
     49 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
     50 {
     51   unsigned Opc = MI->getOpcode();
     52 
     53   if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
     54       (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
     55       (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
     56       (Opc == Mips::LDC164_P8)) {
     57     if ((MI->getOperand(1).isFI()) && // is a stack slot
     58         (MI->getOperand(2).isImm()) &&  // the imm is zero
     59         (isZeroImm(MI->getOperand(2)))) {
     60       FrameIndex = MI->getOperand(1).getIndex();
     61       return MI->getOperand(0).getReg();
     62     }
     63   }
     64 
     65   return 0;
     66 }
     67 
     68 /// isStoreToStackSlot - If the specified machine instruction is a direct
     69 /// store to a stack slot, return the virtual or physical register number of
     70 /// the source reg along with the FrameIndex of the loaded stack slot.  If
     71 /// not, return 0.  This predicate must return 0 if the instruction has
     72 /// any side effects other than storing to the stack slot.
     73 unsigned MipsInstrInfo::
     74 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
     75 {
     76   unsigned Opc = MI->getOpcode();
     77 
     78   if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
     79       (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
     80       (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
     81       (Opc == Mips::SDC164_P8)) {
     82     if ((MI->getOperand(1).isFI()) && // is a stack slot
     83         (MI->getOperand(2).isImm()) &&  // the imm is zero
     84         (isZeroImm(MI->getOperand(2)))) {
     85       FrameIndex = MI->getOperand(1).getIndex();
     86       return MI->getOperand(0).getReg();
     87     }
     88   }
     89   return 0;
     90 }
     91 
     92 /// insertNoop - If data hazard condition is found insert the target nop
     93 /// instruction.
     94 void MipsInstrInfo::
     95 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
     96 {
     97   DebugLoc DL;
     98   BuildMI(MBB, MI, DL, get(Mips::NOP));
     99 }
    100 
    101 void MipsInstrInfo::
    102 copyPhysReg(MachineBasicBlock &MBB,
    103             MachineBasicBlock::iterator I, DebugLoc DL,
    104             unsigned DestReg, unsigned SrcReg,
    105             bool KillSrc) const {
    106   unsigned Opc = 0, ZeroReg = 0;
    107 
    108   if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
    109     if (Mips::CPURegsRegClass.contains(SrcReg))
    110       Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
    111     else if (Mips::CCRRegClass.contains(SrcReg))
    112       Opc = Mips::CFC1;
    113     else if (Mips::FGR32RegClass.contains(SrcReg))
    114       Opc = Mips::MFC1;
    115     else if (SrcReg == Mips::HI)
    116       Opc = Mips::MFHI, SrcReg = 0;
    117     else if (SrcReg == Mips::LO)
    118       Opc = Mips::MFLO, SrcReg = 0;
    119   }
    120   else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
    121     if (Mips::CCRRegClass.contains(DestReg))
    122       Opc = Mips::CTC1;
    123     else if (Mips::FGR32RegClass.contains(DestReg))
    124       Opc = Mips::MTC1;
    125     else if (DestReg == Mips::HI)
    126       Opc = Mips::MTHI, DestReg = 0;
    127     else if (DestReg == Mips::LO)
    128       Opc = Mips::MTLO, DestReg = 0;
    129   }
    130   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
    131     Opc = Mips::FMOV_S;
    132   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
    133     Opc = Mips::FMOV_D32;
    134   else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
    135     Opc = Mips::MOVCCRToCCR;
    136   else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
    137     if (Mips::CPU64RegsRegClass.contains(SrcReg))
    138       Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
    139     else if (SrcReg == Mips::HI64)
    140       Opc = Mips::MFHI64, SrcReg = 0;
    141     else if (SrcReg == Mips::LO64)
    142       Opc = Mips::MFLO64, SrcReg = 0;
    143   }
    144   else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
    145     if (DestReg == Mips::HI64)
    146       Opc = Mips::MTHI64, DestReg = 0;
    147     else if (DestReg == Mips::LO64)
    148       Opc = Mips::MTLO64, DestReg = 0;
    149   }
    150 
    151   assert(Opc && "Cannot copy registers");
    152 
    153   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
    154 
    155   if (DestReg)
    156     MIB.addReg(DestReg, RegState::Define);
    157 
    158   if (ZeroReg)
    159     MIB.addReg(ZeroReg);
    160 
    161   if (SrcReg)
    162     MIB.addReg(SrcReg, getKillRegState(KillSrc));
    163 }
    164 
    165 void MipsInstrInfo::
    166 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    167                     unsigned SrcReg, bool isKill, int FI,
    168                     const TargetRegisterClass *RC,
    169                     const TargetRegisterInfo *TRI) const {
    170   DebugLoc DL;
    171   if (I != MBB.end()) DL = I->getDebugLoc();
    172   unsigned Opc = 0;
    173 
    174   if (RC == Mips::CPURegsRegisterClass)
    175     Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
    176   else if (RC == Mips::CPU64RegsRegisterClass)
    177     Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
    178   else if (RC == Mips::FGR32RegisterClass)
    179     Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
    180   else if (RC == Mips::AFGR64RegisterClass)
    181     Opc = Mips::SDC1;
    182   else if (RC == Mips::FGR64RegisterClass)
    183     Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
    184 
    185   assert(Opc && "Register class not handled!");
    186   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
    187     .addFrameIndex(FI).addImm(0);
    188 }
    189 
    190 void MipsInstrInfo::
    191 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    192                      unsigned DestReg, int FI,
    193                      const TargetRegisterClass *RC,
    194                      const TargetRegisterInfo *TRI) const
    195 {
    196   DebugLoc DL;
    197   if (I != MBB.end()) DL = I->getDebugLoc();
    198   unsigned Opc = 0;
    199 
    200   if (RC == Mips::CPURegsRegisterClass)
    201     Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
    202   else if (RC == Mips::CPU64RegsRegisterClass)
    203     Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
    204   else if (RC == Mips::FGR32RegisterClass)
    205     Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
    206   else if (RC == Mips::AFGR64RegisterClass)
    207     Opc = Mips::LDC1;
    208   else if (RC == Mips::FGR64RegisterClass)
    209     Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
    210 
    211   assert(Opc && "Register class not handled!");
    212   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0);
    213 }
    214 
    215 MachineInstr*
    216 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
    217                                         uint64_t Offset, const MDNode *MDPtr,
    218                                         DebugLoc DL) const {
    219   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
    220     .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
    221   return &*MIB;
    222 }
    223 
    224 //===----------------------------------------------------------------------===//
    225 // Branch Analysis
    226 //===----------------------------------------------------------------------===//
    227 
    228 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
    229   return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
    230           Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
    231           Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
    232           Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
    233           Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::J) ?
    234          Opc : 0;
    235 }
    236 
    237 /// GetOppositeBranchOpc - Return the inverse of the specified
    238 /// opcode, e.g. turning BEQ to BNE.
    239 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
    240 {
    241   switch (Opc) {
    242   default: llvm_unreachable("Illegal opcode!");
    243   case Mips::BEQ    : return Mips::BNE;
    244   case Mips::BNE    : return Mips::BEQ;
    245   case Mips::BGTZ   : return Mips::BLEZ;
    246   case Mips::BGEZ   : return Mips::BLTZ;
    247   case Mips::BLTZ   : return Mips::BGEZ;
    248   case Mips::BLEZ   : return Mips::BGTZ;
    249   case Mips::BEQ64  : return Mips::BNE64;
    250   case Mips::BNE64  : return Mips::BEQ64;
    251   case Mips::BGTZ64 : return Mips::BLEZ64;
    252   case Mips::BGEZ64 : return Mips::BLTZ64;
    253   case Mips::BLTZ64 : return Mips::BGEZ64;
    254   case Mips::BLEZ64 : return Mips::BGTZ64;
    255   case Mips::BC1T   : return Mips::BC1F;
    256   case Mips::BC1F   : return Mips::BC1T;
    257   }
    258 }
    259 
    260 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
    261                           MachineBasicBlock *&BB,
    262                           SmallVectorImpl<MachineOperand>& Cond) {
    263   assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
    264   int NumOp = Inst->getNumExplicitOperands();
    265 
    266   // for both int and fp branches, the last explicit operand is the
    267   // MBB.
    268   BB = Inst->getOperand(NumOp-1).getMBB();
    269   Cond.push_back(MachineOperand::CreateImm(Opc));
    270 
    271   for (int i=0; i<NumOp-1; i++)
    272     Cond.push_back(Inst->getOperand(i));
    273 }
    274 
    275 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
    276                                   MachineBasicBlock *&TBB,
    277                                   MachineBasicBlock *&FBB,
    278                                   SmallVectorImpl<MachineOperand> &Cond,
    279                                   bool AllowModify) const
    280 {
    281   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    282 
    283   // Skip all the debug instructions.
    284   while (I != REnd && I->isDebugValue())
    285     ++I;
    286 
    287   if (I == REnd || !isUnpredicatedTerminator(&*I)) {
    288     // If this block ends with no branches (it just falls through to its succ)
    289     // just return false, leaving TBB/FBB null.
    290     TBB = FBB = NULL;
    291     return false;
    292   }
    293 
    294   MachineInstr *LastInst = &*I;
    295   unsigned LastOpc = LastInst->getOpcode();
    296 
    297   // Not an analyzable branch (must be an indirect jump).
    298   if (!GetAnalyzableBrOpc(LastOpc))
    299     return true;
    300 
    301   // Get the second to last instruction in the block.
    302   unsigned SecondLastOpc = 0;
    303   MachineInstr *SecondLastInst = NULL;
    304 
    305   if (++I != REnd) {
    306     SecondLastInst = &*I;
    307     SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
    308 
    309     // Not an analyzable branch (must be an indirect jump).
    310     if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
    311       return true;
    312   }
    313 
    314   // If there is only one terminator instruction, process it.
    315   if (!SecondLastOpc) {
    316     // Unconditional branch
    317     if (LastOpc == Mips::J) {
    318       TBB = LastInst->getOperand(0).getMBB();
    319       return false;
    320     }
    321 
    322     // Conditional branch
    323     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
    324     return false;
    325   }
    326 
    327   // If we reached here, there are two branches.
    328   // If there are three terminators, we don't know what sort of block this is.
    329   if (++I != REnd && isUnpredicatedTerminator(&*I))
    330     return true;
    331 
    332   // If second to last instruction is an unconditional branch,
    333   // analyze it and remove the last instruction.
    334   if (SecondLastOpc == Mips::J) {
    335     // Return if the last instruction cannot be removed.
    336     if (!AllowModify)
    337       return true;
    338 
    339     TBB = SecondLastInst->getOperand(0).getMBB();
    340     LastInst->eraseFromParent();
    341     return false;
    342   }
    343 
    344   // Conditional branch followed by an unconditional branch.
    345   // The last one must be unconditional.
    346   if (LastOpc != Mips::J)
    347     return true;
    348 
    349   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
    350   FBB = LastInst->getOperand(0).getMBB();
    351 
    352   return false;
    353 }
    354 
    355 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
    356                                 MachineBasicBlock *TBB, DebugLoc DL,
    357                                 const SmallVectorImpl<MachineOperand>& Cond)
    358   const {
    359   unsigned Opc = Cond[0].getImm();
    360   const MCInstrDesc &MCID = get(Opc);
    361   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
    362 
    363   for (unsigned i = 1; i < Cond.size(); ++i)
    364     MIB.addReg(Cond[i].getReg());
    365 
    366   MIB.addMBB(TBB);
    367 }
    368 
    369 unsigned MipsInstrInfo::
    370 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
    371              MachineBasicBlock *FBB,
    372              const SmallVectorImpl<MachineOperand> &Cond,
    373              DebugLoc DL) const {
    374   // Shouldn't be a fall through.
    375   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    376 
    377   // # of condition operands:
    378   //  Unconditional branches: 0
    379   //  Floating point branches: 1 (opc)
    380   //  Int BranchZero: 2 (opc, reg)
    381   //  Int Branch: 3 (opc, reg0, reg1)
    382   assert((Cond.size() <= 3) &&
    383          "# of Mips branch conditions must be <= 3!");
    384 
    385   // Two-way Conditional branch.
    386   if (FBB) {
    387     BuildCondBr(MBB, TBB, DL, Cond);
    388     BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
    389     return 2;
    390   }
    391 
    392   // One way branch.
    393   // Unconditional branch.
    394   if (Cond.empty())
    395     BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
    396   else // Conditional branch.
    397     BuildCondBr(MBB, TBB, DL, Cond);
    398   return 1;
    399 }
    400 
    401 unsigned MipsInstrInfo::
    402 RemoveBranch(MachineBasicBlock &MBB) const
    403 {
    404   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    405   MachineBasicBlock::reverse_iterator FirstBr;
    406   unsigned removed;
    407 
    408   // Skip all the debug instructions.
    409   while (I != REnd && I->isDebugValue())
    410     ++I;
    411 
    412   FirstBr = I;
    413 
    414   // Up to 2 branches are removed.
    415   // Note that indirect branches are not removed.
    416   for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
    417     if (!GetAnalyzableBrOpc(I->getOpcode()))
    418       break;
    419 
    420   MBB.erase(I.base(), FirstBr.base());
    421 
    422   return removed;
    423 }
    424 
    425 /// ReverseBranchCondition - Return the inverse opcode of the
    426 /// specified Branch instruction.
    427 bool MipsInstrInfo::
    428 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
    429 {
    430   assert( (Cond.size() && Cond.size() <= 3) &&
    431           "Invalid Mips branch condition!");
    432   Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
    433   return false;
    434 }
    435 
    436 /// getGlobalBaseReg - Return a virtual register initialized with the
    437 /// the global base register value. Output instructions required to
    438 /// initialize the register in the function entry block, if necessary.
    439 ///
    440 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
    441   MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
    442   unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
    443   if (GlobalBaseReg != 0)
    444     return GlobalBaseReg;
    445 
    446   // Insert the set of GlobalBaseReg into the first MBB of the function
    447   MachineBasicBlock &FirstMBB = MF->front();
    448   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
    449   MachineRegisterInfo &RegInfo = MF->getRegInfo();
    450   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
    451 
    452   GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
    453   BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
    454           GlobalBaseReg).addReg(Mips::GP);
    455   RegInfo.addLiveIn(Mips::GP);
    456 
    457   MipsFI->setGlobalBaseReg(GlobalBaseReg);
    458   return GlobalBaseReg;
    459 }
    460