| /external/llvm/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 106 .addReg(SrcReg, getKillRegState(KillSrc));
112 .addReg(SrcReg, getKillRegState(KillSrc))
120 .addReg(SrcReg, getKillRegState(KillSrc));
126 .addReg(SrcReg, getKillRegState(KillSrc));
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
139 .addReg(SrcReg, getKillRegState(KillSrc));
147 .addReg(SrcReg, getKillRegState(KillSrc));
153 .addReg(SrcReg, getKillRegState(KillSrc));
181 .addReg(SrcReg, getKillRegState(isKill))
189 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0)
86 .addReg(Reg2, getKillRegState(isKill2));
|
| SystemZInstrInfo.cpp | 70 .addReg(SrcReg, getKillRegState(isKill));
123 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 40 .addReg(SrcReg, getKillRegState(KillSrc)));
69 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 226 .addReg(Src1Reg, getKillRegState(Src1Kill))
227 .addReg(Src2Reg, getKillRegState(Src2Kill));
237 MIB.addReg(TmpReg, getKillRegState(true))
238 .addReg(AccReg, getKillRegState(AccKill));
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMLoadStoreOptimizer.cpp | 345 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
356 .addReg(Base, getKillRegState(BaseKill))
360 | getKillRegState(Regs[i].second));
749 .addReg(Base, getKillRegState(BaseKill))
904 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
907 getKillRegState(MO.isKill())));
938 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
944 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
[all...] |
| ARMBaseInstrInfo.cpp | 635 .addReg(SrcReg, getKillRegState(KillSrc))));
656 MIB.addReg(SrcReg, getKillRegState(KillSrc));
658 MIB.addReg(SrcReg, getKillRegState(KillSrc));
676 .addReg(Src, getKillRegState(KillSrc))
677 .addReg(Src, getKillRegState(KillSrc)));
723 .addReg(SrcReg, getKillRegState(isKill))
727 .addReg(SrcReg, getKillRegState(isKill))
735 .addReg(SrcReg, getKillRegState(isKill))
745 .addReg(SrcReg, getKillRegState(isKill))
749 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| ARMExpandPseudoInsts.cpp | 578 getKillRegState(MO.isKill()));
[all...] |
| Thumb2InstrInfo.cpp | 116 .addReg(SrcReg, getKillRegState(KillSrc)));
139 .addReg(SrcReg, getKillRegState(isKill))
|
| Thumb1FrameLowering.cpp | 343 MIB.addReg(Reg, getKillRegState(isKill));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 151 .addReg(Reg2, getKillRegState(Reg2IsKill))
152 .addReg(Reg1, getKillRegState(Reg1IsKill))
333 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
335 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
349 getKillRegState(isKill)),
358 getKillRegState(isKill)),
365 getKillRegState(isKill)),
374 getKillRegState(isKill)),
380 getKillRegState(isKill)),
385 getKillRegState(isKill))
[all...] |
| PPCRegisterInfo.cpp | 473 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
486 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 128 .addReg(SrcReg, getKillRegState(KillSrc));
132 .addReg(SrcReg, getKillRegState(KillSrc));
136 .addReg(SrcReg, getKillRegState(KillSrc));
157 .addReg(SrcReg, getKillRegState(isKill))
161 .addReg(SrcReg, getKillRegState(isKill))
165 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 275 .addReg(SrcReg, getKillRegState(KillSrc));
278 .addReg(SrcReg, getKillRegState(KillSrc));
281 .addReg(SrcReg, getKillRegState(KillSrc));
297 .addReg(SrcReg, getKillRegState(isKill));
300 .addReg(SrcReg, getKillRegState(isKill));
303 .addReg(SrcReg, getKillRegState(isKill));
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
104 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 343 .addReg(SrcReg, getKillRegState(KillSrc))
355 .addReg(SrcReg, getKillRegState(KillSrc));
371 .addReg(SrcReg, getKillRegState(isKill))
|
| XCoreRegisterInfo.cpp | 245 .addReg(Reg, getKillRegState(isKill))
266 .addReg(Reg, getKillRegState(isKill))
295 .addReg(Reg, getKillRegState(isKill))
|
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfoImpl.cpp | 101 .addReg(Reg2, getKillRegState(Reg2IsKill))
102 .addReg(Reg1, getKillRegState(Reg2IsKill));
105 .addReg(Reg2, getKillRegState(Reg2IsKill))
106 .addReg(Reg1, getKillRegState(Reg2IsKill));
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0);
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 135 .addReg(SrcReg, getKillRegState(KillSrc));
170 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 252 inline unsigned getKillRegState(bool B) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 162 MIB.addReg(SrcReg, getKillRegState(KillSrc));
186 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 60 addReg(SrcReg, getKillRegState(KillSrc));
|
