| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
76 /// the specified operand. This is used for operands with :lower16: and
135 /// operand.
139 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
144 /// operand.
149 /// operand.
154 /// operand.
160 /// operand as needed by load/store instructions.
212 /// operand
[all...] |
| ARMAddressingModes.h | 109 // third operand encodes the shift opcode and the imm if a reg isn't present.
132 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
168 /// into an shifter_operand immediate operand, return the 12-bit encoding for
218 // 8-bit (or less) immediates are trivially immediate operand with a shift
237 // 16-bit (or less) immediates are trivially immediate operand with a shift
310 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
364 // Try a shifter operand as one part
397 // The first operand is always a Reg. The second operand is a reg if in
400 // fourth operand 16-17 encodes the index mode
[all...] |
| /external/clang/include/clang/AST/ |
| ExprCXX.h | 388 llvm::PointerUnion<Stmt *, TypeSourceInfo *> Operand;
392 CXXTypeidExpr(QualType Ty, TypeSourceInfo *Operand, SourceRange R)
397 Operand->getType()->isDependentType(),
398 Operand->getType()->isInstantiationDependentType(),
399 Operand->getType()->containsUnexpandedParameterPack()),
400 Operand(Operand), Range(R) { }
402 CXXTypeidExpr(QualType Ty, Expr *Operand, SourceRange R)
407 Operand->isTypeDependent() || Operand->isValueDependent()
[all...] |
| /external/v8/src/x64/ |
| stub-cache-x64.cc | 60 __ cmpl(name, Operand(kScratchRegister, offset, times_4, 0));
65 Operand(kScratchRegister, offset, times_4, kPointerSize));
149 __ lea(index, Operand(index, index, times_2, 0)); // index *= 3.
154 __ movq(entity_name, Operand(properties, index, times_pointer_size,
243 Operand(rsi, Context::SlotOffset(Context::GLOBAL_INDEX)));
248 __ movq(prototype, Operand(prototype, Context::SlotOffset(index)));
262 __ cmpq(Operand(rsi, Context::SlotOffset(Context::GLOBAL_INDEX)),
423 __ movq(scratch, Operand(rsp, 0));
425 __ movq(Operand(rsp, 0), scratch);
428 __ movq(Operand(rsp, i * kPointerSize), scratch)
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 135 /// getStartLoc - Get the location of the first token of this operand.
138 /// getEndLoc - Get the location of the last token of this operand.
346 return Error(ErrorLoc, "invalid operand for instruction");
474 Error(Parser.getTok().getLoc(), "unknown operand");
478 // Push the parsed operand into the list of operands
497 // Parse the first operand
506 // Parse the next operand
511 // If the instruction requires a memory operand then we need to
513 // memory operand.
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrLoadStore.td | 82 def MEMri32 : Operand<i32> {
86 def MEMri64 : Operand<i64> {
90 def LOCALri32 : Operand<i32> {
94 def LOCALri64 : Operand<i64> {
98 def MEMii32 : Operand<i32> {
102 def MEMii64 : Operand<i64> {
106 // The operand here does not correspond to an actual address, so we
108 def MEMpi : Operand<i32> {
112 def MEMret : Operand<i32> {
|
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyIndVar.cpp | 85 /// foldIVUser - Fold an IV operand into its use. This removes increments of an
90 /// Return the operand of IVOperand for this induction variable if IVOperand can
108 // Attempt to fold a binary operator with constant operand.
115 // IVSrc must be the (SCEVable) IV, since the other operand is const.
116 assert(SE->isSCEVable(IVSrc->getType()) && "Expect SCEVable IV operand");
130 // We have something that might fold it's operand. Compare SCEVs.
134 // Bypass the operand if SCEV can prove it has no effect.
138 DEBUG(dbgs() << "INDVARS: Eliminated IV operand: " << *IVOperand
299 /// non-recursively when the operand is already known to be a simpleIVUser.
|
| /frameworks/compile/libbcc/tests/ |
| disassem.cpp | 67 * they modify the instruction rather than just being an operand to
69 * follows a operand.
72 * 2 - print Operand 2 of a data processing instruction
78 * a - address operand of ldr/str instruction
79 * e - address operand of ldrh/strh instruction
81 * f - 1st fp operand (register) (bits 12-14)
82 * g - 2nd fp operand (register) (bits 16-18)
83 * h - 3rd fp operand (register/immediate) (bits 0-4)
346 /* 2 - print Operand 2 of a data processing instruction */
383 /* a - address operand of ldr/str instruction *
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| disassem.c | 66 * they modify the instruction rather than just being an operand to
68 * follows a operand.
71 * 2 - print Operand 2 of a data processing instruction
77 * a - address operand of ldr/str instruction
78 * e - address operand of ldrh/strh instruction
80 * f - 1st fp operand (register) (bits 12-14)
81 * g - 2nd fp operand (register) (bits 16-18)
82 * h - 3rd fp operand (register/immediate) (bits 0-4)
350 /* 2 - print Operand 2 of a data processing instruction */
387 /* a - address operand of ldr/str instruction *
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 456 /// getStartLoc - Get the location of the first token of this operand.
458 /// getEndLoc - Get the location of the last token of this operand.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 152 /// getMachineOpValue - Return binary encoding of operand. If the machine
153 /// operand requires relocation, record the relocation and return zero.
162 // operand values, instead querying getMachineOpValue() directly for
163 // each operand it needs to encode. Thus, any of the new encoder
348 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
349 /// machine operand requires relocation, record the relocation and return
427 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
428 /// machine operand requires relocation, record the relocation and return zero.
447 llvm_unreachable("Unsupported operand type for movw/movt");
452 /// getMachineOpValue - Return binary encoding of operand. If the machin
[all...] |
| /external/elfutils/libelf/ |
| elf_error.c | 99 N_("invalid size of source operand")
102 (ELF_E_SOURCE_SIZE_IDX + sizeof "invalid size of source operand")
103 N_("invalid size of destination operand")
106 (ELF_E_DEST_SIZE_IDX + sizeof "invalid size of destination operand")
167 N_("invalid operand")
170 (ELF_E_INVALID_OPERAND_IDX + sizeof "invalid operand")
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 15 // Mips Operand, Complex Patterns and Transformations Definitions.
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
21 // Unsigned Operand
22 def uimm16_64 : Operand<i64> {
73 /// Arithmetic Instructions (3-Operand, R-Type)
|
| /external/mesa3d/src/glsl/ |
| opt_algebraic.cpp | 64 ir_rvalue *operand);
162 * we may need to swizzle that operand out to a vector if the expression was
167 ir_rvalue *operand)
169 if (expr->type->is_vector() && operand->type->is_scalar()) {
170 return new(mem_ctx) ir_swizzle(operand, 0, 0, 0, 0,
173 return operand;
|
| /external/skia/src/xml/ |
| SkJSDisplayable.cpp | 268 SkOperand operand; local
269 info->getValue(displayable, &operand, 1);
270 scalar = operand.fScalar;
371 SkOperand operand; local
372 operand.fScalar = scalar;
373 info->setValue(displayable, &operand, 1);
|
| /external/llvm/docs/ |
| GetElementPtr.html | 89 <p>Quick answer: The index stepping through the first operand.</p>
107 first operand indexes through the pointer; the second operand indexes the
120 perform the computation. The first operand to the GEP instruction must be a
122 the GEP instruction as an operand without any need for accessing memory. It
123 must, therefore be indexed and requires an index operand. Consider this
144 statement. The function argument <tt>P</tt> will be the first operand of each
145 of these GEP instructions. The second operand indexes through that pointer.
146 The third operand will be the field offset into the
167 <p>In each case the first operand is the pointer through which the GE
[all...] |
| /external/v8/src/mips/ |
| virtual-frame-mips.h | 192 const Operand& r2 = Operand(no_reg));
197 const Operand& r2 = Operand(no_reg));
240 // The current top of the expression stack as an assembly operand.
246 // An element of the expression stack as an assembly operand.
257 // A frame-allocated local as an assembly operand.
269 // A parameter as an assembly operand.
387 void EmitPush(Operand operand, TypeInfo type_info = TypeInfo::Unknown())
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.c | 149 * specifierForUID - Given a UID, returns the name and operand specification for
294 * instruction as having them. Also sets the instruction's default operand,
361 case 0x66: /* Operand-size override */
[all...] |
| /cts/tools/dx-tests/src/dxc/junit/opcodes/ret/ |
| Test_ret.java | 40 * @title index operand
106 * @title index operand
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| UndefResultChecker.cpp | 64 << " operand of '"
69 // Neither operand was undefined, but the result is undefined.
|
| /external/clang/test/Sema/ |
| i-c-e.c | 8 // rdar://6091492 - ?: with __builtin_constant_p as the operand is an i-c-e.
56 // expected-warning {{use of logical '||' with constant operand}} \
|
| /external/llvm/include/llvm/ |
| GlobalAlias.h | 37 // allocate space for exactly one operand
46 /// Provide fast operand accessors
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 40 assert(Op.isExpr() && "unknown pcrel immediate operand");
54 assert(Op.isExpr() && "unknown operand kind in printOperand");
|
| /external/llvm/lib/Target/PowerPC/ |
| PPC.h | 45 /// Target Operand Flag enum.
51 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
|
| /external/llvm/test/CodeGen/X86/ |
| 2008-09-18-inline-asm-2.ll | 8 ; operand.
24 ; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.
|
