| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.h | 93 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
96 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
|
| MipsDelaySlotFiller.cpp | 75 unsigned Reg);
199 unsigned Reg;
201 if (!MO.isReg() || !(Reg = MO.getReg()))
205 // check whether Reg is defined or used before delay slot.
206 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
210 // check whether Reg is defined before delay slot.
211 if (IsRegInSet(RegDefs, Reg))
233 unsigned Reg;
235 if (!MO.isReg() || !(Reg = MO.getReg())
[all...] |
| MipsRegisterInfo.cpp | 14 #define DEBUG_TYPE "mips-reg-info"
205 for (const unsigned *Reg = ReservedCPURegs; *Reg; ++Reg)
206 Reserved.set(*Reg);
209 for (const unsigned *Reg = ReservedCPU64Regs; *Reg; ++Reg)
210 Reserved.set(*Reg);
213 for (RegIter Reg = Mips::AFGR64RegisterClass->begin()
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 38 /// Target machine description which we query for reg. names, data
72 unsigned Reg);
216 unsigned Reg = MO.getReg();
219 //check whether Reg is defined or used before delay slot.
220 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
224 //check whether Reg is defined before delay slot.
225 if (IsRegInSet(RegDefs, Reg))
243 const MachineOperand &Reg = MI->getOperand(0);
244 assert(Reg.isReg() && "JMPL first operand is not a register.")
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.h | 60 /// VarArgsGPOffset - X86-64 vararg func int reg offset.
62 /// VarArgsFPOffset - X86-64 vararg func fp reg offset.
112 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
115 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
|
| X86InstrBuilder.h | 45 unsigned Reg;
57 Base.Reg = 0;
65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
93 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
104 /// [Reg + Offset], i.e., one with no scale or index, but with a
109 unsigned Reg, bool isKill, int Offset) {
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 /// [Reg + Reg]
[all...] |
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 91 unsigned GetGroup(unsigned Reg);
109 unsigned LeaveGroup(unsigned Reg);
111 /// IsLive - Return true if Reg is live
112 bool IsLive(unsigned Reg);
171 void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
177 BitVector GetRenameRegisters(unsigned Reg);
|
| RegAllocFast.cpp | 73 MachineInstr *LastUse; // Last instr to use reg.
177 // Find the location Reg would belong...
656 unsigned Reg = MO.getReg();
657 if (!TargetRegisterInfo::isVirtualRegister(Reg))
660 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
661 if (ThroughRegs.insert(Reg))
662 DEBUG(dbgs() << ' ' << PrintReg(Reg));
672 unsigned Reg = MO.getReg();
673 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue
[all...] |
| VirtRegMap.cpp | 233 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
234 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG)
235 Used.set(Virt2PhysMap[Reg]);
240 for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
241 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
243 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
[all...] |
| MachineSink.cpp | 90 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
142 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
147 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
150 if (MRI->use_nodbg_empty(Reg))
175 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
189 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
303 unsigned Reg = MO.getReg();
304 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg))
306 if (MRI->hasOneNonDBGUse(Reg))
[all...] |
| MachineLICM.cpp | 53 "Number of instructions hoisted in low reg pressure situation");
172 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
174 void AddToLiveIns(unsigned Reg);
190 bool HasAnyPHIUse(unsigned Reg) const;
192 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
196 unsigned Reg) const;
230 unsigned Reg, unsigned OpIdx,
407 unsigned Reg = MO.getReg();
408 if (!Reg)
410 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &
[all...] |
| ScheduleDAGEmit.cpp | 45 unsigned Reg = 0;
50 Reg = II->getReg();
54 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
|
| InlineSpiller.cpp | 117 SibValueInfo(unsigned Reg, VNInfo *VNI)
119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
158 bool isRegToSpill(unsigned Reg) {
160 RegsToSpill.end(), Reg) != RegsToSpill.end();
163 bool isSibling(unsigned Reg);
175 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
184 void spillAroundUses(unsigned Reg);
209 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
211 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
214 if (MI->getOperand(0).getReg() == Reg)
[all...] |
| MachineVerifier.cpp | 84 // Add Reg and any sub-registers to RV
85 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86 RV.push_back(Reg);
87 if (TargetRegisterInfo::isPhysicalRegister(Reg))
88 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
120 bool addPassed(unsigned Reg) {
121 if (!TargetRegisterInfo::isVirtualRegister(Reg))
123 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
125 return vregsPassed.insert(Reg).second
[all...] |
| MachineInstr.cpp | 53 assert(isReg() && "Can only add reg operand to use lists");
58 Contents.Reg.Prev = 0;
59 Contents.Reg.Next = 0;
70 Head = &(*Head)->Contents.Reg.Next;
72 Contents.Reg.Next = *Head;
73 if (Contents.Reg.Next) {
74 assert(getReg() == Contents.Reg.Next->getReg() &&
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next
[all...] |
| RegAllocLinearScan.cpp | 187 void recordRecentlyUsed(unsigned reg) {
188 assert(reg != 0 && "Recently used register is NOREG!");
190 *RecentNext++ = reg;
230 bool isRecentlyUsed(unsigned reg) const {
231 return reg == avoidWAW_ ||
232 std::find(RecentRegs.begin(), RecentRegs.end(), reg) != RecentRegs.end();
256 void DowngradeRegister(LiveInterval *li, unsigned Reg);
259 void UpgradeRegister(unsigned Reg);
266 unsigned reg, float weight,
285 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
625 unsigned reg = IP.first->reg; local
691 unsigned reg = Interval->reg; local
737 unsigned reg = Interval->reg; local
1089 unsigned reg = I->reg; local
1144 unsigned reg = i->first->reg; local
1162 unsigned reg = Order[i]; local
1173 unsigned reg = Order[i]; local
1508 unsigned reg = i->first->reg; local
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 308 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
309 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
315 bool readsVirtualRegister(unsigned Reg) const {
316 return readsWritesVirtualRegister(Reg).first;
320 /// indicating if this instruction reads or writes Reg. This also considers
322 /// If Ops is not null, all operand indices for Reg are added.
323 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
329 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
330 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
337 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const
[all...] |