/external/llvm/test/CodeGen/Mips/ |
o32_cc.ll | 18 ; CHECK: lwc1 $f12, %lo 19 ; CHECK: lwc1 $f14, %lo 29 ; CHECK: lwc1 $f12, %lo 41 ; CHECK: lwc1 $f14, %lo 89 ; CHECK: lwc1 $f12, %lo 153 ; CHECK: lwc1 $f12, %lo 154 ; CHECK: lwc1 $f14, %lo 166 ; CHECK: lwc1 $f12, %lo 181 ; CHECK: lwc1 $f14, %lo 192 ; CHECK: lwc1 $f12, %l [all...] |
2009-11-16-CstPoolLoad.ll | 8 ; CHECK: lwc1 $f0, %lo($CPI0_0)($2)
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mips64fpldst.ll | 13 ; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) 16 ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
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/external/webkit/Source/JavaScriptCore/assembler/ |
MacroAssemblerMIPS.h | [all...] |
MIPSAssembler.h | 539 void lwc1(FPRegisterID ft, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
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/external/llvm/lib/Target/Mips/ |
MipsISelDAGToDAG.cpp | 165 // lwc1 $f0, 0($2) 168 // lwc1 $f0, %lo($CPI1_0)($2)
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MipsInstrFPU.td | 194 def LWC1_P8 : FPLoad<0x31, "lwc1", load, FGR32, mem64>; 201 def LWC1 : FPLoad<0x31, "lwc1", load, FGR32, mem>;
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MipsInstrInfo.cpp | 54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 205 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
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/external/v8/src/mips/ |
constants-mips.cc | 334 case LWC1:
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disasm-mips.cc | 878 case LWC1: 879 Format(instr, "lwc1 'ft, 'imm16s('rs)");
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assembler-mips.cc | 1586 void Assembler::lwc1(FPURegister fd, const MemOperand& src) { function in class:v8::internal::Assembler [all...] |
constants-mips.h | 240 LWC1 = ((6 << 3) + 1) << kOpcodeShift,
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assembler-mips.h | 672 void lwc1(FPURegister fd, const MemOperand& src); [all...] |
simulator-mips.cc | [all...] |
macro-assembler-mips.cc | 857 lwc1(double_scratch, FieldMemOperand(source, HeapNumber::kMantissaOffset)); [all...] |
/external/webkit/Source/JavaScriptCore/ |
ChangeLog-2010-05-24 | [all...] |