1 /* 2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7 /* File: armv5te/header.S */ 8 /* 9 * Copyright (C) 2008 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24 /* 25 * ARMv5 definitions and declarations. 26 */ 27 28 /* 29 ARM EABI general notes: 30 31 r0-r3 hold first 4 args to a method; they are not preserved across method calls 32 r4-r8 are available for general use 33 r9 is given special treatment in some situations, but not for us 34 r10 (sl) seems to be generally available 35 r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36 r12 (ip) is scratch -- not preserved across method calls 37 r13 (sp) should be managed carefully in case a signal arrives 38 r14 (lr) must be preserved 39 r15 (pc) can be tinkered with directly 40 41 r0 holds returns of <= 4 bytes 42 r0-r1 hold returns of 8 bytes, low word in r0 43 44 Callee must save/restore r4+ (except r12) if it modifies them. If VFP 45 is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46 s0-s15 (d0-d7, q0-a3) do not need to be. 47 48 Stack is "full descending". Only the arguments that don't fit in the first 4 49 registers are placed on the stack. "sp" points at the first stacked argument 50 (i.e. the 5th arg). 51 52 VFP: single-precision results in s0, double-precision results in d0. 53 54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 55 64-bit quantities (long long, double) must be 64-bit aligned. 56 */ 57 58 /* 59 Mterp and ARM notes: 60 61 The following registers have fixed assignments: 62 63 reg nick purpose 64 r4 rPC interpreted program counter, used for fetching instructions 65 r5 rFP interpreted frame pointer, used for accessing locals and args 66 r6 rSELF self (Thread) pointer 67 r7 rINST first 16-bit code unit of current instruction 68 r8 rIBASE interpreted instruction base pointer, used for computed goto 69 70 Macros are provided for common operations. Each macro MUST emit only 71 one instruction to make instruction-counting easier. They MUST NOT alter 72 unspecified registers or condition codes. 73 */ 74 75 /* single-purpose registers, given names for clarity */ 76 #define rPC r4 77 #define rFP r5 78 #define rSELF r6 79 #define rINST r7 80 #define rIBASE r8 81 82 /* save/restore the PC and/or FP from the thread struct */ 83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc] 84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc] 85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame] 86 #define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_curFrame] 87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP} 88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP} 89 90 /* 91 * "export" the PC to the stack frame, f/b/o future exception objects. Must 92 * be done *before* something throws. 93 * 94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96 * 97 * It's okay to do this more than once. 98 */ 99 #define EXPORT_PC() \ 100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101 102 /* 103 * Given a frame pointer, find the stack save area. 104 * 105 * In C this is "((StackSaveArea*)(_fp) -1)". 106 */ 107 #define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108 sub _reg, _fpreg, #sizeofStackSaveArea 109 110 /* 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112 */ 113 #define FETCH_INST() ldrh rINST, [rPC] 114 115 /* 116 * Fetch the next instruction from the specified offset. Advances rPC 117 * to point to the next instruction. "_count" is in 16-bit code units. 118 * 119 * Because of the limited size of immediate constants on ARM, this is only 120 * suitable for small forward movements (i.e. don't try to implement "goto" 121 * with this). 122 * 123 * This must come AFTER anything that can throw an exception, or the 124 * exception catch may miss. (This also implies that it must come after 125 * EXPORT_PC().) 126 */ 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 128 129 /* 130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132 */ 133 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134 ldrh _dreg, [_sreg, #((_count)*2)]! 135 136 /* 137 * Fetch the next instruction from an offset specified by _reg. Updates 138 * rPC to point to the next instruction. "_reg" must specify the distance 139 * in bytes, *not* 16-bit code units, and may be a signed value. 140 * 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 142 * bits that hold the shift distance are used for the half/byte/sign flags. 143 * In some cases we can pre-double _reg for free, so we require a byte offset 144 * here. 145 */ 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147 148 /* 149 * Fetch a half-word code unit from an offset past the current PC. The 150 * "_count" value is in 16-bit code units. Does not advance rPC. 151 * 152 * The "_S" variant works the same but treats the value as signed. 153 */ 154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)] 155 #define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)] 156 157 /* 158 * Fetch one byte from an offset past the current PC. Pass in the same 159 * "_count" as you would for FETCH, and an additional 0/1 indicating which 160 * byte of the halfword you want (lo/hi). 161 */ 162 #define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))] 163 164 /* 165 * Put the instruction's opcode field into the specified register. 166 */ 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168 169 /* 170 * Put the prefetched instruction's opcode field into the specified register. 171 */ 172 #define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173 174 /* 175 * Begin executing the opcode in _reg. Because this only jumps within the 176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177 */ 178 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179 #define GOTO_OPCODE_BASE(_base,_reg) add pc, _base, _reg, lsl #6 180 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 181 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 182 183 /* 184 * Get/set the 32-bit value from a Dalvik register. 185 */ 186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 187 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 188 189 /* 190 * Convert a virtual register index into an address. 191 */ 192 #define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 193 add _reg, rFP, _vreg, lsl #2 194 195 /* 196 * This is a #include, not a %include, because we want the C pre-processor 197 * to expand the macros into assembler assignment statements. 198 */ 199 #include "../common/asm-constants.h" 200 201 #if defined(WITH_JIT) 202 #include "../common/jit-config.h" 203 #endif 204 205 /* File: armv5te/platform.S */ 206 /* 207 * =========================================================================== 208 * CPU-version-specific defines 209 * =========================================================================== 210 */ 211 212 /* 213 * Macro for data memory barrier; not meaningful pre-ARMv6K. 214 */ 215 .macro SMP_DMB 216 .endm 217 218 /* 219 * Macro for data memory barrier; not meaningful pre-ARMv6K. 220 */ 221 .macro SMP_DMB_ST 222 .endm 223 224 /* File: armv5te/entry.S */ 225 /* 226 * Copyright (C) 2008 The Android Open Source Project 227 * 228 * Licensed under the Apache License, Version 2.0 (the "License"); 229 * you may not use this file except in compliance with the License. 230 * You may obtain a copy of the License at 231 * 232 * http://www.apache.org/licenses/LICENSE-2.0 233 * 234 * Unless required by applicable law or agreed to in writing, software 235 * distributed under the License is distributed on an "AS IS" BASIS, 236 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 237 * See the License for the specific language governing permissions and 238 * limitations under the License. 239 */ 240 /* 241 * Interpreter entry point. 242 */ 243 244 /* 245 * We don't have formal stack frames, so gdb scans upward in the code 246 * to find the start of the function (a label with the %function type), 247 * and then looks at the next few instructions to figure out what 248 * got pushed onto the stack. From this it figures out how to restore 249 * the registers, including PC, for the previous stack frame. If gdb 250 * sees a non-function label, it stops scanning, so either we need to 251 * have nothing but assembler-local labels between the entry point and 252 * the break, or we need to fake it out. 253 * 254 * When this is defined, we add some stuff to make gdb less confused. 255 */ 256 #define ASSIST_DEBUGGER 1 257 258 .text 259 .align 2 260 .global dvmMterpStdRun 261 .type dvmMterpStdRun, %function 262 263 /* 264 * On entry: 265 * r0 Thread* self 266 * 267 * The return comes via a call to dvmMterpStdBail(). 268 */ 269 dvmMterpStdRun: 270 #define MTERP_ENTRY1 \ 271 .save {r4-r10,fp,lr}; \ 272 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 273 #define MTERP_ENTRY2 \ 274 .pad #4; \ 275 sub sp, sp, #4 @ align 64 276 277 .fnstart 278 MTERP_ENTRY1 279 MTERP_ENTRY2 280 281 /* save stack pointer, add magic word for debuggerd */ 282 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return 283 284 /* set up "named" registers, figure out entry point */ 285 mov rSELF, r0 @ set rSELF 286 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread" 287 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE 288 289 #if defined(WITH_JIT) 290 .LentryInstr: 291 /* Entry is always a possible trace start */ 292 ldr r0, [rSELF, #offThread_pJitProfTable] 293 FETCH_INST() 294 mov r1, #0 @ prepare the value for the new state 295 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 296 cmp r0,#0 @ is profiling disabled? 297 #if !defined(WITH_SELF_VERIFICATION) 298 bne common_updateProfile @ profiling is enabled 299 #else 300 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state 301 beq 1f @ profiling is disabled 302 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 303 cmp r3, #kSVSTraceSelect @ hot trace following? 304 moveq r2,#kJitTSelectRequestHot @ ask for trace selection 305 beq common_selectTrace @ go build the trace 306 cmp r3, #kSVSNoProfile @ don't profile the next instruction? 307 beq 1f @ intrepret the next instruction 308 b common_updateProfile @ collect profiles 309 #endif 310 1: 311 GET_INST_OPCODE(ip) 312 GOTO_OPCODE(ip) 313 #else 314 /* start executing the instruction at rPC */ 315 FETCH_INST() @ load rINST from rPC 316 GET_INST_OPCODE(ip) @ extract opcode from rINST 317 GOTO_OPCODE(ip) @ jump to next instruction 318 #endif 319 320 .Lbad_arg: 321 ldr r0, strBadEntryPoint 322 @ r1 holds value of entryPoint 323 bl printf 324 bl dvmAbort 325 .fnend 326 .size dvmMterpStdRun, .-dvmMterpStdRun 327 328 329 .global dvmMterpStdBail 330 .type dvmMterpStdBail, %function 331 332 /* 333 * Restore the stack pointer and PC from the save point established on entry. 334 * This is essentially the same as a longjmp, but should be cheaper. The 335 * last instruction causes us to return to whoever called dvmMterpStdRun. 336 * 337 * We pushed some registers on the stack in dvmMterpStdRun, then saved 338 * SP and LR. Here we restore SP, restore the registers, and then restore 339 * LR to PC. 340 * 341 * On entry: 342 * r0 Thread* self 343 */ 344 dvmMterpStdBail: 345 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP 346 add sp, sp, #4 @ un-align 64 347 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return 348 349 350 /* 351 * String references. 352 */ 353 strBadEntryPoint: 354 .word .LstrBadEntryPoint 355 356 357 .global dvmAsmInstructionStart 358 .type dvmAsmInstructionStart, %function 359 dvmAsmInstructionStart = .L_OP_NOP 360 .text 361 362 /* ------------------------------ */ 363 .balign 64 364 .L_OP_NOP: /* 0x00 */ 365 /* File: armv5te/OP_NOP.S */ 366 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 367 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 368 GOTO_OPCODE(ip) @ execute it 369 370 #ifdef ASSIST_DEBUGGER 371 /* insert fake function header to help gdb find the stack frame */ 372 .type dalvik_inst, %function 373 dalvik_inst: 374 .fnstart 375 MTERP_ENTRY1 376 MTERP_ENTRY2 377 .fnend 378 #endif 379 380 /* ------------------------------ */ 381 .balign 64 382 .L_OP_MOVE: /* 0x01 */ 383 /* File: armv5te/OP_MOVE.S */ 384 /* for move, move-object, long-to-int */ 385 /* op vA, vB */ 386 mov r1, rINST, lsr #12 @ r1<- B from 15:12 387 mov r0, rINST, lsr #8 @ r0<- A from 11:8 388 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 389 GET_VREG(r2, r1) @ r2<- fp[B] 390 and r0, r0, #15 391 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 392 SET_VREG(r2, r0) @ fp[A]<- r2 393 GOTO_OPCODE(ip) @ execute next instruction 394 395 /* ------------------------------ */ 396 .balign 64 397 .L_OP_MOVE_FROM16: /* 0x02 */ 398 /* File: armv5te/OP_MOVE_FROM16.S */ 399 /* for: move/from16, move-object/from16 */ 400 /* op vAA, vBBBB */ 401 FETCH(r1, 1) @ r1<- BBBB 402 mov r0, rINST, lsr #8 @ r0<- AA 403 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 404 GET_VREG(r2, r1) @ r2<- fp[BBBB] 405 GET_INST_OPCODE(ip) @ extract opcode from rINST 406 SET_VREG(r2, r0) @ fp[AA]<- r2 407 GOTO_OPCODE(ip) @ jump to next instruction 408 409 /* ------------------------------ */ 410 .balign 64 411 .L_OP_MOVE_16: /* 0x03 */ 412 /* File: armv5te/OP_MOVE_16.S */ 413 /* for: move/16, move-object/16 */ 414 /* op vAAAA, vBBBB */ 415 FETCH(r1, 2) @ r1<- BBBB 416 FETCH(r0, 1) @ r0<- AAAA 417 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 418 GET_VREG(r2, r1) @ r2<- fp[BBBB] 419 GET_INST_OPCODE(ip) @ extract opcode from rINST 420 SET_VREG(r2, r0) @ fp[AAAA]<- r2 421 GOTO_OPCODE(ip) @ jump to next instruction 422 423 /* ------------------------------ */ 424 .balign 64 425 .L_OP_MOVE_WIDE: /* 0x04 */ 426 /* File: armv5te/OP_MOVE_WIDE.S */ 427 /* move-wide vA, vB */ 428 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 429 mov r2, rINST, lsr #8 @ r2<- A(+) 430 mov r3, rINST, lsr #12 @ r3<- B 431 and r2, r2, #15 432 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 433 add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 434 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 435 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 436 GET_INST_OPCODE(ip) @ extract opcode from rINST 437 stmia r2, {r0-r1} @ fp[A]<- r0/r1 438 GOTO_OPCODE(ip) @ jump to next instruction 439 440 /* ------------------------------ */ 441 .balign 64 442 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 443 /* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 444 /* move-wide/from16 vAA, vBBBB */ 445 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 446 FETCH(r3, 1) @ r3<- BBBB 447 mov r2, rINST, lsr #8 @ r2<- AA 448 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 449 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 450 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 451 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 452 GET_INST_OPCODE(ip) @ extract opcode from rINST 453 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 454 GOTO_OPCODE(ip) @ jump to next instruction 455 456 /* ------------------------------ */ 457 .balign 64 458 .L_OP_MOVE_WIDE_16: /* 0x06 */ 459 /* File: armv5te/OP_MOVE_WIDE_16.S */ 460 /* move-wide/16 vAAAA, vBBBB */ 461 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 462 FETCH(r3, 2) @ r3<- BBBB 463 FETCH(r2, 1) @ r2<- AAAA 464 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 465 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 466 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 467 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 468 GET_INST_OPCODE(ip) @ extract opcode from rINST 469 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 470 GOTO_OPCODE(ip) @ jump to next instruction 471 472 /* ------------------------------ */ 473 .balign 64 474 .L_OP_MOVE_OBJECT: /* 0x07 */ 475 /* File: armv5te/OP_MOVE_OBJECT.S */ 476 /* File: armv5te/OP_MOVE.S */ 477 /* for move, move-object, long-to-int */ 478 /* op vA, vB */ 479 mov r1, rINST, lsr #12 @ r1<- B from 15:12 480 mov r0, rINST, lsr #8 @ r0<- A from 11:8 481 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 482 GET_VREG(r2, r1) @ r2<- fp[B] 483 and r0, r0, #15 484 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 485 SET_VREG(r2, r0) @ fp[A]<- r2 486 GOTO_OPCODE(ip) @ execute next instruction 487 488 489 /* ------------------------------ */ 490 .balign 64 491 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 492 /* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 493 /* File: armv5te/OP_MOVE_FROM16.S */ 494 /* for: move/from16, move-object/from16 */ 495 /* op vAA, vBBBB */ 496 FETCH(r1, 1) @ r1<- BBBB 497 mov r0, rINST, lsr #8 @ r0<- AA 498 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 499 GET_VREG(r2, r1) @ r2<- fp[BBBB] 500 GET_INST_OPCODE(ip) @ extract opcode from rINST 501 SET_VREG(r2, r0) @ fp[AA]<- r2 502 GOTO_OPCODE(ip) @ jump to next instruction 503 504 505 /* ------------------------------ */ 506 .balign 64 507 .L_OP_MOVE_OBJECT_16: /* 0x09 */ 508 /* File: armv5te/OP_MOVE_OBJECT_16.S */ 509 /* File: armv5te/OP_MOVE_16.S */ 510 /* for: move/16, move-object/16 */ 511 /* op vAAAA, vBBBB */ 512 FETCH(r1, 2) @ r1<- BBBB 513 FETCH(r0, 1) @ r0<- AAAA 514 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 515 GET_VREG(r2, r1) @ r2<- fp[BBBB] 516 GET_INST_OPCODE(ip) @ extract opcode from rINST 517 SET_VREG(r2, r0) @ fp[AAAA]<- r2 518 GOTO_OPCODE(ip) @ jump to next instruction 519 520 521 /* ------------------------------ */ 522 .balign 64 523 .L_OP_MOVE_RESULT: /* 0x0a */ 524 /* File: armv5te/OP_MOVE_RESULT.S */ 525 /* for: move-result, move-result-object */ 526 /* op vAA */ 527 mov r2, rINST, lsr #8 @ r2<- AA 528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 529 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 530 GET_INST_OPCODE(ip) @ extract opcode from rINST 531 SET_VREG(r0, r2) @ fp[AA]<- r0 532 GOTO_OPCODE(ip) @ jump to next instruction 533 534 /* ------------------------------ */ 535 .balign 64 536 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 537 /* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 538 /* move-result-wide vAA */ 539 mov r2, rINST, lsr #8 @ r2<- AA 540 add r3, rSELF, #offThread_retval @ r3<- &self->retval 541 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 542 ldmia r3, {r0-r1} @ r0/r1<- retval.j 543 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 544 GET_INST_OPCODE(ip) @ extract opcode from rINST 545 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 546 GOTO_OPCODE(ip) @ jump to next instruction 547 548 /* ------------------------------ */ 549 .balign 64 550 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 551 /* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 552 /* File: armv5te/OP_MOVE_RESULT.S */ 553 /* for: move-result, move-result-object */ 554 /* op vAA */ 555 mov r2, rINST, lsr #8 @ r2<- AA 556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 557 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i 558 GET_INST_OPCODE(ip) @ extract opcode from rINST 559 SET_VREG(r0, r2) @ fp[AA]<- r0 560 GOTO_OPCODE(ip) @ jump to next instruction 561 562 563 /* ------------------------------ */ 564 .balign 64 565 .L_OP_MOVE_EXCEPTION: /* 0x0d */ 566 /* File: armv5te/OP_MOVE_EXCEPTION.S */ 567 /* move-exception vAA */ 568 mov r2, rINST, lsr #8 @ r2<- AA 569 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass 570 mov r1, #0 @ r1<- 0 571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 572 SET_VREG(r3, r2) @ fp[AA]<- exception obj 573 GET_INST_OPCODE(ip) @ extract opcode from rINST 574 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass 575 GOTO_OPCODE(ip) @ jump to next instruction 576 577 /* ------------------------------ */ 578 .balign 64 579 .L_OP_RETURN_VOID: /* 0x0e */ 580 /* File: armv5te/OP_RETURN_VOID.S */ 581 b common_returnFromMethod 582 583 /* ------------------------------ */ 584 .balign 64 585 .L_OP_RETURN: /* 0x0f */ 586 /* File: armv5te/OP_RETURN.S */ 587 /* 588 * Return a 32-bit value. Copies the return value into the "thread" 589 * structure, then jumps to the return handler. 590 * 591 * for: return, return-object 592 */ 593 /* op vAA */ 594 mov r2, rINST, lsr #8 @ r2<- AA 595 GET_VREG(r0, r2) @ r0<- vAA 596 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 597 b common_returnFromMethod 598 599 /* ------------------------------ */ 600 .balign 64 601 .L_OP_RETURN_WIDE: /* 0x10 */ 602 /* File: armv5te/OP_RETURN_WIDE.S */ 603 /* 604 * Return a 64-bit value. Copies the return value into the "thread" 605 * structure, then jumps to the return handler. 606 */ 607 /* return-wide vAA */ 608 mov r2, rINST, lsr #8 @ r2<- AA 609 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 610 add r3, rSELF, #offThread_retval @ r3<- &self->retval 611 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 612 stmia r3, {r0-r1} @ retval<- r0/r1 613 b common_returnFromMethod 614 615 /* ------------------------------ */ 616 .balign 64 617 .L_OP_RETURN_OBJECT: /* 0x11 */ 618 /* File: armv5te/OP_RETURN_OBJECT.S */ 619 /* File: armv5te/OP_RETURN.S */ 620 /* 621 * Return a 32-bit value. Copies the return value into the "thread" 622 * structure, then jumps to the return handler. 623 * 624 * for: return, return-object 625 */ 626 /* op vAA */ 627 mov r2, rINST, lsr #8 @ r2<- AA 628 GET_VREG(r0, r2) @ r0<- vAA 629 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA 630 b common_returnFromMethod 631 632 633 /* ------------------------------ */ 634 .balign 64 635 .L_OP_CONST_4: /* 0x12 */ 636 /* File: armv5te/OP_CONST_4.S */ 637 /* const/4 vA, #+B */ 638 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 639 mov r0, rINST, lsr #8 @ r0<- A+ 640 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 641 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 642 and r0, r0, #15 643 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 644 SET_VREG(r1, r0) @ fp[A]<- r1 645 GOTO_OPCODE(ip) @ execute next instruction 646 647 /* ------------------------------ */ 648 .balign 64 649 .L_OP_CONST_16: /* 0x13 */ 650 /* File: armv5te/OP_CONST_16.S */ 651 /* const/16 vAA, #+BBBB */ 652 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 653 mov r3, rINST, lsr #8 @ r3<- AA 654 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 655 SET_VREG(r0, r3) @ vAA<- r0 656 GET_INST_OPCODE(ip) @ extract opcode from rINST 657 GOTO_OPCODE(ip) @ jump to next instruction 658 659 /* ------------------------------ */ 660 .balign 64 661 .L_OP_CONST: /* 0x14 */ 662 /* File: armv5te/OP_CONST.S */ 663 /* const vAA, #+BBBBbbbb */ 664 mov r3, rINST, lsr #8 @ r3<- AA 665 FETCH(r0, 1) @ r0<- bbbb (low) 666 FETCH(r1, 2) @ r1<- BBBB (high) 667 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 668 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 669 GET_INST_OPCODE(ip) @ extract opcode from rINST 670 SET_VREG(r0, r3) @ vAA<- r0 671 GOTO_OPCODE(ip) @ jump to next instruction 672 673 /* ------------------------------ */ 674 .balign 64 675 .L_OP_CONST_HIGH16: /* 0x15 */ 676 /* File: armv5te/OP_CONST_HIGH16.S */ 677 /* const/high16 vAA, #+BBBB0000 */ 678 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 679 mov r3, rINST, lsr #8 @ r3<- AA 680 mov r0, r0, lsl #16 @ r0<- BBBB0000 681 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 682 SET_VREG(r0, r3) @ vAA<- r0 683 GET_INST_OPCODE(ip) @ extract opcode from rINST 684 GOTO_OPCODE(ip) @ jump to next instruction 685 686 /* ------------------------------ */ 687 .balign 64 688 .L_OP_CONST_WIDE_16: /* 0x16 */ 689 /* File: armv5te/OP_CONST_WIDE_16.S */ 690 /* const-wide/16 vAA, #+BBBB */ 691 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 692 mov r3, rINST, lsr #8 @ r3<- AA 693 mov r1, r0, asr #31 @ r1<- ssssssss 694 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 695 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 696 GET_INST_OPCODE(ip) @ extract opcode from rINST 697 stmia r3, {r0-r1} @ vAA<- r0/r1 698 GOTO_OPCODE(ip) @ jump to next instruction 699 700 /* ------------------------------ */ 701 .balign 64 702 .L_OP_CONST_WIDE_32: /* 0x17 */ 703 /* File: armv5te/OP_CONST_WIDE_32.S */ 704 /* const-wide/32 vAA, #+BBBBbbbb */ 705 FETCH(r0, 1) @ r0<- 0000bbbb (low) 706 mov r3, rINST, lsr #8 @ r3<- AA 707 FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 708 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 709 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 710 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 711 mov r1, r0, asr #31 @ r1<- ssssssss 712 GET_INST_OPCODE(ip) @ extract opcode from rINST 713 stmia r3, {r0-r1} @ vAA<- r0/r1 714 GOTO_OPCODE(ip) @ jump to next instruction 715 716 /* ------------------------------ */ 717 .balign 64 718 .L_OP_CONST_WIDE: /* 0x18 */ 719 /* File: armv5te/OP_CONST_WIDE.S */ 720 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 721 FETCH(r0, 1) @ r0<- bbbb (low) 722 FETCH(r1, 2) @ r1<- BBBB (low middle) 723 FETCH(r2, 3) @ r2<- hhhh (high middle) 724 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 725 FETCH(r3, 4) @ r3<- HHHH (high) 726 mov r9, rINST, lsr #8 @ r9<- AA 727 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 728 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 729 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 730 GET_INST_OPCODE(ip) @ extract opcode from rINST 731 stmia r9, {r0-r1} @ vAA<- r0/r1 732 GOTO_OPCODE(ip) @ jump to next instruction 733 734 /* ------------------------------ */ 735 .balign 64 736 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 737 /* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 738 /* const-wide/high16 vAA, #+BBBB000000000000 */ 739 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 740 mov r3, rINST, lsr #8 @ r3<- AA 741 mov r0, #0 @ r0<- 00000000 742 mov r1, r1, lsl #16 @ r1<- BBBB0000 743 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 744 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 745 GET_INST_OPCODE(ip) @ extract opcode from rINST 746 stmia r3, {r0-r1} @ vAA<- r0/r1 747 GOTO_OPCODE(ip) @ jump to next instruction 748 749 /* ------------------------------ */ 750 .balign 64 751 .L_OP_CONST_STRING: /* 0x1a */ 752 /* File: armv5te/OP_CONST_STRING.S */ 753 /* const/string vAA, String@BBBB */ 754 FETCH(r1, 1) @ r1<- BBBB 755 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 756 mov r9, rINST, lsr #8 @ r9<- AA 757 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 758 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 759 cmp r0, #0 @ not yet resolved? 760 beq .LOP_CONST_STRING_resolve 761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 762 GET_INST_OPCODE(ip) @ extract opcode from rINST 763 SET_VREG(r0, r9) @ vAA<- r0 764 GOTO_OPCODE(ip) @ jump to next instruction 765 766 /* ------------------------------ */ 767 .balign 64 768 .L_OP_CONST_STRING_JUMBO: /* 0x1b */ 769 /* File: armv5te/OP_CONST_STRING_JUMBO.S */ 770 /* const/string vAA, String@BBBBBBBB */ 771 FETCH(r0, 1) @ r0<- bbbb (low) 772 FETCH(r1, 2) @ r1<- BBBB (high) 773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 774 mov r9, rINST, lsr #8 @ r9<- AA 775 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 776 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 777 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 778 cmp r0, #0 779 beq .LOP_CONST_STRING_JUMBO_resolve 780 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 781 GET_INST_OPCODE(ip) @ extract opcode from rINST 782 SET_VREG(r0, r9) @ vAA<- r0 783 GOTO_OPCODE(ip) @ jump to next instruction 784 785 /* ------------------------------ */ 786 .balign 64 787 .L_OP_CONST_CLASS: /* 0x1c */ 788 /* File: armv5te/OP_CONST_CLASS.S */ 789 /* const/class vAA, Class@BBBB */ 790 FETCH(r1, 1) @ r1<- BBBB 791 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex 792 mov r9, rINST, lsr #8 @ r9<- AA 793 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 794 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 795 cmp r0, #0 @ not yet resolved? 796 beq .LOP_CONST_CLASS_resolve 797 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 798 GET_INST_OPCODE(ip) @ extract opcode from rINST 799 SET_VREG(r0, r9) @ vAA<- r0 800 GOTO_OPCODE(ip) @ jump to next instruction 801 802 /* ------------------------------ */ 803 .balign 64 804 .L_OP_MONITOR_ENTER: /* 0x1d */ 805 /* File: armv5te/OP_MONITOR_ENTER.S */ 806 /* 807 * Synchronize on an object. 808 */ 809 /* monitor-enter vAA */ 810 mov r2, rINST, lsr #8 @ r2<- AA 811 GET_VREG(r1, r2) @ r1<- vAA (object) 812 mov r0, rSELF @ r0<- self 813 cmp r1, #0 @ null object? 814 EXPORT_PC() @ need for precise GC 815 beq common_errNullObject @ null object, throw an exception 816 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 817 bl dvmLockObject @ call(self, obj) 818 GET_INST_OPCODE(ip) @ extract opcode from rINST 819 GOTO_OPCODE(ip) @ jump to next instruction 820 821 /* ------------------------------ */ 822 .balign 64 823 .L_OP_MONITOR_EXIT: /* 0x1e */ 824 /* File: armv5te/OP_MONITOR_EXIT.S */ 825 /* 826 * Unlock an object. 827 * 828 * Exceptions that occur when unlocking a monitor need to appear as 829 * if they happened at the following instruction. See the Dalvik 830 * instruction spec. 831 */ 832 /* monitor-exit vAA */ 833 mov r2, rINST, lsr #8 @ r2<- AA 834 EXPORT_PC() @ before fetch: export the PC 835 GET_VREG(r1, r2) @ r1<- vAA (object) 836 cmp r1, #0 @ null object? 837 beq 1f @ yes 838 mov r0, rSELF @ r0<- self 839 bl dvmUnlockObject @ r0<- success for unlock(self, obj) 840 cmp r0, #0 @ failed? 841 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 842 beq common_exceptionThrown @ yes, exception is pending 843 GET_INST_OPCODE(ip) @ extract opcode from rINST 844 GOTO_OPCODE(ip) @ jump to next instruction 845 1: 846 FETCH_ADVANCE_INST(1) @ advance before throw 847 b common_errNullObject 848 849 /* ------------------------------ */ 850 .balign 64 851 .L_OP_CHECK_CAST: /* 0x1f */ 852 /* File: armv5te/OP_CHECK_CAST.S */ 853 /* 854 * Check to see if a cast from one class to another is allowed. 855 */ 856 /* check-cast vAA, class@BBBB */ 857 mov r3, rINST, lsr #8 @ r3<- AA 858 FETCH(r2, 1) @ r2<- BBBB 859 GET_VREG(r9, r3) @ r9<- object 860 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 861 cmp r9, #0 @ is object null? 862 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 863 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 864 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 865 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 866 cmp r1, #0 @ have we resolved this before? 867 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 868 .LOP_CHECK_CAST_resolved: 869 cmp r0, r1 @ same class (trivial success)? 870 bne .LOP_CHECK_CAST_fullcheck @ no, do full check 871 .LOP_CHECK_CAST_okay: 872 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 873 GET_INST_OPCODE(ip) @ extract opcode from rINST 874 GOTO_OPCODE(ip) @ jump to next instruction 875 876 /* ------------------------------ */ 877 .balign 64 878 .L_OP_INSTANCE_OF: /* 0x20 */ 879 /* File: armv5te/OP_INSTANCE_OF.S */ 880 /* 881 * Check to see if an object reference is an instance of a class. 882 * 883 * Most common situation is a non-null object, being compared against 884 * an already-resolved class. 885 */ 886 /* instance-of vA, vB, class@CCCC */ 887 mov r3, rINST, lsr #12 @ r3<- B 888 mov r9, rINST, lsr #8 @ r9<- A+ 889 GET_VREG(r0, r3) @ r0<- vB (object) 890 and r9, r9, #15 @ r9<- A 891 cmp r0, #0 @ is object null? 892 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 893 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 894 FETCH(r3, 1) @ r3<- CCCC 895 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 896 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 897 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 898 cmp r1, #0 @ have we resolved this before? 899 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 900 .LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 901 cmp r0, r1 @ same class (trivial success)? 902 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 903 b .LOP_INSTANCE_OF_fullcheck @ no, do full check 904 905 /* ------------------------------ */ 906 .balign 64 907 .L_OP_ARRAY_LENGTH: /* 0x21 */ 908 /* File: armv5te/OP_ARRAY_LENGTH.S */ 909 /* 910 * Return the length of an array. 911 */ 912 mov r1, rINST, lsr #12 @ r1<- B 913 mov r2, rINST, lsr #8 @ r2<- A+ 914 GET_VREG(r0, r1) @ r0<- vB (object ref) 915 and r2, r2, #15 @ r2<- A 916 cmp r0, #0 @ is object null? 917 beq common_errNullObject @ yup, fail 918 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 919 ldr r3, [r0, #offArrayObject_length] @ r3<- array length 920 GET_INST_OPCODE(ip) @ extract opcode from rINST 921 SET_VREG(r3, r2) @ vB<- length 922 GOTO_OPCODE(ip) @ jump to next instruction 923 924 /* ------------------------------ */ 925 .balign 64 926 .L_OP_NEW_INSTANCE: /* 0x22 */ 927 /* File: armv5te/OP_NEW_INSTANCE.S */ 928 /* 929 * Create a new instance of a class. 930 */ 931 /* new-instance vAA, class@BBBB */ 932 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 933 FETCH(r1, 1) @ r1<- BBBB 934 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 935 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 936 #if defined(WITH_JIT) 937 add r10, r3, r1, lsl #2 @ r10<- &resolved_class 938 #endif 939 EXPORT_PC() @ req'd for init, resolve, alloc 940 cmp r0, #0 @ already resolved? 941 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 942 .LOP_NEW_INSTANCE_resolved: @ r0=class 943 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 944 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 945 bne .LOP_NEW_INSTANCE_needinit @ no, init class now 946 .LOP_NEW_INSTANCE_initialized: @ r0=class 947 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 948 bl dvmAllocObject @ r0<- new object 949 b .LOP_NEW_INSTANCE_finish @ continue 950 951 /* ------------------------------ */ 952 .balign 64 953 .L_OP_NEW_ARRAY: /* 0x23 */ 954 /* File: armv5te/OP_NEW_ARRAY.S */ 955 /* 956 * Allocate an array of objects, specified with the array class 957 * and a count. 958 * 959 * The verifier guarantees that this is an array class, so we don't 960 * check for it here. 961 */ 962 /* new-array vA, vB, class@CCCC */ 963 mov r0, rINST, lsr #12 @ r0<- B 964 FETCH(r2, 1) @ r2<- CCCC 965 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 966 GET_VREG(r1, r0) @ r1<- vB (array length) 967 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 968 cmp r1, #0 @ check length 969 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 970 bmi common_errNegativeArraySize @ negative length, bail - len in r1 971 cmp r0, #0 @ already resolved? 972 EXPORT_PC() @ req'd for resolve, alloc 973 bne .LOP_NEW_ARRAY_finish @ resolved, continue 974 b .LOP_NEW_ARRAY_resolve @ do resolve now 975 976 /* ------------------------------ */ 977 .balign 64 978 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 979 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 980 /* 981 * Create a new array with elements filled from registers. 982 * 983 * for: filled-new-array, filled-new-array/range 984 */ 985 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 986 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 987 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 988 FETCH(r1, 1) @ r1<- BBBB 989 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 990 EXPORT_PC() @ need for resolve and alloc 991 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 992 mov r10, rINST, lsr #8 @ r10<- AA or BA 993 cmp r0, #0 @ already resolved? 994 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 995 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 996 mov r2, #0 @ r2<- false 997 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 998 bl dvmResolveClass @ r0<- call(clazz, ref) 999 cmp r0, #0 @ got null? 1000 beq common_exceptionThrown @ yes, handle exception 1001 b .LOP_FILLED_NEW_ARRAY_continue 1002 1003 /* ------------------------------ */ 1004 .balign 64 1005 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1006 /* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1007 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1008 /* 1009 * Create a new array with elements filled from registers. 1010 * 1011 * for: filled-new-array, filled-new-array/range 1012 */ 1013 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1014 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1015 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 1016 FETCH(r1, 1) @ r1<- BBBB 1017 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1018 EXPORT_PC() @ need for resolve and alloc 1019 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1020 mov r10, rINST, lsr #8 @ r10<- AA or BA 1021 cmp r0, #0 @ already resolved? 1022 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1023 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 1024 mov r2, #0 @ r2<- false 1025 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1026 bl dvmResolveClass @ r0<- call(clazz, ref) 1027 cmp r0, #0 @ got null? 1028 beq common_exceptionThrown @ yes, handle exception 1029 b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1030 1031 1032 /* ------------------------------ */ 1033 .balign 64 1034 .L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1035 /* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1036 /* fill-array-data vAA, +BBBBBBBB */ 1037 FETCH(r0, 1) @ r0<- bbbb (lo) 1038 FETCH(r1, 2) @ r1<- BBBB (hi) 1039 mov r3, rINST, lsr #8 @ r3<- AA 1040 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1041 GET_VREG(r0, r3) @ r0<- vAA (array object) 1042 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1043 EXPORT_PC(); 1044 bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1045 cmp r0, #0 @ 0 means an exception is thrown 1046 beq common_exceptionThrown @ has exception 1047 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1048 GET_INST_OPCODE(ip) @ extract opcode from rINST 1049 GOTO_OPCODE(ip) @ jump to next instruction 1050 1051 /* ------------------------------ */ 1052 .balign 64 1053 .L_OP_THROW: /* 0x27 */ 1054 /* File: armv5te/OP_THROW.S */ 1055 /* 1056 * Throw an exception object in the current thread. 1057 */ 1058 /* throw vAA */ 1059 mov r2, rINST, lsr #8 @ r2<- AA 1060 GET_VREG(r1, r2) @ r1<- vAA (exception object) 1061 EXPORT_PC() @ exception handler can throw 1062 cmp r1, #0 @ null object? 1063 beq common_errNullObject @ yes, throw an NPE instead 1064 @ bypass dvmSetException, just store it 1065 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj 1066 b common_exceptionThrown 1067 1068 /* ------------------------------ */ 1069 .balign 64 1070 .L_OP_GOTO: /* 0x28 */ 1071 /* File: armv5te/OP_GOTO.S */ 1072 /* 1073 * Unconditional branch, 8-bit offset. 1074 * 1075 * The branch distance is a signed code-unit offset, which we need to 1076 * double to get a byte offset. 1077 */ 1078 /* goto +AA */ 1079 /* tuning: use sbfx for 6t2+ targets */ 1080 mov r0, rINST, lsl #16 @ r0<- AAxx0000 1081 movs r1, r0, asr #24 @ r1<- ssssssAA (sign-extended) 1082 add r2, r1, r1 @ r2<- byte offset, set flags 1083 @ If backwards branch refresh rIBASE 1084 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1085 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1086 #if defined(WITH_JIT) 1087 ldr r0, [rSELF, #offThread_pJitProfTable] 1088 bmi common_testUpdateProfile @ (r0) check for trace hotness 1089 #endif 1090 GET_INST_OPCODE(ip) @ extract opcode from rINST 1091 GOTO_OPCODE(ip) @ jump to next instruction 1092 1093 /* ------------------------------ */ 1094 .balign 64 1095 .L_OP_GOTO_16: /* 0x29 */ 1096 /* File: armv5te/OP_GOTO_16.S */ 1097 /* 1098 * Unconditional branch, 16-bit offset. 1099 * 1100 * The branch distance is a signed code-unit offset, which we need to 1101 * double to get a byte offset. 1102 */ 1103 /* goto/16 +AAAA */ 1104 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1105 adds r1, r0, r0 @ r1<- byte offset, flags set 1106 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1107 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1108 #if defined(WITH_JIT) 1109 ldr r0, [rSELF, #offThread_pJitProfTable] 1110 bmi common_testUpdateProfile @ (r0) hot trace head? 1111 #endif 1112 GET_INST_OPCODE(ip) @ extract opcode from rINST 1113 GOTO_OPCODE(ip) @ jump to next instruction 1114 1115 /* ------------------------------ */ 1116 .balign 64 1117 .L_OP_GOTO_32: /* 0x2a */ 1118 /* File: armv5te/OP_GOTO_32.S */ 1119 /* 1120 * Unconditional branch, 32-bit offset. 1121 * 1122 * The branch distance is a signed code-unit offset, which we need to 1123 * double to get a byte offset. 1124 * 1125 * Unlike most opcodes, this one is allowed to branch to itself, so 1126 * our "backward branch" test must be "<=0" instead of "<0". Because 1127 * we need the V bit set, we'll use an adds to convert from Dalvik 1128 * offset to byte offset. 1129 */ 1130 /* goto/32 +AAAAAAAA */ 1131 FETCH(r0, 1) @ r0<- aaaa (lo) 1132 FETCH(r1, 2) @ r1<- AAAA (hi) 1133 orr r0, r0, r1, lsl #16 @ r0<- AAAAaaaa 1134 adds r1, r0, r0 @ r1<- byte offset 1135 #if defined(WITH_JIT) 1136 ldr r0, [rSELF, #offThread_pJitProfTable] 1137 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1138 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1139 ble common_testUpdateProfile @ (r0) hot trace head? 1140 #else 1141 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1142 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1143 #endif 1144 GET_INST_OPCODE(ip) @ extract opcode from rINST 1145 GOTO_OPCODE(ip) @ jump to next instruction 1146 1147 /* ------------------------------ */ 1148 .balign 64 1149 .L_OP_PACKED_SWITCH: /* 0x2b */ 1150 /* File: armv5te/OP_PACKED_SWITCH.S */ 1151 /* 1152 * Handle a packed-switch or sparse-switch instruction. In both cases 1153 * we decode it and hand it off to a helper function. 1154 * 1155 * We don't really expect backward branches in a switch statement, but 1156 * they're perfectly legal, so we check for them here. 1157 * 1158 * When the JIT is present, all targets are considered treated as 1159 * a potential trace heads regardless of branch direction. 1160 * 1161 * for: packed-switch, sparse-switch 1162 */ 1163 /* op vAA, +BBBB */ 1164 FETCH(r0, 1) @ r0<- bbbb (lo) 1165 FETCH(r1, 2) @ r1<- BBBB (hi) 1166 mov r3, rINST, lsr #8 @ r3<- AA 1167 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1168 GET_VREG(r1, r3) @ r1<- vAA 1169 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1170 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1171 adds r1, r0, r0 @ r1<- byte offset; clear V 1172 #if defined(WITH_JIT) 1173 ldr r0, [rSELF, #offThread_pJitProfTable] 1174 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1175 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1176 cmp r0, #0 1177 bne common_updateProfile 1178 #else 1179 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1180 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1181 #endif 1182 GET_INST_OPCODE(ip) @ extract opcode from rINST 1183 GOTO_OPCODE(ip) @ jump to next instruction 1184 1185 /* ------------------------------ */ 1186 .balign 64 1187 .L_OP_SPARSE_SWITCH: /* 0x2c */ 1188 /* File: armv5te/OP_SPARSE_SWITCH.S */ 1189 /* File: armv5te/OP_PACKED_SWITCH.S */ 1190 /* 1191 * Handle a packed-switch or sparse-switch instruction. In both cases 1192 * we decode it and hand it off to a helper function. 1193 * 1194 * We don't really expect backward branches in a switch statement, but 1195 * they're perfectly legal, so we check for them here. 1196 * 1197 * When the JIT is present, all targets are considered treated as 1198 * a potential trace heads regardless of branch direction. 1199 * 1200 * for: packed-switch, sparse-switch 1201 */ 1202 /* op vAA, +BBBB */ 1203 FETCH(r0, 1) @ r0<- bbbb (lo) 1204 FETCH(r1, 2) @ r1<- BBBB (hi) 1205 mov r3, rINST, lsr #8 @ r3<- AA 1206 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1207 GET_VREG(r1, r3) @ r1<- vAA 1208 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1209 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1210 adds r1, r0, r0 @ r1<- byte offset; clear V 1211 #if defined(WITH_JIT) 1212 ldr r0, [rSELF, #offThread_pJitProfTable] 1213 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1214 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1215 cmp r0, #0 1216 bne common_updateProfile 1217 #else 1218 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base 1219 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1220 #endif 1221 GET_INST_OPCODE(ip) @ extract opcode from rINST 1222 GOTO_OPCODE(ip) @ jump to next instruction 1223 1224 1225 /* ------------------------------ */ 1226 .balign 64 1227 .L_OP_CMPL_FLOAT: /* 0x2d */ 1228 /* File: arm-vfp/OP_CMPL_FLOAT.S */ 1229 /* 1230 * Compare two floating-point values. Puts 0, 1, or -1 into the 1231 * destination register based on the results of the comparison. 1232 * 1233 * int compare(x, y) { 1234 * if (x == y) { 1235 * return 0; 1236 * } else if (x > y) { 1237 * return 1; 1238 * } else if (x < y) { 1239 * return -1; 1240 * } else { 1241 * return -1; 1242 * } 1243 * } 1244 */ 1245 /* op vAA, vBB, vCC */ 1246 FETCH(r0, 1) @ r0<- CCBB 1247 mov r9, rINST, lsr #8 @ r9<- AA 1248 and r2, r0, #255 @ r2<- BB 1249 mov r3, r0, lsr #8 @ r3<- CC 1250 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1251 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1252 flds s0, [r2] @ s0<- vBB 1253 flds s1, [r3] @ s1<- vCC 1254 fcmpes s0, s1 @ compare (vBB, vCC) 1255 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1256 mvn r0, #0 @ r0<- -1 (default) 1257 GET_INST_OPCODE(ip) @ extract opcode from rINST 1258 fmstat @ export status flags 1259 movgt r0, #1 @ (greater than) r1<- 1 1260 moveq r0, #0 @ (equal) r1<- 0 1261 b .LOP_CMPL_FLOAT_finish @ argh 1262 1263 1264 /* ------------------------------ */ 1265 .balign 64 1266 .L_OP_CMPG_FLOAT: /* 0x2e */ 1267 /* File: arm-vfp/OP_CMPG_FLOAT.S */ 1268 /* 1269 * Compare two floating-point values. Puts 0, 1, or -1 into the 1270 * destination register based on the results of the comparison. 1271 * 1272 * int compare(x, y) { 1273 * if (x == y) { 1274 * return 0; 1275 * } else if (x < y) { 1276 * return -1; 1277 * } else if (x > y) { 1278 * return 1; 1279 * } else { 1280 * return 1; 1281 * } 1282 * } 1283 */ 1284 /* op vAA, vBB, vCC */ 1285 FETCH(r0, 1) @ r0<- CCBB 1286 mov r9, rINST, lsr #8 @ r9<- AA 1287 and r2, r0, #255 @ r2<- BB 1288 mov r3, r0, lsr #8 @ r3<- CC 1289 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1290 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1291 flds s0, [r2] @ s0<- vBB 1292 flds s1, [r3] @ s1<- vCC 1293 fcmpes s0, s1 @ compare (vBB, vCC) 1294 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1295 mov r0, #1 @ r0<- 1 (default) 1296 GET_INST_OPCODE(ip) @ extract opcode from rINST 1297 fmstat @ export status flags 1298 mvnmi r0, #0 @ (less than) r1<- -1 1299 moveq r0, #0 @ (equal) r1<- 0 1300 b .LOP_CMPG_FLOAT_finish @ argh 1301 1302 1303 /* ------------------------------ */ 1304 .balign 64 1305 .L_OP_CMPL_DOUBLE: /* 0x2f */ 1306 /* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1307 /* 1308 * Compare two floating-point values. Puts 0, 1, or -1 into the 1309 * destination register based on the results of the comparison. 1310 * 1311 * int compare(x, y) { 1312 * if (x == y) { 1313 * return 0; 1314 * } else if (x > y) { 1315 * return 1; 1316 * } else if (x < y) { 1317 * return -1; 1318 * } else { 1319 * return -1; 1320 * } 1321 * } 1322 */ 1323 /* op vAA, vBB, vCC */ 1324 FETCH(r0, 1) @ r0<- CCBB 1325 mov r9, rINST, lsr #8 @ r9<- AA 1326 and r2, r0, #255 @ r2<- BB 1327 mov r3, r0, lsr #8 @ r3<- CC 1328 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1329 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1330 fldd d0, [r2] @ d0<- vBB 1331 fldd d1, [r3] @ d1<- vCC 1332 fcmped d0, d1 @ compare (vBB, vCC) 1333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1334 mvn r0, #0 @ r0<- -1 (default) 1335 GET_INST_OPCODE(ip) @ extract opcode from rINST 1336 fmstat @ export status flags 1337 movgt r0, #1 @ (greater than) r1<- 1 1338 moveq r0, #0 @ (equal) r1<- 0 1339 b .LOP_CMPL_DOUBLE_finish @ argh 1340 1341 1342 /* ------------------------------ */ 1343 .balign 64 1344 .L_OP_CMPG_DOUBLE: /* 0x30 */ 1345 /* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1346 /* 1347 * Compare two floating-point values. Puts 0, 1, or -1 into the 1348 * destination register based on the results of the comparison. 1349 * 1350 * int compare(x, y) { 1351 * if (x == y) { 1352 * return 0; 1353 * } else if (x < y) { 1354 * return -1; 1355 * } else if (x > y) { 1356 * return 1; 1357 * } else { 1358 * return 1; 1359 * } 1360 * } 1361 */ 1362 /* op vAA, vBB, vCC */ 1363 FETCH(r0, 1) @ r0<- CCBB 1364 mov r9, rINST, lsr #8 @ r9<- AA 1365 and r2, r0, #255 @ r2<- BB 1366 mov r3, r0, lsr #8 @ r3<- CC 1367 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1368 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 1369 fldd d0, [r2] @ d0<- vBB 1370 fldd d1, [r3] @ d1<- vCC 1371 fcmped d0, d1 @ compare (vBB, vCC) 1372 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1373 mov r0, #1 @ r0<- 1 (default) 1374 GET_INST_OPCODE(ip) @ extract opcode from rINST 1375 fmstat @ export status flags 1376 mvnmi r0, #0 @ (less than) r1<- -1 1377 moveq r0, #0 @ (equal) r1<- 0 1378 b .LOP_CMPG_DOUBLE_finish @ argh 1379 1380 1381 /* ------------------------------ */ 1382 .balign 64 1383 .L_OP_CMP_LONG: /* 0x31 */ 1384 /* File: armv5te/OP_CMP_LONG.S */ 1385 /* 1386 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1387 * register based on the results of the comparison. 1388 * 1389 * We load the full values with LDM, but in practice many values could 1390 * be resolved by only looking at the high word. This could be made 1391 * faster or slower by splitting the LDM into a pair of LDRs. 1392 * 1393 * If we just wanted to set condition flags, we could do this: 1394 * subs ip, r0, r2 1395 * sbcs ip, r1, r3 1396 * subeqs ip, r0, r2 1397 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1398 * integer value, which we can do with 2 conditional mov/mvn instructions 1399 * (set 1, set -1; if they're equal we already have 0 in ip), giving 1400 * us a constant 5-cycle path plus a branch at the end to the 1401 * instruction epilogue code. The multi-compare approach below needs 1402 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1403 * in the worst case (the 64-bit values are equal). 1404 */ 1405 /* cmp-long vAA, vBB, vCC */ 1406 FETCH(r0, 1) @ r0<- CCBB 1407 mov r9, rINST, lsr #8 @ r9<- AA 1408 and r2, r0, #255 @ r2<- BB 1409 mov r3, r0, lsr #8 @ r3<- CC 1410 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1411 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1412 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1413 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1414 cmp r1, r3 @ compare (vBB+1, vCC+1) 1415 blt .LOP_CMP_LONG_less @ signed compare on high part 1416 bgt .LOP_CMP_LONG_greater 1417 subs r1, r0, r2 @ r1<- r0 - r2 1418 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1419 bne .LOP_CMP_LONG_less 1420 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1421 1422 /* ------------------------------ */ 1423 .balign 64 1424 .L_OP_IF_EQ: /* 0x32 */ 1425 /* File: armv5te/OP_IF_EQ.S */ 1426 /* File: armv5te/bincmp.S */ 1427 /* 1428 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1429 * fragment that specifies the *reverse* comparison to perform, e.g. 1430 * for "if-le" you would use "gt". 1431 * 1432 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1433 */ 1434 /* if-cmp vA, vB, +CCCC */ 1435 mov r0, rINST, lsr #8 @ r0<- A+ 1436 mov r1, rINST, lsr #12 @ r1<- B 1437 and r0, r0, #15 1438 GET_VREG(r3, r1) @ r3<- vB 1439 GET_VREG(r2, r0) @ r2<- vA 1440 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1441 cmp r2, r3 @ compare (vA, vB) 1442 movne r1, #2 @ r1<- BYTE branch dist for not-taken 1443 adds r2, r1, r1 @ convert to bytes, check sign 1444 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1445 #if defined(WITH_JIT) 1446 ldr r0, [rSELF, #offThread_pJitProfTable] 1447 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1448 cmp r0,#0 1449 bne common_updateProfile 1450 #else 1451 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1452 #endif 1453 GET_INST_OPCODE(ip) @ extract opcode from rINST 1454 GOTO_OPCODE(ip) @ jump to next instruction 1455 1456 1457 /* ------------------------------ */ 1458 .balign 64 1459 .L_OP_IF_NE: /* 0x33 */ 1460 /* File: armv5te/OP_IF_NE.S */ 1461 /* File: armv5te/bincmp.S */ 1462 /* 1463 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1464 * fragment that specifies the *reverse* comparison to perform, e.g. 1465 * for "if-le" you would use "gt". 1466 * 1467 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1468 */ 1469 /* if-cmp vA, vB, +CCCC */ 1470 mov r0, rINST, lsr #8 @ r0<- A+ 1471 mov r1, rINST, lsr #12 @ r1<- B 1472 and r0, r0, #15 1473 GET_VREG(r3, r1) @ r3<- vB 1474 GET_VREG(r2, r0) @ r2<- vA 1475 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1476 cmp r2, r3 @ compare (vA, vB) 1477 moveq r1, #2 @ r1<- BYTE branch dist for not-taken 1478 adds r2, r1, r1 @ convert to bytes, check sign 1479 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1480 #if defined(WITH_JIT) 1481 ldr r0, [rSELF, #offThread_pJitProfTable] 1482 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1483 cmp r0,#0 1484 bne common_updateProfile 1485 #else 1486 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1487 #endif 1488 GET_INST_OPCODE(ip) @ extract opcode from rINST 1489 GOTO_OPCODE(ip) @ jump to next instruction 1490 1491 1492 /* ------------------------------ */ 1493 .balign 64 1494 .L_OP_IF_LT: /* 0x34 */ 1495 /* File: armv5te/OP_IF_LT.S */ 1496 /* File: armv5te/bincmp.S */ 1497 /* 1498 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1499 * fragment that specifies the *reverse* comparison to perform, e.g. 1500 * for "if-le" you would use "gt". 1501 * 1502 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1503 */ 1504 /* if-cmp vA, vB, +CCCC */ 1505 mov r0, rINST, lsr #8 @ r0<- A+ 1506 mov r1, rINST, lsr #12 @ r1<- B 1507 and r0, r0, #15 1508 GET_VREG(r3, r1) @ r3<- vB 1509 GET_VREG(r2, r0) @ r2<- vA 1510 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1511 cmp r2, r3 @ compare (vA, vB) 1512 movge r1, #2 @ r1<- BYTE branch dist for not-taken 1513 adds r2, r1, r1 @ convert to bytes, check sign 1514 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1515 #if defined(WITH_JIT) 1516 ldr r0, [rSELF, #offThread_pJitProfTable] 1517 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1518 cmp r0,#0 1519 bne common_updateProfile 1520 #else 1521 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1522 #endif 1523 GET_INST_OPCODE(ip) @ extract opcode from rINST 1524 GOTO_OPCODE(ip) @ jump to next instruction 1525 1526 1527 /* ------------------------------ */ 1528 .balign 64 1529 .L_OP_IF_GE: /* 0x35 */ 1530 /* File: armv5te/OP_IF_GE.S */ 1531 /* File: armv5te/bincmp.S */ 1532 /* 1533 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1534 * fragment that specifies the *reverse* comparison to perform, e.g. 1535 * for "if-le" you would use "gt". 1536 * 1537 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1538 */ 1539 /* if-cmp vA, vB, +CCCC */ 1540 mov r0, rINST, lsr #8 @ r0<- A+ 1541 mov r1, rINST, lsr #12 @ r1<- B 1542 and r0, r0, #15 1543 GET_VREG(r3, r1) @ r3<- vB 1544 GET_VREG(r2, r0) @ r2<- vA 1545 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1546 cmp r2, r3 @ compare (vA, vB) 1547 movlt r1, #2 @ r1<- BYTE branch dist for not-taken 1548 adds r2, r1, r1 @ convert to bytes, check sign 1549 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1550 #if defined(WITH_JIT) 1551 ldr r0, [rSELF, #offThread_pJitProfTable] 1552 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1553 cmp r0,#0 1554 bne common_updateProfile 1555 #else 1556 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1557 #endif 1558 GET_INST_OPCODE(ip) @ extract opcode from rINST 1559 GOTO_OPCODE(ip) @ jump to next instruction 1560 1561 1562 /* ------------------------------ */ 1563 .balign 64 1564 .L_OP_IF_GT: /* 0x36 */ 1565 /* File: armv5te/OP_IF_GT.S */ 1566 /* File: armv5te/bincmp.S */ 1567 /* 1568 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1569 * fragment that specifies the *reverse* comparison to perform, e.g. 1570 * for "if-le" you would use "gt". 1571 * 1572 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1573 */ 1574 /* if-cmp vA, vB, +CCCC */ 1575 mov r0, rINST, lsr #8 @ r0<- A+ 1576 mov r1, rINST, lsr #12 @ r1<- B 1577 and r0, r0, #15 1578 GET_VREG(r3, r1) @ r3<- vB 1579 GET_VREG(r2, r0) @ r2<- vA 1580 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1581 cmp r2, r3 @ compare (vA, vB) 1582 movle r1, #2 @ r1<- BYTE branch dist for not-taken 1583 adds r2, r1, r1 @ convert to bytes, check sign 1584 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1585 #if defined(WITH_JIT) 1586 ldr r0, [rSELF, #offThread_pJitProfTable] 1587 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1588 cmp r0,#0 1589 bne common_updateProfile 1590 #else 1591 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1592 #endif 1593 GET_INST_OPCODE(ip) @ extract opcode from rINST 1594 GOTO_OPCODE(ip) @ jump to next instruction 1595 1596 1597 /* ------------------------------ */ 1598 .balign 64 1599 .L_OP_IF_LE: /* 0x37 */ 1600 /* File: armv5te/OP_IF_LE.S */ 1601 /* File: armv5te/bincmp.S */ 1602 /* 1603 * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1604 * fragment that specifies the *reverse* comparison to perform, e.g. 1605 * for "if-le" you would use "gt". 1606 * 1607 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1608 */ 1609 /* if-cmp vA, vB, +CCCC */ 1610 mov r0, rINST, lsr #8 @ r0<- A+ 1611 mov r1, rINST, lsr #12 @ r1<- B 1612 and r0, r0, #15 1613 GET_VREG(r3, r1) @ r3<- vB 1614 GET_VREG(r2, r0) @ r2<- vA 1615 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1616 cmp r2, r3 @ compare (vA, vB) 1617 movgt r1, #2 @ r1<- BYTE branch dist for not-taken 1618 adds r2, r1, r1 @ convert to bytes, check sign 1619 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST 1620 #if defined(WITH_JIT) 1621 ldr r0, [rSELF, #offThread_pJitProfTable] 1622 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1623 cmp r0,#0 1624 bne common_updateProfile 1625 #else 1626 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 1627 #endif 1628 GET_INST_OPCODE(ip) @ extract opcode from rINST 1629 GOTO_OPCODE(ip) @ jump to next instruction 1630 1631 1632 /* ------------------------------ */ 1633 .balign 64 1634 .L_OP_IF_EQZ: /* 0x38 */ 1635 /* File: armv5te/OP_IF_EQZ.S */ 1636 /* File: armv5te/zcmp.S */ 1637 /* 1638 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1639 * fragment that specifies the *reverse* comparison to perform, e.g. 1640 * for "if-le" you would use "gt". 1641 * 1642 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1643 */ 1644 /* if-cmp vAA, +BBBB */ 1645 mov r0, rINST, lsr #8 @ r0<- AA 1646 GET_VREG(r2, r0) @ r2<- vAA 1647 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1648 cmp r2, #0 @ compare (vA, 0) 1649 movne r1, #2 @ r1<- inst branch dist for not-taken 1650 adds r1, r1, r1 @ convert to bytes & set flags 1651 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1652 #if defined(WITH_JIT) 1653 ldr r0, [rSELF, #offThread_pJitProfTable] 1654 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1655 cmp r0,#0 1656 bne common_updateProfile @ test for JIT off at target 1657 #else 1658 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1659 #endif 1660 GET_INST_OPCODE(ip) @ extract opcode from rINST 1661 GOTO_OPCODE(ip) @ jump to next instruction 1662 1663 1664 /* ------------------------------ */ 1665 .balign 64 1666 .L_OP_IF_NEZ: /* 0x39 */ 1667 /* File: armv5te/OP_IF_NEZ.S */ 1668 /* File: armv5te/zcmp.S */ 1669 /* 1670 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1671 * fragment that specifies the *reverse* comparison to perform, e.g. 1672 * for "if-le" you would use "gt". 1673 * 1674 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1675 */ 1676 /* if-cmp vAA, +BBBB */ 1677 mov r0, rINST, lsr #8 @ r0<- AA 1678 GET_VREG(r2, r0) @ r2<- vAA 1679 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1680 cmp r2, #0 @ compare (vA, 0) 1681 moveq r1, #2 @ r1<- inst branch dist for not-taken 1682 adds r1, r1, r1 @ convert to bytes & set flags 1683 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1684 #if defined(WITH_JIT) 1685 ldr r0, [rSELF, #offThread_pJitProfTable] 1686 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1687 cmp r0,#0 1688 bne common_updateProfile @ test for JIT off at target 1689 #else 1690 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1691 #endif 1692 GET_INST_OPCODE(ip) @ extract opcode from rINST 1693 GOTO_OPCODE(ip) @ jump to next instruction 1694 1695 1696 /* ------------------------------ */ 1697 .balign 64 1698 .L_OP_IF_LTZ: /* 0x3a */ 1699 /* File: armv5te/OP_IF_LTZ.S */ 1700 /* File: armv5te/zcmp.S */ 1701 /* 1702 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1703 * fragment that specifies the *reverse* comparison to perform, e.g. 1704 * for "if-le" you would use "gt". 1705 * 1706 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1707 */ 1708 /* if-cmp vAA, +BBBB */ 1709 mov r0, rINST, lsr #8 @ r0<- AA 1710 GET_VREG(r2, r0) @ r2<- vAA 1711 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1712 cmp r2, #0 @ compare (vA, 0) 1713 movge r1, #2 @ r1<- inst branch dist for not-taken 1714 adds r1, r1, r1 @ convert to bytes & set flags 1715 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1716 #if defined(WITH_JIT) 1717 ldr r0, [rSELF, #offThread_pJitProfTable] 1718 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1719 cmp r0,#0 1720 bne common_updateProfile @ test for JIT off at target 1721 #else 1722 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1723 #endif 1724 GET_INST_OPCODE(ip) @ extract opcode from rINST 1725 GOTO_OPCODE(ip) @ jump to next instruction 1726 1727 1728 /* ------------------------------ */ 1729 .balign 64 1730 .L_OP_IF_GEZ: /* 0x3b */ 1731 /* File: armv5te/OP_IF_GEZ.S */ 1732 /* File: armv5te/zcmp.S */ 1733 /* 1734 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1735 * fragment that specifies the *reverse* comparison to perform, e.g. 1736 * for "if-le" you would use "gt". 1737 * 1738 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1739 */ 1740 /* if-cmp vAA, +BBBB */ 1741 mov r0, rINST, lsr #8 @ r0<- AA 1742 GET_VREG(r2, r0) @ r2<- vAA 1743 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1744 cmp r2, #0 @ compare (vA, 0) 1745 movlt r1, #2 @ r1<- inst branch dist for not-taken 1746 adds r1, r1, r1 @ convert to bytes & set flags 1747 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1748 #if defined(WITH_JIT) 1749 ldr r0, [rSELF, #offThread_pJitProfTable] 1750 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1751 cmp r0,#0 1752 bne common_updateProfile @ test for JIT off at target 1753 #else 1754 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1755 #endif 1756 GET_INST_OPCODE(ip) @ extract opcode from rINST 1757 GOTO_OPCODE(ip) @ jump to next instruction 1758 1759 1760 /* ------------------------------ */ 1761 .balign 64 1762 .L_OP_IF_GTZ: /* 0x3c */ 1763 /* File: armv5te/OP_IF_GTZ.S */ 1764 /* File: armv5te/zcmp.S */ 1765 /* 1766 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1767 * fragment that specifies the *reverse* comparison to perform, e.g. 1768 * for "if-le" you would use "gt". 1769 * 1770 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1771 */ 1772 /* if-cmp vAA, +BBBB */ 1773 mov r0, rINST, lsr #8 @ r0<- AA 1774 GET_VREG(r2, r0) @ r2<- vAA 1775 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1776 cmp r2, #0 @ compare (vA, 0) 1777 movle r1, #2 @ r1<- inst branch dist for not-taken 1778 adds r1, r1, r1 @ convert to bytes & set flags 1779 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1780 #if defined(WITH_JIT) 1781 ldr r0, [rSELF, #offThread_pJitProfTable] 1782 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1783 cmp r0,#0 1784 bne common_updateProfile @ test for JIT off at target 1785 #else 1786 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1787 #endif 1788 GET_INST_OPCODE(ip) @ extract opcode from rINST 1789 GOTO_OPCODE(ip) @ jump to next instruction 1790 1791 1792 /* ------------------------------ */ 1793 .balign 64 1794 .L_OP_IF_LEZ: /* 0x3d */ 1795 /* File: armv5te/OP_IF_LEZ.S */ 1796 /* File: armv5te/zcmp.S */ 1797 /* 1798 * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1799 * fragment that specifies the *reverse* comparison to perform, e.g. 1800 * for "if-le" you would use "gt". 1801 * 1802 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1803 */ 1804 /* if-cmp vAA, +BBBB */ 1805 mov r0, rINST, lsr #8 @ r0<- AA 1806 GET_VREG(r2, r0) @ r2<- vAA 1807 FETCH_S(r1, 1) @ r1<- branch offset, in code units 1808 cmp r2, #0 @ compare (vA, 0) 1809 movgt r1, #2 @ r1<- inst branch dist for not-taken 1810 adds r1, r1, r1 @ convert to bytes & set flags 1811 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST 1812 #if defined(WITH_JIT) 1813 ldr r0, [rSELF, #offThread_pJitProfTable] 1814 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1815 cmp r0,#0 1816 bne common_updateProfile @ test for JIT off at target 1817 #else 1818 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base 1819 #endif 1820 GET_INST_OPCODE(ip) @ extract opcode from rINST 1821 GOTO_OPCODE(ip) @ jump to next instruction 1822 1823 1824 /* ------------------------------ */ 1825 .balign 64 1826 .L_OP_UNUSED_3E: /* 0x3e */ 1827 /* File: armv5te/OP_UNUSED_3E.S */ 1828 /* File: armv5te/unused.S */ 1829 bl common_abort 1830 1831 1832 /* ------------------------------ */ 1833 .balign 64 1834 .L_OP_UNUSED_3F: /* 0x3f */ 1835 /* File: armv5te/OP_UNUSED_3F.S */ 1836 /* File: armv5te/unused.S */ 1837 bl common_abort 1838 1839 1840 /* ------------------------------ */ 1841 .balign 64 1842 .L_OP_UNUSED_40: /* 0x40 */ 1843 /* File: armv5te/OP_UNUSED_40.S */ 1844 /* File: armv5te/unused.S */ 1845 bl common_abort 1846 1847 1848 /* ------------------------------ */ 1849 .balign 64 1850 .L_OP_UNUSED_41: /* 0x41 */ 1851 /* File: armv5te/OP_UNUSED_41.S */ 1852 /* File: armv5te/unused.S */ 1853 bl common_abort 1854 1855 1856 /* ------------------------------ */ 1857 .balign 64 1858 .L_OP_UNUSED_42: /* 0x42 */ 1859 /* File: armv5te/OP_UNUSED_42.S */ 1860 /* File: armv5te/unused.S */ 1861 bl common_abort 1862 1863 1864 /* ------------------------------ */ 1865 .balign 64 1866 .L_OP_UNUSED_43: /* 0x43 */ 1867 /* File: armv5te/OP_UNUSED_43.S */ 1868 /* File: armv5te/unused.S */ 1869 bl common_abort 1870 1871 1872 /* ------------------------------ */ 1873 .balign 64 1874 .L_OP_AGET: /* 0x44 */ 1875 /* File: armv5te/OP_AGET.S */ 1876 /* 1877 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1878 * 1879 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1880 * instructions. We use a pair of FETCH_Bs instead. 1881 * 1882 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1883 */ 1884 /* op vAA, vBB, vCC */ 1885 FETCH_B(r2, 1, 0) @ r2<- BB 1886 mov r9, rINST, lsr #8 @ r9<- AA 1887 FETCH_B(r3, 1, 1) @ r3<- CC 1888 GET_VREG(r0, r2) @ r0<- vBB (array object) 1889 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1890 cmp r0, #0 @ null array object? 1891 beq common_errNullObject @ yes, bail 1892 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1893 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1894 cmp r1, r3 @ compare unsigned index, length 1895 bcs common_errArrayIndex @ index >= length, bail 1896 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1897 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1898 GET_INST_OPCODE(ip) @ extract opcode from rINST 1899 SET_VREG(r2, r9) @ vAA<- r2 1900 GOTO_OPCODE(ip) @ jump to next instruction 1901 1902 /* ------------------------------ */ 1903 .balign 64 1904 .L_OP_AGET_WIDE: /* 0x45 */ 1905 /* File: armv5te/OP_AGET_WIDE.S */ 1906 /* 1907 * Array get, 64 bits. vAA <- vBB[vCC]. 1908 * 1909 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1910 */ 1911 /* aget-wide vAA, vBB, vCC */ 1912 FETCH(r0, 1) @ r0<- CCBB 1913 mov r9, rINST, lsr #8 @ r9<- AA 1914 and r2, r0, #255 @ r2<- BB 1915 mov r3, r0, lsr #8 @ r3<- CC 1916 GET_VREG(r0, r2) @ r0<- vBB (array object) 1917 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1918 cmp r0, #0 @ null array object? 1919 beq common_errNullObject @ yes, bail 1920 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1921 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1922 cmp r1, r3 @ compare unsigned index, length 1923 bcc .LOP_AGET_WIDE_finish @ okay, continue below 1924 b common_errArrayIndex @ index >= length, bail 1925 @ May want to swap the order of these two branches depending on how the 1926 @ branch prediction (if any) handles conditional forward branches vs. 1927 @ unconditional forward branches. 1928 1929 /* ------------------------------ */ 1930 .balign 64 1931 .L_OP_AGET_OBJECT: /* 0x46 */ 1932 /* File: armv5te/OP_AGET_OBJECT.S */ 1933 /* File: armv5te/OP_AGET.S */ 1934 /* 1935 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1936 * 1937 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1938 * instructions. We use a pair of FETCH_Bs instead. 1939 * 1940 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1941 */ 1942 /* op vAA, vBB, vCC */ 1943 FETCH_B(r2, 1, 0) @ r2<- BB 1944 mov r9, rINST, lsr #8 @ r9<- AA 1945 FETCH_B(r3, 1, 1) @ r3<- CC 1946 GET_VREG(r0, r2) @ r0<- vBB (array object) 1947 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1948 cmp r0, #0 @ null array object? 1949 beq common_errNullObject @ yes, bail 1950 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1951 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1952 cmp r1, r3 @ compare unsigned index, length 1953 bcs common_errArrayIndex @ index >= length, bail 1954 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1955 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1956 GET_INST_OPCODE(ip) @ extract opcode from rINST 1957 SET_VREG(r2, r9) @ vAA<- r2 1958 GOTO_OPCODE(ip) @ jump to next instruction 1959 1960 1961 /* ------------------------------ */ 1962 .balign 64 1963 .L_OP_AGET_BOOLEAN: /* 0x47 */ 1964 /* File: armv5te/OP_AGET_BOOLEAN.S */ 1965 /* File: armv5te/OP_AGET.S */ 1966 /* 1967 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1968 * 1969 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1970 * instructions. We use a pair of FETCH_Bs instead. 1971 * 1972 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1973 */ 1974 /* op vAA, vBB, vCC */ 1975 FETCH_B(r2, 1, 0) @ r2<- BB 1976 mov r9, rINST, lsr #8 @ r9<- AA 1977 FETCH_B(r3, 1, 1) @ r3<- CC 1978 GET_VREG(r0, r2) @ r0<- vBB (array object) 1979 GET_VREG(r1, r3) @ r1<- vCC (requested index) 1980 cmp r0, #0 @ null array object? 1981 beq common_errNullObject @ yes, bail 1982 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1983 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 1984 cmp r1, r3 @ compare unsigned index, length 1985 bcs common_errArrayIndex @ index >= length, bail 1986 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1987 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 1988 GET_INST_OPCODE(ip) @ extract opcode from rINST 1989 SET_VREG(r2, r9) @ vAA<- r2 1990 GOTO_OPCODE(ip) @ jump to next instruction 1991 1992 1993 /* ------------------------------ */ 1994 .balign 64 1995 .L_OP_AGET_BYTE: /* 0x48 */ 1996 /* File: armv5te/OP_AGET_BYTE.S */ 1997 /* File: armv5te/OP_AGET.S */ 1998 /* 1999 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2000 * 2001 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2002 * instructions. We use a pair of FETCH_Bs instead. 2003 * 2004 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2005 */ 2006 /* op vAA, vBB, vCC */ 2007 FETCH_B(r2, 1, 0) @ r2<- BB 2008 mov r9, rINST, lsr #8 @ r9<- AA 2009 FETCH_B(r3, 1, 1) @ r3<- CC 2010 GET_VREG(r0, r2) @ r0<- vBB (array object) 2011 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2012 cmp r0, #0 @ null array object? 2013 beq common_errNullObject @ yes, bail 2014 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2015 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2016 cmp r1, r3 @ compare unsigned index, length 2017 bcs common_errArrayIndex @ index >= length, bail 2018 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2019 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2020 GET_INST_OPCODE(ip) @ extract opcode from rINST 2021 SET_VREG(r2, r9) @ vAA<- r2 2022 GOTO_OPCODE(ip) @ jump to next instruction 2023 2024 2025 /* ------------------------------ */ 2026 .balign 64 2027 .L_OP_AGET_CHAR: /* 0x49 */ 2028 /* File: armv5te/OP_AGET_CHAR.S */ 2029 /* File: armv5te/OP_AGET.S */ 2030 /* 2031 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2032 * 2033 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2034 * instructions. We use a pair of FETCH_Bs instead. 2035 * 2036 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2037 */ 2038 /* op vAA, vBB, vCC */ 2039 FETCH_B(r2, 1, 0) @ r2<- BB 2040 mov r9, rINST, lsr #8 @ r9<- AA 2041 FETCH_B(r3, 1, 1) @ r3<- CC 2042 GET_VREG(r0, r2) @ r0<- vBB (array object) 2043 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2044 cmp r0, #0 @ null array object? 2045 beq common_errNullObject @ yes, bail 2046 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2047 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2048 cmp r1, r3 @ compare unsigned index, length 2049 bcs common_errArrayIndex @ index >= length, bail 2050 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2051 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2052 GET_INST_OPCODE(ip) @ extract opcode from rINST 2053 SET_VREG(r2, r9) @ vAA<- r2 2054 GOTO_OPCODE(ip) @ jump to next instruction 2055 2056 2057 /* ------------------------------ */ 2058 .balign 64 2059 .L_OP_AGET_SHORT: /* 0x4a */ 2060 /* File: armv5te/OP_AGET_SHORT.S */ 2061 /* File: armv5te/OP_AGET.S */ 2062 /* 2063 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2064 * 2065 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2066 * instructions. We use a pair of FETCH_Bs instead. 2067 * 2068 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2069 */ 2070 /* op vAA, vBB, vCC */ 2071 FETCH_B(r2, 1, 0) @ r2<- BB 2072 mov r9, rINST, lsr #8 @ r9<- AA 2073 FETCH_B(r3, 1, 1) @ r3<- CC 2074 GET_VREG(r0, r2) @ r0<- vBB (array object) 2075 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2076 cmp r0, #0 @ null array object? 2077 beq common_errNullObject @ yes, bail 2078 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2079 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2080 cmp r1, r3 @ compare unsigned index, length 2081 bcs common_errArrayIndex @ index >= length, bail 2082 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2083 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2084 GET_INST_OPCODE(ip) @ extract opcode from rINST 2085 SET_VREG(r2, r9) @ vAA<- r2 2086 GOTO_OPCODE(ip) @ jump to next instruction 2087 2088 2089 /* ------------------------------ */ 2090 .balign 64 2091 .L_OP_APUT: /* 0x4b */ 2092 /* File: armv5te/OP_APUT.S */ 2093 /* 2094 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2095 * 2096 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2097 * instructions. We use a pair of FETCH_Bs instead. 2098 * 2099 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2100 */ 2101 /* op vAA, vBB, vCC */ 2102 FETCH_B(r2, 1, 0) @ r2<- BB 2103 mov r9, rINST, lsr #8 @ r9<- AA 2104 FETCH_B(r3, 1, 1) @ r3<- CC 2105 GET_VREG(r0, r2) @ r0<- vBB (array object) 2106 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2107 cmp r0, #0 @ null array object? 2108 beq common_errNullObject @ yes, bail 2109 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2110 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2111 cmp r1, r3 @ compare unsigned index, length 2112 bcs common_errArrayIndex @ index >= length, bail 2113 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2114 GET_VREG(r2, r9) @ r2<- vAA 2115 GET_INST_OPCODE(ip) @ extract opcode from rINST 2116 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2117 GOTO_OPCODE(ip) @ jump to next instruction 2118 2119 /* ------------------------------ */ 2120 .balign 64 2121 .L_OP_APUT_WIDE: /* 0x4c */ 2122 /* File: armv5te/OP_APUT_WIDE.S */ 2123 /* 2124 * Array put, 64 bits. vBB[vCC] <- vAA. 2125 * 2126 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2127 */ 2128 /* aput-wide vAA, vBB, vCC */ 2129 FETCH(r0, 1) @ r0<- CCBB 2130 mov r9, rINST, lsr #8 @ r9<- AA 2131 and r2, r0, #255 @ r2<- BB 2132 mov r3, r0, lsr #8 @ r3<- CC 2133 GET_VREG(r0, r2) @ r0<- vBB (array object) 2134 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2135 cmp r0, #0 @ null array object? 2136 beq common_errNullObject @ yes, bail 2137 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2138 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2139 cmp r1, r3 @ compare unsigned index, length 2140 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2141 bcc .LOP_APUT_WIDE_finish @ okay, continue below 2142 b common_errArrayIndex @ index >= length, bail 2143 @ May want to swap the order of these two branches depending on how the 2144 @ branch prediction (if any) handles conditional forward branches vs. 2145 @ unconditional forward branches. 2146 2147 /* ------------------------------ */ 2148 .balign 64 2149 .L_OP_APUT_OBJECT: /* 0x4d */ 2150 /* File: armv5te/OP_APUT_OBJECT.S */ 2151 /* 2152 * Store an object into an array. vBB[vCC] <- vAA. 2153 */ 2154 /* op vAA, vBB, vCC */ 2155 FETCH(r0, 1) @ r0<- CCBB 2156 mov r9, rINST, lsr #8 @ r9<- AA 2157 and r2, r0, #255 @ r2<- BB 2158 mov r3, r0, lsr #8 @ r3<- CC 2159 GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2160 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2161 cmp rINST, #0 @ null array object? 2162 GET_VREG(r9, r9) @ r9<- vAA 2163 beq common_errNullObject @ yes, bail 2164 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2165 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 2166 cmp r1, r3 @ compare unsigned index, length 2167 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2168 b common_errArrayIndex @ index >= length, bail 2169 2170 2171 /* ------------------------------ */ 2172 .balign 64 2173 .L_OP_APUT_BOOLEAN: /* 0x4e */ 2174 /* File: armv5te/OP_APUT_BOOLEAN.S */ 2175 /* File: armv5te/OP_APUT.S */ 2176 /* 2177 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2178 * 2179 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2180 * instructions. We use a pair of FETCH_Bs instead. 2181 * 2182 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2183 */ 2184 /* op vAA, vBB, vCC */ 2185 FETCH_B(r2, 1, 0) @ r2<- BB 2186 mov r9, rINST, lsr #8 @ r9<- AA 2187 FETCH_B(r3, 1, 1) @ r3<- CC 2188 GET_VREG(r0, r2) @ r0<- vBB (array object) 2189 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2190 cmp r0, #0 @ null array object? 2191 beq common_errNullObject @ yes, bail 2192 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2193 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2194 cmp r1, r3 @ compare unsigned index, length 2195 bcs common_errArrayIndex @ index >= length, bail 2196 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2197 GET_VREG(r2, r9) @ r2<- vAA 2198 GET_INST_OPCODE(ip) @ extract opcode from rINST 2199 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2200 GOTO_OPCODE(ip) @ jump to next instruction 2201 2202 2203 /* ------------------------------ */ 2204 .balign 64 2205 .L_OP_APUT_BYTE: /* 0x4f */ 2206 /* File: armv5te/OP_APUT_BYTE.S */ 2207 /* File: armv5te/OP_APUT.S */ 2208 /* 2209 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2210 * 2211 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2212 * instructions. We use a pair of FETCH_Bs instead. 2213 * 2214 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2215 */ 2216 /* op vAA, vBB, vCC */ 2217 FETCH_B(r2, 1, 0) @ r2<- BB 2218 mov r9, rINST, lsr #8 @ r9<- AA 2219 FETCH_B(r3, 1, 1) @ r3<- CC 2220 GET_VREG(r0, r2) @ r0<- vBB (array object) 2221 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2222 cmp r0, #0 @ null array object? 2223 beq common_errNullObject @ yes, bail 2224 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2225 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2226 cmp r1, r3 @ compare unsigned index, length 2227 bcs common_errArrayIndex @ index >= length, bail 2228 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2229 GET_VREG(r2, r9) @ r2<- vAA 2230 GET_INST_OPCODE(ip) @ extract opcode from rINST 2231 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2232 GOTO_OPCODE(ip) @ jump to next instruction 2233 2234 2235 /* ------------------------------ */ 2236 .balign 64 2237 .L_OP_APUT_CHAR: /* 0x50 */ 2238 /* File: armv5te/OP_APUT_CHAR.S */ 2239 /* File: armv5te/OP_APUT.S */ 2240 /* 2241 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2242 * 2243 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2244 * instructions. We use a pair of FETCH_Bs instead. 2245 * 2246 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2247 */ 2248 /* op vAA, vBB, vCC */ 2249 FETCH_B(r2, 1, 0) @ r2<- BB 2250 mov r9, rINST, lsr #8 @ r9<- AA 2251 FETCH_B(r3, 1, 1) @ r3<- CC 2252 GET_VREG(r0, r2) @ r0<- vBB (array object) 2253 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2254 cmp r0, #0 @ null array object? 2255 beq common_errNullObject @ yes, bail 2256 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2257 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2258 cmp r1, r3 @ compare unsigned index, length 2259 bcs common_errArrayIndex @ index >= length, bail 2260 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2261 GET_VREG(r2, r9) @ r2<- vAA 2262 GET_INST_OPCODE(ip) @ extract opcode from rINST 2263 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2264 GOTO_OPCODE(ip) @ jump to next instruction 2265 2266 2267 /* ------------------------------ */ 2268 .balign 64 2269 .L_OP_APUT_SHORT: /* 0x51 */ 2270 /* File: armv5te/OP_APUT_SHORT.S */ 2271 /* File: armv5te/OP_APUT.S */ 2272 /* 2273 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2274 * 2275 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2276 * instructions. We use a pair of FETCH_Bs instead. 2277 * 2278 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2279 */ 2280 /* op vAA, vBB, vCC */ 2281 FETCH_B(r2, 1, 0) @ r2<- BB 2282 mov r9, rINST, lsr #8 @ r9<- AA 2283 FETCH_B(r3, 1, 1) @ r3<- CC 2284 GET_VREG(r0, r2) @ r0<- vBB (array object) 2285 GET_VREG(r1, r3) @ r1<- vCC (requested index) 2286 cmp r0, #0 @ null array object? 2287 beq common_errNullObject @ yes, bail 2288 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2289 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2290 cmp r1, r3 @ compare unsigned index, length 2291 bcs common_errArrayIndex @ index >= length, bail 2292 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2293 GET_VREG(r2, r9) @ r2<- vAA 2294 GET_INST_OPCODE(ip) @ extract opcode from rINST 2295 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2296 GOTO_OPCODE(ip) @ jump to next instruction 2297 2298 2299 /* ------------------------------ */ 2300 .balign 64 2301 .L_OP_IGET: /* 0x52 */ 2302 /* File: armv5te/OP_IGET.S */ 2303 /* 2304 * General 32-bit instance field get. 2305 * 2306 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2307 */ 2308 /* op vA, vB, field@CCCC */ 2309 mov r0, rINST, lsr #12 @ r0<- B 2310 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2311 FETCH(r1, 1) @ r1<- field ref CCCC 2312 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2313 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2314 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2315 cmp r0, #0 @ is resolved entry null? 2316 bne .LOP_IGET_finish @ no, already resolved 2317 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2318 EXPORT_PC() @ resolve() could throw 2319 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2320 bl dvmResolveInstField @ r0<- resolved InstField ptr 2321 cmp r0, #0 2322 bne .LOP_IGET_finish 2323 b common_exceptionThrown 2324 2325 /* ------------------------------ */ 2326 .balign 64 2327 .L_OP_IGET_WIDE: /* 0x53 */ 2328 /* File: armv5te/OP_IGET_WIDE.S */ 2329 /* 2330 * Wide 32-bit instance field get. 2331 */ 2332 /* iget-wide vA, vB, field@CCCC */ 2333 mov r0, rINST, lsr #12 @ r0<- B 2334 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2335 FETCH(r1, 1) @ r1<- field ref CCCC 2336 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2337 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2338 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2339 cmp r0, #0 @ is resolved entry null? 2340 bne .LOP_IGET_WIDE_finish @ no, already resolved 2341 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2342 EXPORT_PC() @ resolve() could throw 2343 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2344 bl dvmResolveInstField @ r0<- resolved InstField ptr 2345 cmp r0, #0 2346 bne .LOP_IGET_WIDE_finish 2347 b common_exceptionThrown 2348 2349 /* ------------------------------ */ 2350 .balign 64 2351 .L_OP_IGET_OBJECT: /* 0x54 */ 2352 /* File: armv5te/OP_IGET_OBJECT.S */ 2353 /* File: armv5te/OP_IGET.S */ 2354 /* 2355 * General 32-bit instance field get. 2356 * 2357 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2358 */ 2359 /* op vA, vB, field@CCCC */ 2360 mov r0, rINST, lsr #12 @ r0<- B 2361 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2362 FETCH(r1, 1) @ r1<- field ref CCCC 2363 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2364 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2365 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2366 cmp r0, #0 @ is resolved entry null? 2367 bne .LOP_IGET_OBJECT_finish @ no, already resolved 2368 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2369 EXPORT_PC() @ resolve() could throw 2370 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2371 bl dvmResolveInstField @ r0<- resolved InstField ptr 2372 cmp r0, #0 2373 bne .LOP_IGET_OBJECT_finish 2374 b common_exceptionThrown 2375 2376 2377 /* ------------------------------ */ 2378 .balign 64 2379 .L_OP_IGET_BOOLEAN: /* 0x55 */ 2380 /* File: armv5te/OP_IGET_BOOLEAN.S */ 2381 @include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2382 /* File: armv5te/OP_IGET.S */ 2383 /* 2384 * General 32-bit instance field get. 2385 * 2386 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2387 */ 2388 /* op vA, vB, field@CCCC */ 2389 mov r0, rINST, lsr #12 @ r0<- B 2390 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2391 FETCH(r1, 1) @ r1<- field ref CCCC 2392 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2393 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2394 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2395 cmp r0, #0 @ is resolved entry null? 2396 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2397 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2398 EXPORT_PC() @ resolve() could throw 2399 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2400 bl dvmResolveInstField @ r0<- resolved InstField ptr 2401 cmp r0, #0 2402 bne .LOP_IGET_BOOLEAN_finish 2403 b common_exceptionThrown 2404 2405 2406 /* ------------------------------ */ 2407 .balign 64 2408 .L_OP_IGET_BYTE: /* 0x56 */ 2409 /* File: armv5te/OP_IGET_BYTE.S */ 2410 @include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2411 /* File: armv5te/OP_IGET.S */ 2412 /* 2413 * General 32-bit instance field get. 2414 * 2415 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2416 */ 2417 /* op vA, vB, field@CCCC */ 2418 mov r0, rINST, lsr #12 @ r0<- B 2419 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2420 FETCH(r1, 1) @ r1<- field ref CCCC 2421 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2422 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2423 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2424 cmp r0, #0 @ is resolved entry null? 2425 bne .LOP_IGET_BYTE_finish @ no, already resolved 2426 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2427 EXPORT_PC() @ resolve() could throw 2428 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2429 bl dvmResolveInstField @ r0<- resolved InstField ptr 2430 cmp r0, #0 2431 bne .LOP_IGET_BYTE_finish 2432 b common_exceptionThrown 2433 2434 2435 /* ------------------------------ */ 2436 .balign 64 2437 .L_OP_IGET_CHAR: /* 0x57 */ 2438 /* File: armv5te/OP_IGET_CHAR.S */ 2439 @include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2440 /* File: armv5te/OP_IGET.S */ 2441 /* 2442 * General 32-bit instance field get. 2443 * 2444 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2445 */ 2446 /* op vA, vB, field@CCCC */ 2447 mov r0, rINST, lsr #12 @ r0<- B 2448 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2449 FETCH(r1, 1) @ r1<- field ref CCCC 2450 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2451 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2452 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2453 cmp r0, #0 @ is resolved entry null? 2454 bne .LOP_IGET_CHAR_finish @ no, already resolved 2455 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2456 EXPORT_PC() @ resolve() could throw 2457 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2458 bl dvmResolveInstField @ r0<- resolved InstField ptr 2459 cmp r0, #0 2460 bne .LOP_IGET_CHAR_finish 2461 b common_exceptionThrown 2462 2463 2464 /* ------------------------------ */ 2465 .balign 64 2466 .L_OP_IGET_SHORT: /* 0x58 */ 2467 /* File: armv5te/OP_IGET_SHORT.S */ 2468 @include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2469 /* File: armv5te/OP_IGET.S */ 2470 /* 2471 * General 32-bit instance field get. 2472 * 2473 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2474 */ 2475 /* op vA, vB, field@CCCC */ 2476 mov r0, rINST, lsr #12 @ r0<- B 2477 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2478 FETCH(r1, 1) @ r1<- field ref CCCC 2479 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2480 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2481 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2482 cmp r0, #0 @ is resolved entry null? 2483 bne .LOP_IGET_SHORT_finish @ no, already resolved 2484 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2485 EXPORT_PC() @ resolve() could throw 2486 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2487 bl dvmResolveInstField @ r0<- resolved InstField ptr 2488 cmp r0, #0 2489 bne .LOP_IGET_SHORT_finish 2490 b common_exceptionThrown 2491 2492 2493 /* ------------------------------ */ 2494 .balign 64 2495 .L_OP_IPUT: /* 0x59 */ 2496 /* File: armv5te/OP_IPUT.S */ 2497 /* 2498 * General 32-bit instance field put. 2499 * 2500 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2501 */ 2502 /* op vA, vB, field@CCCC */ 2503 mov r0, rINST, lsr #12 @ r0<- B 2504 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2505 FETCH(r1, 1) @ r1<- field ref CCCC 2506 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2507 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2508 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2509 cmp r0, #0 @ is resolved entry null? 2510 bne .LOP_IPUT_finish @ no, already resolved 2511 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2512 EXPORT_PC() @ resolve() could throw 2513 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2514 bl dvmResolveInstField @ r0<- resolved InstField ptr 2515 cmp r0, #0 @ success? 2516 bne .LOP_IPUT_finish @ yes, finish up 2517 b common_exceptionThrown 2518 2519 /* ------------------------------ */ 2520 .balign 64 2521 .L_OP_IPUT_WIDE: /* 0x5a */ 2522 /* File: armv5te/OP_IPUT_WIDE.S */ 2523 /* iput-wide vA, vB, field@CCCC */ 2524 mov r0, rINST, lsr #12 @ r0<- B 2525 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2526 FETCH(r1, 1) @ r1<- field ref CCCC 2527 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2528 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2529 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2530 cmp r0, #0 @ is resolved entry null? 2531 bne .LOP_IPUT_WIDE_finish @ no, already resolved 2532 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2533 EXPORT_PC() @ resolve() could throw 2534 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2535 bl dvmResolveInstField @ r0<- resolved InstField ptr 2536 cmp r0, #0 @ success? 2537 bne .LOP_IPUT_WIDE_finish @ yes, finish up 2538 b common_exceptionThrown 2539 2540 /* ------------------------------ */ 2541 .balign 64 2542 .L_OP_IPUT_OBJECT: /* 0x5b */ 2543 /* File: armv5te/OP_IPUT_OBJECT.S */ 2544 /* 2545 * 32-bit instance field put. 2546 * 2547 * for: iput-object, iput-object-volatile 2548 */ 2549 /* op vA, vB, field@CCCC */ 2550 mov r0, rINST, lsr #12 @ r0<- B 2551 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2552 FETCH(r1, 1) @ r1<- field ref CCCC 2553 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2554 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2555 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2556 cmp r0, #0 @ is resolved entry null? 2557 bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2558 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2559 EXPORT_PC() @ resolve() could throw 2560 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2561 bl dvmResolveInstField @ r0<- resolved InstField ptr 2562 cmp r0, #0 @ success? 2563 bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2564 b common_exceptionThrown 2565 2566 /* ------------------------------ */ 2567 .balign 64 2568 .L_OP_IPUT_BOOLEAN: /* 0x5c */ 2569 /* File: armv5te/OP_IPUT_BOOLEAN.S */ 2570 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2571 /* File: armv5te/OP_IPUT.S */ 2572 /* 2573 * General 32-bit instance field put. 2574 * 2575 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2576 */ 2577 /* op vA, vB, field@CCCC */ 2578 mov r0, rINST, lsr #12 @ r0<- B 2579 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2580 FETCH(r1, 1) @ r1<- field ref CCCC 2581 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2582 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2583 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2584 cmp r0, #0 @ is resolved entry null? 2585 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2586 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2587 EXPORT_PC() @ resolve() could throw 2588 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2589 bl dvmResolveInstField @ r0<- resolved InstField ptr 2590 cmp r0, #0 @ success? 2591 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2592 b common_exceptionThrown 2593 2594 2595 /* ------------------------------ */ 2596 .balign 64 2597 .L_OP_IPUT_BYTE: /* 0x5d */ 2598 /* File: armv5te/OP_IPUT_BYTE.S */ 2599 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2600 /* File: armv5te/OP_IPUT.S */ 2601 /* 2602 * General 32-bit instance field put. 2603 * 2604 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2605 */ 2606 /* op vA, vB, field@CCCC */ 2607 mov r0, rINST, lsr #12 @ r0<- B 2608 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2609 FETCH(r1, 1) @ r1<- field ref CCCC 2610 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2611 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2612 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2613 cmp r0, #0 @ is resolved entry null? 2614 bne .LOP_IPUT_BYTE_finish @ no, already resolved 2615 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2616 EXPORT_PC() @ resolve() could throw 2617 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2618 bl dvmResolveInstField @ r0<- resolved InstField ptr 2619 cmp r0, #0 @ success? 2620 bne .LOP_IPUT_BYTE_finish @ yes, finish up 2621 b common_exceptionThrown 2622 2623 2624 /* ------------------------------ */ 2625 .balign 64 2626 .L_OP_IPUT_CHAR: /* 0x5e */ 2627 /* File: armv5te/OP_IPUT_CHAR.S */ 2628 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2629 /* File: armv5te/OP_IPUT.S */ 2630 /* 2631 * General 32-bit instance field put. 2632 * 2633 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2634 */ 2635 /* op vA, vB, field@CCCC */ 2636 mov r0, rINST, lsr #12 @ r0<- B 2637 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2638 FETCH(r1, 1) @ r1<- field ref CCCC 2639 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2640 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2641 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2642 cmp r0, #0 @ is resolved entry null? 2643 bne .LOP_IPUT_CHAR_finish @ no, already resolved 2644 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2645 EXPORT_PC() @ resolve() could throw 2646 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2647 bl dvmResolveInstField @ r0<- resolved InstField ptr 2648 cmp r0, #0 @ success? 2649 bne .LOP_IPUT_CHAR_finish @ yes, finish up 2650 b common_exceptionThrown 2651 2652 2653 /* ------------------------------ */ 2654 .balign 64 2655 .L_OP_IPUT_SHORT: /* 0x5f */ 2656 /* File: armv5te/OP_IPUT_SHORT.S */ 2657 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2658 /* File: armv5te/OP_IPUT.S */ 2659 /* 2660 * General 32-bit instance field put. 2661 * 2662 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2663 */ 2664 /* op vA, vB, field@CCCC */ 2665 mov r0, rINST, lsr #12 @ r0<- B 2666 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 2667 FETCH(r1, 1) @ r1<- field ref CCCC 2668 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2669 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2670 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2671 cmp r0, #0 @ is resolved entry null? 2672 bne .LOP_IPUT_SHORT_finish @ no, already resolved 2673 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 2674 EXPORT_PC() @ resolve() could throw 2675 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2676 bl dvmResolveInstField @ r0<- resolved InstField ptr 2677 cmp r0, #0 @ success? 2678 bne .LOP_IPUT_SHORT_finish @ yes, finish up 2679 b common_exceptionThrown 2680 2681 2682 /* ------------------------------ */ 2683 .balign 64 2684 .L_OP_SGET: /* 0x60 */ 2685 /* File: armv5te/OP_SGET.S */ 2686 /* 2687 * General 32-bit SGET handler. 2688 * 2689 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2690 */ 2691 /* op vAA, field@BBBB */ 2692 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2693 FETCH(r1, 1) @ r1<- field ref BBBB 2694 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2695 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2696 cmp r0, #0 @ is resolved entry null? 2697 beq .LOP_SGET_resolve @ yes, do resolve 2698 .LOP_SGET_finish: @ field ptr in r0 2699 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2700 @ no-op @ acquiring load 2701 mov r2, rINST, lsr #8 @ r2<- AA 2702 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2703 SET_VREG(r1, r2) @ fp[AA]<- r1 2704 GET_INST_OPCODE(ip) @ extract opcode from rINST 2705 GOTO_OPCODE(ip) @ jump to next instruction 2706 2707 /* ------------------------------ */ 2708 .balign 64 2709 .L_OP_SGET_WIDE: /* 0x61 */ 2710 /* File: armv5te/OP_SGET_WIDE.S */ 2711 /* 2712 * 64-bit SGET handler. 2713 */ 2714 /* sget-wide vAA, field@BBBB */ 2715 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2716 FETCH(r1, 1) @ r1<- field ref BBBB 2717 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2718 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2719 cmp r0, #0 @ is resolved entry null? 2720 beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2721 .LOP_SGET_WIDE_finish: 2722 mov r9, rINST, lsr #8 @ r9<- AA 2723 .if 0 2724 add r0, r0, #offStaticField_value @ r0<- pointer to data 2725 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2726 .else 2727 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2728 .endif 2729 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2730 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2731 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2732 GET_INST_OPCODE(ip) @ extract opcode from rINST 2733 GOTO_OPCODE(ip) @ jump to next instruction 2734 2735 /* ------------------------------ */ 2736 .balign 64 2737 .L_OP_SGET_OBJECT: /* 0x62 */ 2738 /* File: armv5te/OP_SGET_OBJECT.S */ 2739 /* File: armv5te/OP_SGET.S */ 2740 /* 2741 * General 32-bit SGET handler. 2742 * 2743 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2744 */ 2745 /* op vAA, field@BBBB */ 2746 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2747 FETCH(r1, 1) @ r1<- field ref BBBB 2748 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2749 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2750 cmp r0, #0 @ is resolved entry null? 2751 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2752 .LOP_SGET_OBJECT_finish: @ field ptr in r0 2753 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2754 @ no-op @ acquiring load 2755 mov r2, rINST, lsr #8 @ r2<- AA 2756 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2757 SET_VREG(r1, r2) @ fp[AA]<- r1 2758 GET_INST_OPCODE(ip) @ extract opcode from rINST 2759 GOTO_OPCODE(ip) @ jump to next instruction 2760 2761 2762 /* ------------------------------ */ 2763 .balign 64 2764 .L_OP_SGET_BOOLEAN: /* 0x63 */ 2765 /* File: armv5te/OP_SGET_BOOLEAN.S */ 2766 /* File: armv5te/OP_SGET.S */ 2767 /* 2768 * General 32-bit SGET handler. 2769 * 2770 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2771 */ 2772 /* op vAA, field@BBBB */ 2773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2774 FETCH(r1, 1) @ r1<- field ref BBBB 2775 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2776 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2777 cmp r0, #0 @ is resolved entry null? 2778 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2779 .LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2780 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2781 @ no-op @ acquiring load 2782 mov r2, rINST, lsr #8 @ r2<- AA 2783 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2784 SET_VREG(r1, r2) @ fp[AA]<- r1 2785 GET_INST_OPCODE(ip) @ extract opcode from rINST 2786 GOTO_OPCODE(ip) @ jump to next instruction 2787 2788 2789 /* ------------------------------ */ 2790 .balign 64 2791 .L_OP_SGET_BYTE: /* 0x64 */ 2792 /* File: armv5te/OP_SGET_BYTE.S */ 2793 /* File: armv5te/OP_SGET.S */ 2794 /* 2795 * General 32-bit SGET handler. 2796 * 2797 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2798 */ 2799 /* op vAA, field@BBBB */ 2800 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2801 FETCH(r1, 1) @ r1<- field ref BBBB 2802 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2803 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2804 cmp r0, #0 @ is resolved entry null? 2805 beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2806 .LOP_SGET_BYTE_finish: @ field ptr in r0 2807 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2808 @ no-op @ acquiring load 2809 mov r2, rINST, lsr #8 @ r2<- AA 2810 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2811 SET_VREG(r1, r2) @ fp[AA]<- r1 2812 GET_INST_OPCODE(ip) @ extract opcode from rINST 2813 GOTO_OPCODE(ip) @ jump to next instruction 2814 2815 2816 /* ------------------------------ */ 2817 .balign 64 2818 .L_OP_SGET_CHAR: /* 0x65 */ 2819 /* File: armv5te/OP_SGET_CHAR.S */ 2820 /* File: armv5te/OP_SGET.S */ 2821 /* 2822 * General 32-bit SGET handler. 2823 * 2824 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2825 */ 2826 /* op vAA, field@BBBB */ 2827 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2828 FETCH(r1, 1) @ r1<- field ref BBBB 2829 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2830 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2831 cmp r0, #0 @ is resolved entry null? 2832 beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2833 .LOP_SGET_CHAR_finish: @ field ptr in r0 2834 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2835 @ no-op @ acquiring load 2836 mov r2, rINST, lsr #8 @ r2<- AA 2837 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2838 SET_VREG(r1, r2) @ fp[AA]<- r1 2839 GET_INST_OPCODE(ip) @ extract opcode from rINST 2840 GOTO_OPCODE(ip) @ jump to next instruction 2841 2842 2843 /* ------------------------------ */ 2844 .balign 64 2845 .L_OP_SGET_SHORT: /* 0x66 */ 2846 /* File: armv5te/OP_SGET_SHORT.S */ 2847 /* File: armv5te/OP_SGET.S */ 2848 /* 2849 * General 32-bit SGET handler. 2850 * 2851 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2852 */ 2853 /* op vAA, field@BBBB */ 2854 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2855 FETCH(r1, 1) @ r1<- field ref BBBB 2856 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2857 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2858 cmp r0, #0 @ is resolved entry null? 2859 beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2860 .LOP_SGET_SHORT_finish: @ field ptr in r0 2861 ldr r1, [r0, #offStaticField_value] @ r1<- field value 2862 @ no-op @ acquiring load 2863 mov r2, rINST, lsr #8 @ r2<- AA 2864 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2865 SET_VREG(r1, r2) @ fp[AA]<- r1 2866 GET_INST_OPCODE(ip) @ extract opcode from rINST 2867 GOTO_OPCODE(ip) @ jump to next instruction 2868 2869 2870 /* ------------------------------ */ 2871 .balign 64 2872 .L_OP_SPUT: /* 0x67 */ 2873 /* File: armv5te/OP_SPUT.S */ 2874 /* 2875 * General 32-bit SPUT handler. 2876 * 2877 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2878 */ 2879 /* op vAA, field@BBBB */ 2880 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2881 FETCH(r1, 1) @ r1<- field ref BBBB 2882 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2883 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2884 cmp r0, #0 @ is resolved entry null? 2885 beq .LOP_SPUT_resolve @ yes, do resolve 2886 .LOP_SPUT_finish: @ field ptr in r0 2887 mov r2, rINST, lsr #8 @ r2<- AA 2888 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2889 GET_VREG(r1, r2) @ r1<- fp[AA] 2890 GET_INST_OPCODE(ip) @ extract opcode from rINST 2891 @ no-op @ releasing store 2892 str r1, [r0, #offStaticField_value] @ field<- vAA 2893 @ no-op 2894 GOTO_OPCODE(ip) @ jump to next instruction 2895 2896 /* ------------------------------ */ 2897 .balign 64 2898 .L_OP_SPUT_WIDE: /* 0x68 */ 2899 /* File: armv5te/OP_SPUT_WIDE.S */ 2900 /* 2901 * 64-bit SPUT handler. 2902 */ 2903 /* sput-wide vAA, field@BBBB */ 2904 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 2905 FETCH(r1, 1) @ r1<- field ref BBBB 2906 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2907 mov r9, rINST, lsr #8 @ r9<- AA 2908 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr 2909 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2910 cmp r2, #0 @ is resolved entry null? 2911 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 2912 .LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 2913 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2914 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 2915 GET_INST_OPCODE(r10) @ extract opcode from rINST 2916 .if 0 2917 add r2, r2, #offStaticField_value @ r2<- pointer to data 2918 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 2919 .else 2920 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 2921 .endif 2922 GOTO_OPCODE(r10) @ jump to next instruction 2923 2924 /* ------------------------------ */ 2925 .balign 64 2926 .L_OP_SPUT_OBJECT: /* 0x69 */ 2927 /* File: armv5te/OP_SPUT_OBJECT.S */ 2928 /* 2929 * 32-bit SPUT handler for objects 2930 * 2931 * for: sput-object, sput-object-volatile 2932 */ 2933 /* op vAA, field@BBBB */ 2934 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2935 FETCH(r1, 1) @ r1<- field ref BBBB 2936 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2937 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2938 cmp r0, #0 @ is resolved entry null? 2939 beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 2940 .LOP_SPUT_OBJECT_finish: @ field ptr in r0 2941 mov r2, rINST, lsr #8 @ r2<- AA 2942 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2943 GET_VREG(r1, r2) @ r1<- fp[AA] 2944 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 2945 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 2946 GET_INST_OPCODE(ip) @ extract opcode from rINST 2947 @ no-op @ releasing store 2948 b .LOP_SPUT_OBJECT_end 2949 2950 /* ------------------------------ */ 2951 .balign 64 2952 .L_OP_SPUT_BOOLEAN: /* 0x6a */ 2953 /* File: armv5te/OP_SPUT_BOOLEAN.S */ 2954 /* File: armv5te/OP_SPUT.S */ 2955 /* 2956 * General 32-bit SPUT handler. 2957 * 2958 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2959 */ 2960 /* op vAA, field@BBBB */ 2961 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2962 FETCH(r1, 1) @ r1<- field ref BBBB 2963 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2964 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2965 cmp r0, #0 @ is resolved entry null? 2966 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 2967 .LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 2968 mov r2, rINST, lsr #8 @ r2<- AA 2969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2970 GET_VREG(r1, r2) @ r1<- fp[AA] 2971 GET_INST_OPCODE(ip) @ extract opcode from rINST 2972 @ no-op @ releasing store 2973 str r1, [r0, #offStaticField_value] @ field<- vAA 2974 @ no-op 2975 GOTO_OPCODE(ip) @ jump to next instruction 2976 2977 2978 /* ------------------------------ */ 2979 .balign 64 2980 .L_OP_SPUT_BYTE: /* 0x6b */ 2981 /* File: armv5te/OP_SPUT_BYTE.S */ 2982 /* File: armv5te/OP_SPUT.S */ 2983 /* 2984 * General 32-bit SPUT handler. 2985 * 2986 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2987 */ 2988 /* op vAA, field@BBBB */ 2989 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 2990 FETCH(r1, 1) @ r1<- field ref BBBB 2991 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 2992 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 2993 cmp r0, #0 @ is resolved entry null? 2994 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 2995 .LOP_SPUT_BYTE_finish: @ field ptr in r0 2996 mov r2, rINST, lsr #8 @ r2<- AA 2997 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2998 GET_VREG(r1, r2) @ r1<- fp[AA] 2999 GET_INST_OPCODE(ip) @ extract opcode from rINST 3000 @ no-op @ releasing store 3001 str r1, [r0, #offStaticField_value] @ field<- vAA 3002 @ no-op 3003 GOTO_OPCODE(ip) @ jump to next instruction 3004 3005 3006 /* ------------------------------ */ 3007 .balign 64 3008 .L_OP_SPUT_CHAR: /* 0x6c */ 3009 /* File: armv5te/OP_SPUT_CHAR.S */ 3010 /* File: armv5te/OP_SPUT.S */ 3011 /* 3012 * General 32-bit SPUT handler. 3013 * 3014 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3015 */ 3016 /* op vAA, field@BBBB */ 3017 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3018 FETCH(r1, 1) @ r1<- field ref BBBB 3019 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 3020 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 3021 cmp r0, #0 @ is resolved entry null? 3022 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3023 .LOP_SPUT_CHAR_finish: @ field ptr in r0 3024 mov r2, rINST, lsr #8 @ r2<- AA 3025 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3026 GET_VREG(r1, r2) @ r1<- fp[AA] 3027 GET_INST_OPCODE(ip) @ extract opcode from rINST 3028 @ no-op @ releasing store 3029 str r1, [r0, #offStaticField_value] @ field<- vAA 3030 @ no-op 3031 GOTO_OPCODE(ip) @ jump to next instruction 3032 3033 3034 /* ------------------------------ */ 3035 .balign 64 3036 .L_OP_SPUT_SHORT: /* 0x6d */ 3037 /* File: armv5te/OP_SPUT_SHORT.S */ 3038 /* File: armv5te/OP_SPUT.S */ 3039 /* 3040 * General 32-bit SPUT handler. 3041 * 3042 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3043 */ 3044 /* op vAA, field@BBBB */ 3045 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 3046 FETCH(r1, 1) @ r1<- field ref BBBB 3047 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 3048 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 3049 cmp r0, #0 @ is resolved entry null? 3050 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3051 .LOP_SPUT_SHORT_finish: @ field ptr in r0 3052 mov r2, rINST, lsr #8 @ r2<- AA 3053 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3054 GET_VREG(r1, r2) @ r1<- fp[AA] 3055 GET_INST_OPCODE(ip) @ extract opcode from rINST 3056 @ no-op @ releasing store 3057 str r1, [r0, #offStaticField_value] @ field<- vAA 3058 @ no-op 3059 GOTO_OPCODE(ip) @ jump to next instruction 3060 3061 3062 /* ------------------------------ */ 3063 .balign 64 3064 .L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3065 /* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3066 /* 3067 * Handle a virtual method call. 3068 * 3069 * for: invoke-virtual, invoke-virtual/range 3070 */ 3071 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3072 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3073 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3074 FETCH(r1, 1) @ r1<- BBBB 3075 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3076 FETCH(r10, 2) @ r10<- GFED or CCCC 3077 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3078 .if (!0) 3079 and r10, r10, #15 @ r10<- D (or stays CCCC) 3080 .endif 3081 cmp r0, #0 @ already resolved? 3082 EXPORT_PC() @ must export for invoke 3083 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3084 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3085 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3086 mov r2, #METHOD_VIRTUAL @ resolver method type 3087 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3088 cmp r0, #0 @ got null? 3089 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3090 b common_exceptionThrown @ yes, handle exception 3091 3092 /* ------------------------------ */ 3093 .balign 64 3094 .L_OP_INVOKE_SUPER: /* 0x6f */ 3095 /* File: armv5te/OP_INVOKE_SUPER.S */ 3096 /* 3097 * Handle a "super" method call. 3098 * 3099 * for: invoke-super, invoke-super/range 3100 */ 3101 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3102 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3103 FETCH(r10, 2) @ r10<- GFED or CCCC 3104 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3105 .if (!0) 3106 and r10, r10, #15 @ r10<- D (or stays CCCC) 3107 .endif 3108 FETCH(r1, 1) @ r1<- BBBB 3109 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3110 GET_VREG(r9, r10) @ r9<- "this" ptr 3111 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3112 cmp r9, #0 @ null "this"? 3113 ldr r10, [rSELF, #offThread_method] @ r10<- current method 3114 beq common_errNullObject @ null "this", throw exception 3115 cmp r0, #0 @ already resolved? 3116 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz 3117 EXPORT_PC() @ must export for invoke 3118 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3119 b .LOP_INVOKE_SUPER_resolve @ do resolve now 3120 3121 /* ------------------------------ */ 3122 .balign 64 3123 .L_OP_INVOKE_DIRECT: /* 0x70 */ 3124 /* File: armv5te/OP_INVOKE_DIRECT.S */ 3125 /* 3126 * Handle a direct method call. 3127 * 3128 * (We could defer the "is 'this' pointer null" test to the common 3129 * method invocation code, and use a flag to indicate that static 3130 * calls don't count. If we do this as part of copying the arguments 3131 * out we could avoiding loading the first arg twice.) 3132 * 3133 * for: invoke-direct, invoke-direct/range 3134 */ 3135 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3136 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3137 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3138 FETCH(r1, 1) @ r1<- BBBB 3139 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3140 FETCH(r10, 2) @ r10<- GFED or CCCC 3141 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3142 .if (!0) 3143 and r10, r10, #15 @ r10<- D (or stays CCCC) 3144 .endif 3145 cmp r0, #0 @ already resolved? 3146 EXPORT_PC() @ must export for invoke 3147 GET_VREG(r9, r10) @ r9<- "this" ptr 3148 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3149 .LOP_INVOKE_DIRECT_finish: 3150 cmp r9, #0 @ null "this" ref? 3151 bne common_invokeMethodNoRange @ r0=method, r9="this" 3152 b common_errNullObject @ yes, throw exception 3153 3154 /* ------------------------------ */ 3155 .balign 64 3156 .L_OP_INVOKE_STATIC: /* 0x71 */ 3157 /* File: armv5te/OP_INVOKE_STATIC.S */ 3158 /* 3159 * Handle a static method call. 3160 * 3161 * for: invoke-static, invoke-static/range 3162 */ 3163 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3164 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3165 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3166 FETCH(r1, 1) @ r1<- BBBB 3167 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3168 mov r9, #0 @ null "this" in delay slot 3169 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3170 #if defined(WITH_JIT) 3171 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall 3172 #endif 3173 cmp r0, #0 @ already resolved? 3174 EXPORT_PC() @ must export for invoke 3175 bne common_invokeMethodNoRange @ yes, continue on 3176 b .LOP_INVOKE_STATIC_resolve 3177 3178 /* ------------------------------ */ 3179 .balign 64 3180 .L_OP_INVOKE_INTERFACE: /* 0x72 */ 3181 /* File: armv5te/OP_INVOKE_INTERFACE.S */ 3182 /* 3183 * Handle an interface method call. 3184 * 3185 * for: invoke-interface, invoke-interface/range 3186 */ 3187 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3188 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3189 FETCH(r2, 2) @ r2<- FEDC or CCCC 3190 FETCH(r1, 1) @ r1<- BBBB 3191 .if (!0) 3192 and r2, r2, #15 @ r2<- C (or stays CCCC) 3193 .endif 3194 EXPORT_PC() @ must export for invoke 3195 GET_VREG(r9, r2) @ r9<- first arg ("this") 3196 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3197 cmp r9, #0 @ null obj? 3198 ldr r2, [rSELF, #offThread_method] @ r2<- method 3199 beq common_errNullObject @ yes, fail 3200 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz 3201 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3202 cmp r0, #0 @ failed? 3203 beq common_exceptionThrown @ yes, handle exception 3204 b common_invokeMethodNoRange @ (r0=method, r9="this") 3205 3206 /* ------------------------------ */ 3207 .balign 64 3208 .L_OP_UNUSED_73: /* 0x73 */ 3209 /* File: armv5te/OP_UNUSED_73.S */ 3210 /* File: armv5te/unused.S */ 3211 bl common_abort 3212 3213 3214 /* ------------------------------ */ 3215 .balign 64 3216 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3217 /* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3218 /* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3219 /* 3220 * Handle a virtual method call. 3221 * 3222 * for: invoke-virtual, invoke-virtual/range 3223 */ 3224 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3225 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3226 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3227 FETCH(r1, 1) @ r1<- BBBB 3228 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3229 FETCH(r10, 2) @ r10<- GFED or CCCC 3230 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3231 .if (!1) 3232 and r10, r10, #15 @ r10<- D (or stays CCCC) 3233 .endif 3234 cmp r0, #0 @ already resolved? 3235 EXPORT_PC() @ must export for invoke 3236 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3237 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 3238 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3239 mov r2, #METHOD_VIRTUAL @ resolver method type 3240 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3241 cmp r0, #0 @ got null? 3242 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3243 b common_exceptionThrown @ yes, handle exception 3244 3245 3246 /* ------------------------------ */ 3247 .balign 64 3248 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3249 /* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3250 /* File: armv5te/OP_INVOKE_SUPER.S */ 3251 /* 3252 * Handle a "super" method call. 3253 * 3254 * for: invoke-super, invoke-super/range 3255 */ 3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3257 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3258 FETCH(r10, 2) @ r10<- GFED or CCCC 3259 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3260 .if (!1) 3261 and r10, r10, #15 @ r10<- D (or stays CCCC) 3262 .endif 3263 FETCH(r1, 1) @ r1<- BBBB 3264 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3265 GET_VREG(r9, r10) @ r9<- "this" ptr 3266 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3267 cmp r9, #0 @ null "this"? 3268 ldr r10, [rSELF, #offThread_method] @ r10<- current method 3269 beq common_errNullObject @ null "this", throw exception 3270 cmp r0, #0 @ already resolved? 3271 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz 3272 EXPORT_PC() @ must export for invoke 3273 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3274 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3275 3276 3277 /* ------------------------------ */ 3278 .balign 64 3279 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3280 /* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3281 /* File: armv5te/OP_INVOKE_DIRECT.S */ 3282 /* 3283 * Handle a direct method call. 3284 * 3285 * (We could defer the "is 'this' pointer null" test to the common 3286 * method invocation code, and use a flag to indicate that static 3287 * calls don't count. If we do this as part of copying the arguments 3288 * out we could avoiding loading the first arg twice.) 3289 * 3290 * for: invoke-direct, invoke-direct/range 3291 */ 3292 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3293 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3294 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3295 FETCH(r1, 1) @ r1<- BBBB 3296 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3297 FETCH(r10, 2) @ r10<- GFED or CCCC 3298 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3299 .if (!1) 3300 and r10, r10, #15 @ r10<- D (or stays CCCC) 3301 .endif 3302 cmp r0, #0 @ already resolved? 3303 EXPORT_PC() @ must export for invoke 3304 GET_VREG(r9, r10) @ r9<- "this" ptr 3305 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3306 .LOP_INVOKE_DIRECT_RANGE_finish: 3307 cmp r9, #0 @ null "this" ref? 3308 bne common_invokeMethodRange @ r0=method, r9="this" 3309 b common_errNullObject @ yes, throw exception 3310 3311 3312 /* ------------------------------ */ 3313 .balign 64 3314 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3315 /* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3316 /* File: armv5te/OP_INVOKE_STATIC.S */ 3317 /* 3318 * Handle a static method call. 3319 * 3320 * for: invoke-static, invoke-static/range 3321 */ 3322 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3323 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3324 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 3325 FETCH(r1, 1) @ r1<- BBBB 3326 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3327 mov r9, #0 @ null "this" in delay slot 3328 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3329 #if defined(WITH_JIT) 3330 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall 3331 #endif 3332 cmp r0, #0 @ already resolved? 3333 EXPORT_PC() @ must export for invoke 3334 bne common_invokeMethodRange @ yes, continue on 3335 b .LOP_INVOKE_STATIC_RANGE_resolve 3336 3337 3338 /* ------------------------------ */ 3339 .balign 64 3340 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3341 /* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3342 /* File: armv5te/OP_INVOKE_INTERFACE.S */ 3343 /* 3344 * Handle an interface method call. 3345 * 3346 * for: invoke-interface, invoke-interface/range 3347 */ 3348 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3349 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3350 FETCH(r2, 2) @ r2<- FEDC or CCCC 3351 FETCH(r1, 1) @ r1<- BBBB 3352 .if (!1) 3353 and r2, r2, #15 @ r2<- C (or stays CCCC) 3354 .endif 3355 EXPORT_PC() @ must export for invoke 3356 GET_VREG(r9, r2) @ r9<- first arg ("this") 3357 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 3358 cmp r9, #0 @ null obj? 3359 ldr r2, [rSELF, #offThread_method] @ r2<- method 3360 beq common_errNullObject @ yes, fail 3361 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz 3362 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3363 cmp r0, #0 @ failed? 3364 beq common_exceptionThrown @ yes, handle exception 3365 b common_invokeMethodRange @ (r0=method, r9="this") 3366 3367 3368 /* ------------------------------ */ 3369 .balign 64 3370 .L_OP_UNUSED_79: /* 0x79 */ 3371 /* File: armv5te/OP_UNUSED_79.S */ 3372 /* File: armv5te/unused.S */ 3373 bl common_abort 3374 3375 3376 /* ------------------------------ */ 3377 .balign 64 3378 .L_OP_UNUSED_7A: /* 0x7a */ 3379 /* File: armv5te/OP_UNUSED_7A.S */ 3380 /* File: armv5te/unused.S */ 3381 bl common_abort 3382 3383 3384 /* ------------------------------ */ 3385 .balign 64 3386 .L_OP_NEG_INT: /* 0x7b */ 3387 /* File: armv5te/OP_NEG_INT.S */ 3388 /* File: armv5te/unop.S */ 3389 /* 3390 * Generic 32-bit unary operation. Provide an "instr" line that 3391 * specifies an instruction that performs "result = op r0". 3392 * This could be an ARM instruction or a function call. 3393 * 3394 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3395 * int-to-byte, int-to-char, int-to-short 3396 */ 3397 /* unop vA, vB */ 3398 mov r3, rINST, lsr #12 @ r3<- B 3399 mov r9, rINST, lsr #8 @ r9<- A+ 3400 GET_VREG(r0, r3) @ r0<- vB 3401 and r9, r9, #15 3402 @ optional op; may set condition codes 3403 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3404 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3405 GET_INST_OPCODE(ip) @ extract opcode from rINST 3406 SET_VREG(r0, r9) @ vAA<- r0 3407 GOTO_OPCODE(ip) @ jump to next instruction 3408 /* 9-10 instructions */ 3409 3410 3411 /* ------------------------------ */ 3412 .balign 64 3413 .L_OP_NOT_INT: /* 0x7c */ 3414 /* File: armv5te/OP_NOT_INT.S */ 3415 /* File: armv5te/unop.S */ 3416 /* 3417 * Generic 32-bit unary operation. Provide an "instr" line that 3418 * specifies an instruction that performs "result = op r0". 3419 * This could be an ARM instruction or a function call. 3420 * 3421 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3422 * int-to-byte, int-to-char, int-to-short 3423 */ 3424 /* unop vA, vB */ 3425 mov r3, rINST, lsr #12 @ r3<- B 3426 mov r9, rINST, lsr #8 @ r9<- A+ 3427 GET_VREG(r0, r3) @ r0<- vB 3428 and r9, r9, #15 3429 @ optional op; may set condition codes 3430 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3431 mvn r0, r0 @ r0<- op, r0-r3 changed 3432 GET_INST_OPCODE(ip) @ extract opcode from rINST 3433 SET_VREG(r0, r9) @ vAA<- r0 3434 GOTO_OPCODE(ip) @ jump to next instruction 3435 /* 9-10 instructions */ 3436 3437 3438 /* ------------------------------ */ 3439 .balign 64 3440 .L_OP_NEG_LONG: /* 0x7d */ 3441 /* File: armv5te/OP_NEG_LONG.S */ 3442 /* File: armv5te/unopWide.S */ 3443 /* 3444 * Generic 64-bit unary operation. Provide an "instr" line that 3445 * specifies an instruction that performs "result = op r0/r1". 3446 * This could be an ARM instruction or a function call. 3447 * 3448 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3449 */ 3450 /* unop vA, vB */ 3451 mov r9, rINST, lsr #8 @ r9<- A+ 3452 mov r3, rINST, lsr #12 @ r3<- B 3453 and r9, r9, #15 3454 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3455 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3456 ldmia r3, {r0-r1} @ r0/r1<- vAA 3457 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3458 rsbs r0, r0, #0 @ optional op; may set condition codes 3459 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3460 GET_INST_OPCODE(ip) @ extract opcode from rINST 3461 stmia r9, {r0-r1} @ vAA<- r0/r1 3462 GOTO_OPCODE(ip) @ jump to next instruction 3463 /* 12-13 instructions */ 3464 3465 3466 /* ------------------------------ */ 3467 .balign 64 3468 .L_OP_NOT_LONG: /* 0x7e */ 3469 /* File: armv5te/OP_NOT_LONG.S */ 3470 /* File: armv5te/unopWide.S */ 3471 /* 3472 * Generic 64-bit unary operation. Provide an "instr" line that 3473 * specifies an instruction that performs "result = op r0/r1". 3474 * This could be an ARM instruction or a function call. 3475 * 3476 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3477 */ 3478 /* unop vA, vB */ 3479 mov r9, rINST, lsr #8 @ r9<- A+ 3480 mov r3, rINST, lsr #12 @ r3<- B 3481 and r9, r9, #15 3482 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3483 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3484 ldmia r3, {r0-r1} @ r0/r1<- vAA 3485 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3486 mvn r0, r0 @ optional op; may set condition codes 3487 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3488 GET_INST_OPCODE(ip) @ extract opcode from rINST 3489 stmia r9, {r0-r1} @ vAA<- r0/r1 3490 GOTO_OPCODE(ip) @ jump to next instruction 3491 /* 12-13 instructions */ 3492 3493 3494 /* ------------------------------ */ 3495 .balign 64 3496 .L_OP_NEG_FLOAT: /* 0x7f */ 3497 /* File: armv5te/OP_NEG_FLOAT.S */ 3498 /* File: armv5te/unop.S */ 3499 /* 3500 * Generic 32-bit unary operation. Provide an "instr" line that 3501 * specifies an instruction that performs "result = op r0". 3502 * This could be an ARM instruction or a function call. 3503 * 3504 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3505 * int-to-byte, int-to-char, int-to-short 3506 */ 3507 /* unop vA, vB */ 3508 mov r3, rINST, lsr #12 @ r3<- B 3509 mov r9, rINST, lsr #8 @ r9<- A+ 3510 GET_VREG(r0, r3) @ r0<- vB 3511 and r9, r9, #15 3512 @ optional op; may set condition codes 3513 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3514 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3515 GET_INST_OPCODE(ip) @ extract opcode from rINST 3516 SET_VREG(r0, r9) @ vAA<- r0 3517 GOTO_OPCODE(ip) @ jump to next instruction 3518 /* 9-10 instructions */ 3519 3520 3521 /* ------------------------------ */ 3522 .balign 64 3523 .L_OP_NEG_DOUBLE: /* 0x80 */ 3524 /* File: armv5te/OP_NEG_DOUBLE.S */ 3525 /* File: armv5te/unopWide.S */ 3526 /* 3527 * Generic 64-bit unary operation. Provide an "instr" line that 3528 * specifies an instruction that performs "result = op r0/r1". 3529 * This could be an ARM instruction or a function call. 3530 * 3531 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3532 */ 3533 /* unop vA, vB */ 3534 mov r9, rINST, lsr #8 @ r9<- A+ 3535 mov r3, rINST, lsr #12 @ r3<- B 3536 and r9, r9, #15 3537 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3538 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3539 ldmia r3, {r0-r1} @ r0/r1<- vAA 3540 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3541 @ optional op; may set condition codes 3542 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3543 GET_INST_OPCODE(ip) @ extract opcode from rINST 3544 stmia r9, {r0-r1} @ vAA<- r0/r1 3545 GOTO_OPCODE(ip) @ jump to next instruction 3546 /* 12-13 instructions */ 3547 3548 3549 /* ------------------------------ */ 3550 .balign 64 3551 .L_OP_INT_TO_LONG: /* 0x81 */ 3552 /* File: armv5te/OP_INT_TO_LONG.S */ 3553 /* File: armv5te/unopWider.S */ 3554 /* 3555 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3556 * that specifies an instruction that performs "result = op r0", where 3557 * "result" is a 64-bit quantity in r0/r1. 3558 * 3559 * For: int-to-long, int-to-double, float-to-long, float-to-double 3560 */ 3561 /* unop vA, vB */ 3562 mov r9, rINST, lsr #8 @ r9<- A+ 3563 mov r3, rINST, lsr #12 @ r3<- B 3564 and r9, r9, #15 3565 GET_VREG(r0, r3) @ r0<- vB 3566 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3567 @ optional op; may set condition codes 3568 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3569 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3570 GET_INST_OPCODE(ip) @ extract opcode from rINST 3571 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3572 GOTO_OPCODE(ip) @ jump to next instruction 3573 /* 10-11 instructions */ 3574 3575 3576 /* ------------------------------ */ 3577 .balign 64 3578 .L_OP_INT_TO_FLOAT: /* 0x82 */ 3579 /* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3580 /* File: arm-vfp/funop.S */ 3581 /* 3582 * Generic 32-bit unary floating-point operation. Provide an "instr" 3583 * line that specifies an instruction that performs "s1 = op s0". 3584 * 3585 * for: int-to-float, float-to-int 3586 */ 3587 /* unop vA, vB */ 3588 mov r3, rINST, lsr #12 @ r3<- B 3589 mov r9, rINST, lsr #8 @ r9<- A+ 3590 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3591 flds s0, [r3] @ s0<- vB 3592 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3593 and r9, r9, #15 @ r9<- A 3594 fsitos s1, s0 @ s1<- op 3595 GET_INST_OPCODE(ip) @ extract opcode from rINST 3596 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3597 fsts s1, [r9] @ vA<- s1 3598 GOTO_OPCODE(ip) @ jump to next instruction 3599 3600 3601 /* ------------------------------ */ 3602 .balign 64 3603 .L_OP_INT_TO_DOUBLE: /* 0x83 */ 3604 /* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3605 /* File: arm-vfp/funopWider.S */ 3606 /* 3607 * Generic 32bit-to-64bit floating point unary operation. Provide an 3608 * "instr" line that specifies an instruction that performs "d0 = op s0". 3609 * 3610 * For: int-to-double, float-to-double 3611 */ 3612 /* unop vA, vB */ 3613 mov r3, rINST, lsr #12 @ r3<- B 3614 mov r9, rINST, lsr #8 @ r9<- A+ 3615 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3616 flds s0, [r3] @ s0<- vB 3617 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3618 and r9, r9, #15 @ r9<- A 3619 fsitod d0, s0 @ d0<- op 3620 GET_INST_OPCODE(ip) @ extract opcode from rINST 3621 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3622 fstd d0, [r9] @ vA<- d0 3623 GOTO_OPCODE(ip) @ jump to next instruction 3624 3625 3626 /* ------------------------------ */ 3627 .balign 64 3628 .L_OP_LONG_TO_INT: /* 0x84 */ 3629 /* File: armv5te/OP_LONG_TO_INT.S */ 3630 /* we ignore the high word, making this equivalent to a 32-bit reg move */ 3631 /* File: armv5te/OP_MOVE.S */ 3632 /* for move, move-object, long-to-int */ 3633 /* op vA, vB */ 3634 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3635 mov r0, rINST, lsr #8 @ r0<- A from 11:8 3636 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3637 GET_VREG(r2, r1) @ r2<- fp[B] 3638 and r0, r0, #15 3639 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3640 SET_VREG(r2, r0) @ fp[A]<- r2 3641 GOTO_OPCODE(ip) @ execute next instruction 3642 3643 3644 /* ------------------------------ */ 3645 .balign 64 3646 .L_OP_LONG_TO_FLOAT: /* 0x85 */ 3647 /* File: armv5te/OP_LONG_TO_FLOAT.S */ 3648 /* File: armv5te/unopNarrower.S */ 3649 /* 3650 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3651 * that specifies an instruction that performs "result = op r0/r1", where 3652 * "result" is a 32-bit quantity in r0. 3653 * 3654 * For: long-to-float, double-to-int, double-to-float 3655 * 3656 * (This would work for long-to-int, but that instruction is actually 3657 * an exact match for OP_MOVE.) 3658 */ 3659 /* unop vA, vB */ 3660 mov r3, rINST, lsr #12 @ r3<- B 3661 mov r9, rINST, lsr #8 @ r9<- A+ 3662 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3663 and r9, r9, #15 3664 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3665 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3666 @ optional op; may set condition codes 3667 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3668 GET_INST_OPCODE(ip) @ extract opcode from rINST 3669 SET_VREG(r0, r9) @ vA<- r0 3670 GOTO_OPCODE(ip) @ jump to next instruction 3671 /* 10-11 instructions */ 3672 3673 3674 /* ------------------------------ */ 3675 .balign 64 3676 .L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3677 /* File: armv5te/OP_LONG_TO_DOUBLE.S */ 3678 /* File: armv5te/unopWide.S */ 3679 /* 3680 * Generic 64-bit unary operation. Provide an "instr" line that 3681 * specifies an instruction that performs "result = op r0/r1". 3682 * This could be an ARM instruction or a function call. 3683 * 3684 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3685 */ 3686 /* unop vA, vB */ 3687 mov r9, rINST, lsr #8 @ r9<- A+ 3688 mov r3, rINST, lsr #12 @ r3<- B 3689 and r9, r9, #15 3690 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3691 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3692 ldmia r3, {r0-r1} @ r0/r1<- vAA 3693 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3694 @ optional op; may set condition codes 3695 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3696 GET_INST_OPCODE(ip) @ extract opcode from rINST 3697 stmia r9, {r0-r1} @ vAA<- r0/r1 3698 GOTO_OPCODE(ip) @ jump to next instruction 3699 /* 12-13 instructions */ 3700 3701 3702 /* ------------------------------ */ 3703 .balign 64 3704 .L_OP_FLOAT_TO_INT: /* 0x87 */ 3705 /* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3706 /* File: arm-vfp/funop.S */ 3707 /* 3708 * Generic 32-bit unary floating-point operation. Provide an "instr" 3709 * line that specifies an instruction that performs "s1 = op s0". 3710 * 3711 * for: int-to-float, float-to-int 3712 */ 3713 /* unop vA, vB */ 3714 mov r3, rINST, lsr #12 @ r3<- B 3715 mov r9, rINST, lsr #8 @ r9<- A+ 3716 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3717 flds s0, [r3] @ s0<- vB 3718 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3719 and r9, r9, #15 @ r9<- A 3720 ftosizs s1, s0 @ s1<- op 3721 GET_INST_OPCODE(ip) @ extract opcode from rINST 3722 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3723 fsts s1, [r9] @ vA<- s1 3724 GOTO_OPCODE(ip) @ jump to next instruction 3725 3726 3727 /* ------------------------------ */ 3728 .balign 64 3729 .L_OP_FLOAT_TO_LONG: /* 0x88 */ 3730 /* File: armv5te/OP_FLOAT_TO_LONG.S */ 3731 @include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3732 /* File: armv5te/unopWider.S */ 3733 /* 3734 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3735 * that specifies an instruction that performs "result = op r0", where 3736 * "result" is a 64-bit quantity in r0/r1. 3737 * 3738 * For: int-to-long, int-to-double, float-to-long, float-to-double 3739 */ 3740 /* unop vA, vB */ 3741 mov r9, rINST, lsr #8 @ r9<- A+ 3742 mov r3, rINST, lsr #12 @ r3<- B 3743 and r9, r9, #15 3744 GET_VREG(r0, r3) @ r0<- vB 3745 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3746 @ optional op; may set condition codes 3747 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3748 bl f2l_doconv @ r0<- op, r0-r3 changed 3749 GET_INST_OPCODE(ip) @ extract opcode from rINST 3750 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3751 GOTO_OPCODE(ip) @ jump to next instruction 3752 /* 10-11 instructions */ 3753 3754 3755 3756 /* ------------------------------ */ 3757 .balign 64 3758 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3759 /* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3760 /* File: arm-vfp/funopWider.S */ 3761 /* 3762 * Generic 32bit-to-64bit floating point unary operation. Provide an 3763 * "instr" line that specifies an instruction that performs "d0 = op s0". 3764 * 3765 * For: int-to-double, float-to-double 3766 */ 3767 /* unop vA, vB */ 3768 mov r3, rINST, lsr #12 @ r3<- B 3769 mov r9, rINST, lsr #8 @ r9<- A+ 3770 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3771 flds s0, [r3] @ s0<- vB 3772 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3773 and r9, r9, #15 @ r9<- A 3774 fcvtds d0, s0 @ d0<- op 3775 GET_INST_OPCODE(ip) @ extract opcode from rINST 3776 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3777 fstd d0, [r9] @ vA<- d0 3778 GOTO_OPCODE(ip) @ jump to next instruction 3779 3780 3781 /* ------------------------------ */ 3782 .balign 64 3783 .L_OP_DOUBLE_TO_INT: /* 0x8a */ 3784 /* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3785 /* File: arm-vfp/funopNarrower.S */ 3786 /* 3787 * Generic 64bit-to-32bit unary floating point operation. Provide an 3788 * "instr" line that specifies an instruction that performs "s0 = op d0". 3789 * 3790 * For: double-to-int, double-to-float 3791 */ 3792 /* unop vA, vB */ 3793 mov r3, rINST, lsr #12 @ r3<- B 3794 mov r9, rINST, lsr #8 @ r9<- A+ 3795 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3796 fldd d0, [r3] @ d0<- vB 3797 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3798 and r9, r9, #15 @ r9<- A 3799 ftosizd s0, d0 @ s0<- op 3800 GET_INST_OPCODE(ip) @ extract opcode from rINST 3801 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3802 fsts s0, [r9] @ vA<- s0 3803 GOTO_OPCODE(ip) @ jump to next instruction 3804 3805 3806 /* ------------------------------ */ 3807 .balign 64 3808 .L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3809 /* File: armv5te/OP_DOUBLE_TO_LONG.S */ 3810 @include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3811 /* File: armv5te/unopWide.S */ 3812 /* 3813 * Generic 64-bit unary operation. Provide an "instr" line that 3814 * specifies an instruction that performs "result = op r0/r1". 3815 * This could be an ARM instruction or a function call. 3816 * 3817 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3818 */ 3819 /* unop vA, vB */ 3820 mov r9, rINST, lsr #8 @ r9<- A+ 3821 mov r3, rINST, lsr #12 @ r3<- B 3822 and r9, r9, #15 3823 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3824 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3825 ldmia r3, {r0-r1} @ r0/r1<- vAA 3826 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3827 @ optional op; may set condition codes 3828 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3829 GET_INST_OPCODE(ip) @ extract opcode from rINST 3830 stmia r9, {r0-r1} @ vAA<- r0/r1 3831 GOTO_OPCODE(ip) @ jump to next instruction 3832 /* 12-13 instructions */ 3833 3834 3835 3836 /* ------------------------------ */ 3837 .balign 64 3838 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3839 /* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3840 /* File: arm-vfp/funopNarrower.S */ 3841 /* 3842 * Generic 64bit-to-32bit unary floating point operation. Provide an 3843 * "instr" line that specifies an instruction that performs "s0 = op d0". 3844 * 3845 * For: double-to-int, double-to-float 3846 */ 3847 /* unop vA, vB */ 3848 mov r3, rINST, lsr #12 @ r3<- B 3849 mov r9, rINST, lsr #8 @ r9<- A+ 3850 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3851 fldd d0, [r3] @ d0<- vB 3852 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3853 and r9, r9, #15 @ r9<- A 3854 fcvtsd s0, d0 @ s0<- op 3855 GET_INST_OPCODE(ip) @ extract opcode from rINST 3856 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3857 fsts s0, [r9] @ vA<- s0 3858 GOTO_OPCODE(ip) @ jump to next instruction 3859 3860 3861 /* ------------------------------ */ 3862 .balign 64 3863 .L_OP_INT_TO_BYTE: /* 0x8d */ 3864 /* File: armv5te/OP_INT_TO_BYTE.S */ 3865 /* File: armv5te/unop.S */ 3866 /* 3867 * Generic 32-bit unary operation. Provide an "instr" line that 3868 * specifies an instruction that performs "result = op r0". 3869 * This could be an ARM instruction or a function call. 3870 * 3871 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3872 * int-to-byte, int-to-char, int-to-short 3873 */ 3874 /* unop vA, vB */ 3875 mov r3, rINST, lsr #12 @ r3<- B 3876 mov r9, rINST, lsr #8 @ r9<- A+ 3877 GET_VREG(r0, r3) @ r0<- vB 3878 and r9, r9, #15 3879 mov r0, r0, asl #24 @ optional op; may set condition codes 3880 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3881 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed 3882 GET_INST_OPCODE(ip) @ extract opcode from rINST 3883 SET_VREG(r0, r9) @ vAA<- r0 3884 GOTO_OPCODE(ip) @ jump to next instruction 3885 /* 9-10 instructions */ 3886 3887 3888 /* ------------------------------ */ 3889 .balign 64 3890 .L_OP_INT_TO_CHAR: /* 0x8e */ 3891 /* File: armv5te/OP_INT_TO_CHAR.S */ 3892 /* File: armv5te/unop.S */ 3893 /* 3894 * Generic 32-bit unary operation. Provide an "instr" line that 3895 * specifies an instruction that performs "result = op r0". 3896 * This could be an ARM instruction or a function call. 3897 * 3898 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3899 * int-to-byte, int-to-char, int-to-short 3900 */ 3901 /* unop vA, vB */ 3902 mov r3, rINST, lsr #12 @ r3<- B 3903 mov r9, rINST, lsr #8 @ r9<- A+ 3904 GET_VREG(r0, r3) @ r0<- vB 3905 and r9, r9, #15 3906 mov r0, r0, asl #16 @ optional op; may set condition codes 3907 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3908 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed 3909 GET_INST_OPCODE(ip) @ extract opcode from rINST 3910 SET_VREG(r0, r9) @ vAA<- r0 3911 GOTO_OPCODE(ip) @ jump to next instruction 3912 /* 9-10 instructions */ 3913 3914 3915 /* ------------------------------ */ 3916 .balign 64 3917 .L_OP_INT_TO_SHORT: /* 0x8f */ 3918 /* File: armv5te/OP_INT_TO_SHORT.S */ 3919 /* File: armv5te/unop.S */ 3920 /* 3921 * Generic 32-bit unary operation. Provide an "instr" line that 3922 * specifies an instruction that performs "result = op r0". 3923 * This could be an ARM instruction or a function call. 3924 * 3925 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3926 * int-to-byte, int-to-char, int-to-short 3927 */ 3928 /* unop vA, vB */ 3929 mov r3, rINST, lsr #12 @ r3<- B 3930 mov r9, rINST, lsr #8 @ r9<- A+ 3931 GET_VREG(r0, r3) @ r0<- vB 3932 and r9, r9, #15 3933 mov r0, r0, asl #16 @ optional op; may set condition codes 3934 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3935 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed 3936 GET_INST_OPCODE(ip) @ extract opcode from rINST 3937 SET_VREG(r0, r9) @ vAA<- r0 3938 GOTO_OPCODE(ip) @ jump to next instruction 3939 /* 9-10 instructions */ 3940 3941 3942 /* ------------------------------ */ 3943 .balign 64 3944 .L_OP_ADD_INT: /* 0x90 */ 3945 /* File: armv5te/OP_ADD_INT.S */ 3946 /* File: armv5te/binop.S */ 3947 /* 3948 * Generic 32-bit binary operation. Provide an "instr" line that 3949 * specifies an instruction that performs "result = r0 op r1". 3950 * This could be an ARM instruction or a function call. (If the result 3951 * comes back in a register other than r0, you can override "result".) 3952 * 3953 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3954 * vCC (r1). Useful for integer division and modulus. Note that we 3955 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3956 * handles it correctly. 3957 * 3958 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3959 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3960 * mul-float, div-float, rem-float 3961 */ 3962 /* binop vAA, vBB, vCC */ 3963 FETCH(r0, 1) @ r0<- CCBB 3964 mov r9, rINST, lsr #8 @ r9<- AA 3965 mov r3, r0, lsr #8 @ r3<- CC 3966 and r2, r0, #255 @ r2<- BB 3967 GET_VREG(r1, r3) @ r1<- vCC 3968 GET_VREG(r0, r2) @ r0<- vBB 3969 .if 0 3970 cmp r1, #0 @ is second operand zero? 3971 beq common_errDivideByZero 3972 .endif 3973 3974 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3975 @ optional op; may set condition codes 3976 add r0, r0, r1 @ r0<- op, r0-r3 changed 3977 GET_INST_OPCODE(ip) @ extract opcode from rINST 3978 SET_VREG(r0, r9) @ vAA<- r0 3979 GOTO_OPCODE(ip) @ jump to next instruction 3980 /* 11-14 instructions */ 3981 3982 3983 /* ------------------------------ */ 3984 .balign 64 3985 .L_OP_SUB_INT: /* 0x91 */ 3986 /* File: armv5te/OP_SUB_INT.S */ 3987 /* File: armv5te/binop.S */ 3988 /* 3989 * Generic 32-bit binary operation. Provide an "instr" line that 3990 * specifies an instruction that performs "result = r0 op r1". 3991 * This could be an ARM instruction or a function call. (If the result 3992 * comes back in a register other than r0, you can override "result".) 3993 * 3994 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3995 * vCC (r1). Useful for integer division and modulus. Note that we 3996 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3997 * handles it correctly. 3998 * 3999 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4000 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4001 * mul-float, div-float, rem-float 4002 */ 4003 /* binop vAA, vBB, vCC */ 4004 FETCH(r0, 1) @ r0<- CCBB 4005 mov r9, rINST, lsr #8 @ r9<- AA 4006 mov r3, r0, lsr #8 @ r3<- CC 4007 and r2, r0, #255 @ r2<- BB 4008 GET_VREG(r1, r3) @ r1<- vCC 4009 GET_VREG(r0, r2) @ r0<- vBB 4010 .if 0 4011 cmp r1, #0 @ is second operand zero? 4012 beq common_errDivideByZero 4013 .endif 4014 4015 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4016 @ optional op; may set condition codes 4017 sub r0, r0, r1 @ r0<- op, r0-r3 changed 4018 GET_INST_OPCODE(ip) @ extract opcode from rINST 4019 SET_VREG(r0, r9) @ vAA<- r0 4020 GOTO_OPCODE(ip) @ jump to next instruction 4021 /* 11-14 instructions */ 4022 4023 4024 /* ------------------------------ */ 4025 .balign 64 4026 .L_OP_MUL_INT: /* 0x92 */ 4027 /* File: armv5te/OP_MUL_INT.S */ 4028 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4029 /* File: armv5te/binop.S */ 4030 /* 4031 * Generic 32-bit binary operation. Provide an "instr" line that 4032 * specifies an instruction that performs "result = r0 op r1". 4033 * This could be an ARM instruction or a function call. (If the result 4034 * comes back in a register other than r0, you can override "result".) 4035 * 4036 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4037 * vCC (r1). Useful for integer division and modulus. Note that we 4038 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4039 * handles it correctly. 4040 * 4041 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4042 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4043 * mul-float, div-float, rem-float 4044 */ 4045 /* binop vAA, vBB, vCC */ 4046 FETCH(r0, 1) @ r0<- CCBB 4047 mov r9, rINST, lsr #8 @ r9<- AA 4048 mov r3, r0, lsr #8 @ r3<- CC 4049 and r2, r0, #255 @ r2<- BB 4050 GET_VREG(r1, r3) @ r1<- vCC 4051 GET_VREG(r0, r2) @ r0<- vBB 4052 .if 0 4053 cmp r1, #0 @ is second operand zero? 4054 beq common_errDivideByZero 4055 .endif 4056 4057 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4058 @ optional op; may set condition codes 4059 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4060 GET_INST_OPCODE(ip) @ extract opcode from rINST 4061 SET_VREG(r0, r9) @ vAA<- r0 4062 GOTO_OPCODE(ip) @ jump to next instruction 4063 /* 11-14 instructions */ 4064 4065 4066 /* ------------------------------ */ 4067 .balign 64 4068 .L_OP_DIV_INT: /* 0x93 */ 4069 /* File: armv5te/OP_DIV_INT.S */ 4070 /* File: armv5te/binop.S */ 4071 /* 4072 * Generic 32-bit binary operation. Provide an "instr" line that 4073 * specifies an instruction that performs "result = r0 op r1". 4074 * This could be an ARM instruction or a function call. (If the result 4075 * comes back in a register other than r0, you can override "result".) 4076 * 4077 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4078 * vCC (r1). Useful for integer division and modulus. Note that we 4079 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4080 * handles it correctly. 4081 * 4082 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4083 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4084 * mul-float, div-float, rem-float 4085 */ 4086 /* binop vAA, vBB, vCC */ 4087 FETCH(r0, 1) @ r0<- CCBB 4088 mov r9, rINST, lsr #8 @ r9<- AA 4089 mov r3, r0, lsr #8 @ r3<- CC 4090 and r2, r0, #255 @ r2<- BB 4091 GET_VREG(r1, r3) @ r1<- vCC 4092 GET_VREG(r0, r2) @ r0<- vBB 4093 .if 1 4094 cmp r1, #0 @ is second operand zero? 4095 beq common_errDivideByZero 4096 .endif 4097 4098 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4099 @ optional op; may set condition codes 4100 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4101 GET_INST_OPCODE(ip) @ extract opcode from rINST 4102 SET_VREG(r0, r9) @ vAA<- r0 4103 GOTO_OPCODE(ip) @ jump to next instruction 4104 /* 11-14 instructions */ 4105 4106 4107 /* ------------------------------ */ 4108 .balign 64 4109 .L_OP_REM_INT: /* 0x94 */ 4110 /* File: armv5te/OP_REM_INT.S */ 4111 /* idivmod returns quotient in r0 and remainder in r1 */ 4112 /* File: armv5te/binop.S */ 4113 /* 4114 * Generic 32-bit binary operation. Provide an "instr" line that 4115 * specifies an instruction that performs "result = r0 op r1". 4116 * This could be an ARM instruction or a function call. (If the result 4117 * comes back in a register other than r0, you can override "result".) 4118 * 4119 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4120 * vCC (r1). Useful for integer division and modulus. Note that we 4121 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4122 * handles it correctly. 4123 * 4124 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4125 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4126 * mul-float, div-float, rem-float 4127 */ 4128 /* binop vAA, vBB, vCC */ 4129 FETCH(r0, 1) @ r0<- CCBB 4130 mov r9, rINST, lsr #8 @ r9<- AA 4131 mov r3, r0, lsr #8 @ r3<- CC 4132 and r2, r0, #255 @ r2<- BB 4133 GET_VREG(r1, r3) @ r1<- vCC 4134 GET_VREG(r0, r2) @ r0<- vBB 4135 .if 1 4136 cmp r1, #0 @ is second operand zero? 4137 beq common_errDivideByZero 4138 .endif 4139 4140 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4141 @ optional op; may set condition codes 4142 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4143 GET_INST_OPCODE(ip) @ extract opcode from rINST 4144 SET_VREG(r1, r9) @ vAA<- r1 4145 GOTO_OPCODE(ip) @ jump to next instruction 4146 /* 11-14 instructions */ 4147 4148 4149 /* ------------------------------ */ 4150 .balign 64 4151 .L_OP_AND_INT: /* 0x95 */ 4152 /* File: armv5te/OP_AND_INT.S */ 4153 /* File: armv5te/binop.S */ 4154 /* 4155 * Generic 32-bit binary operation. Provide an "instr" line that 4156 * specifies an instruction that performs "result = r0 op r1". 4157 * This could be an ARM instruction or a function call. (If the result 4158 * comes back in a register other than r0, you can override "result".) 4159 * 4160 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4161 * vCC (r1). Useful for integer division and modulus. Note that we 4162 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4163 * handles it correctly. 4164 * 4165 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4166 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4167 * mul-float, div-float, rem-float 4168 */ 4169 /* binop vAA, vBB, vCC */ 4170 FETCH(r0, 1) @ r0<- CCBB 4171 mov r9, rINST, lsr #8 @ r9<- AA 4172 mov r3, r0, lsr #8 @ r3<- CC 4173 and r2, r0, #255 @ r2<- BB 4174 GET_VREG(r1, r3) @ r1<- vCC 4175 GET_VREG(r0, r2) @ r0<- vBB 4176 .if 0 4177 cmp r1, #0 @ is second operand zero? 4178 beq common_errDivideByZero 4179 .endif 4180 4181 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4182 @ optional op; may set condition codes 4183 and r0, r0, r1 @ r0<- op, r0-r3 changed 4184 GET_INST_OPCODE(ip) @ extract opcode from rINST 4185 SET_VREG(r0, r9) @ vAA<- r0 4186 GOTO_OPCODE(ip) @ jump to next instruction 4187 /* 11-14 instructions */ 4188 4189 4190 /* ------------------------------ */ 4191 .balign 64 4192 .L_OP_OR_INT: /* 0x96 */ 4193 /* File: armv5te/OP_OR_INT.S */ 4194 /* File: armv5te/binop.S */ 4195 /* 4196 * Generic 32-bit binary operation. Provide an "instr" line that 4197 * specifies an instruction that performs "result = r0 op r1". 4198 * This could be an ARM instruction or a function call. (If the result 4199 * comes back in a register other than r0, you can override "result".) 4200 * 4201 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4202 * vCC (r1). Useful for integer division and modulus. Note that we 4203 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4204 * handles it correctly. 4205 * 4206 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4207 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4208 * mul-float, div-float, rem-float 4209 */ 4210 /* binop vAA, vBB, vCC */ 4211 FETCH(r0, 1) @ r0<- CCBB 4212 mov r9, rINST, lsr #8 @ r9<- AA 4213 mov r3, r0, lsr #8 @ r3<- CC 4214 and r2, r0, #255 @ r2<- BB 4215 GET_VREG(r1, r3) @ r1<- vCC 4216 GET_VREG(r0, r2) @ r0<- vBB 4217 .if 0 4218 cmp r1, #0 @ is second operand zero? 4219 beq common_errDivideByZero 4220 .endif 4221 4222 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4223 @ optional op; may set condition codes 4224 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4225 GET_INST_OPCODE(ip) @ extract opcode from rINST 4226 SET_VREG(r0, r9) @ vAA<- r0 4227 GOTO_OPCODE(ip) @ jump to next instruction 4228 /* 11-14 instructions */ 4229 4230 4231 /* ------------------------------ */ 4232 .balign 64 4233 .L_OP_XOR_INT: /* 0x97 */ 4234 /* File: armv5te/OP_XOR_INT.S */ 4235 /* File: armv5te/binop.S */ 4236 /* 4237 * Generic 32-bit binary operation. Provide an "instr" line that 4238 * specifies an instruction that performs "result = r0 op r1". 4239 * This could be an ARM instruction or a function call. (If the result 4240 * comes back in a register other than r0, you can override "result".) 4241 * 4242 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4243 * vCC (r1). Useful for integer division and modulus. Note that we 4244 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4245 * handles it correctly. 4246 * 4247 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4248 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4249 * mul-float, div-float, rem-float 4250 */ 4251 /* binop vAA, vBB, vCC */ 4252 FETCH(r0, 1) @ r0<- CCBB 4253 mov r9, rINST, lsr #8 @ r9<- AA 4254 mov r3, r0, lsr #8 @ r3<- CC 4255 and r2, r0, #255 @ r2<- BB 4256 GET_VREG(r1, r3) @ r1<- vCC 4257 GET_VREG(r0, r2) @ r0<- vBB 4258 .if 0 4259 cmp r1, #0 @ is second operand zero? 4260 beq common_errDivideByZero 4261 .endif 4262 4263 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4264 @ optional op; may set condition codes 4265 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4266 GET_INST_OPCODE(ip) @ extract opcode from rINST 4267 SET_VREG(r0, r9) @ vAA<- r0 4268 GOTO_OPCODE(ip) @ jump to next instruction 4269 /* 11-14 instructions */ 4270 4271 4272 /* ------------------------------ */ 4273 .balign 64 4274 .L_OP_SHL_INT: /* 0x98 */ 4275 /* File: armv5te/OP_SHL_INT.S */ 4276 /* File: armv5te/binop.S */ 4277 /* 4278 * Generic 32-bit binary operation. Provide an "instr" line that 4279 * specifies an instruction that performs "result = r0 op r1". 4280 * This could be an ARM instruction or a function call. (If the result 4281 * comes back in a register other than r0, you can override "result".) 4282 * 4283 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4284 * vCC (r1). Useful for integer division and modulus. Note that we 4285 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4286 * handles it correctly. 4287 * 4288 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4289 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4290 * mul-float, div-float, rem-float 4291 */ 4292 /* binop vAA, vBB, vCC */ 4293 FETCH(r0, 1) @ r0<- CCBB 4294 mov r9, rINST, lsr #8 @ r9<- AA 4295 mov r3, r0, lsr #8 @ r3<- CC 4296 and r2, r0, #255 @ r2<- BB 4297 GET_VREG(r1, r3) @ r1<- vCC 4298 GET_VREG(r0, r2) @ r0<- vBB 4299 .if 0 4300 cmp r1, #0 @ is second operand zero? 4301 beq common_errDivideByZero 4302 .endif 4303 4304 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4305 and r1, r1, #31 @ optional op; may set condition codes 4306 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4307 GET_INST_OPCODE(ip) @ extract opcode from rINST 4308 SET_VREG(r0, r9) @ vAA<- r0 4309 GOTO_OPCODE(ip) @ jump to next instruction 4310 /* 11-14 instructions */ 4311 4312 4313 /* ------------------------------ */ 4314 .balign 64 4315 .L_OP_SHR_INT: /* 0x99 */ 4316 /* File: armv5te/OP_SHR_INT.S */ 4317 /* File: armv5te/binop.S */ 4318 /* 4319 * Generic 32-bit binary operation. Provide an "instr" line that 4320 * specifies an instruction that performs "result = r0 op r1". 4321 * This could be an ARM instruction or a function call. (If the result 4322 * comes back in a register other than r0, you can override "result".) 4323 * 4324 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4325 * vCC (r1). Useful for integer division and modulus. Note that we 4326 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4327 * handles it correctly. 4328 * 4329 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4330 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4331 * mul-float, div-float, rem-float 4332 */ 4333 /* binop vAA, vBB, vCC */ 4334 FETCH(r0, 1) @ r0<- CCBB 4335 mov r9, rINST, lsr #8 @ r9<- AA 4336 mov r3, r0, lsr #8 @ r3<- CC 4337 and r2, r0, #255 @ r2<- BB 4338 GET_VREG(r1, r3) @ r1<- vCC 4339 GET_VREG(r0, r2) @ r0<- vBB 4340 .if 0 4341 cmp r1, #0 @ is second operand zero? 4342 beq common_errDivideByZero 4343 .endif 4344 4345 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4346 and r1, r1, #31 @ optional op; may set condition codes 4347 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4348 GET_INST_OPCODE(ip) @ extract opcode from rINST 4349 SET_VREG(r0, r9) @ vAA<- r0 4350 GOTO_OPCODE(ip) @ jump to next instruction 4351 /* 11-14 instructions */ 4352 4353 4354 /* ------------------------------ */ 4355 .balign 64 4356 .L_OP_USHR_INT: /* 0x9a */ 4357 /* File: armv5te/OP_USHR_INT.S */ 4358 /* File: armv5te/binop.S */ 4359 /* 4360 * Generic 32-bit binary operation. Provide an "instr" line that 4361 * specifies an instruction that performs "result = r0 op r1". 4362 * This could be an ARM instruction or a function call. (If the result 4363 * comes back in a register other than r0, you can override "result".) 4364 * 4365 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4366 * vCC (r1). Useful for integer division and modulus. Note that we 4367 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4368 * handles it correctly. 4369 * 4370 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4371 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4372 * mul-float, div-float, rem-float 4373 */ 4374 /* binop vAA, vBB, vCC */ 4375 FETCH(r0, 1) @ r0<- CCBB 4376 mov r9, rINST, lsr #8 @ r9<- AA 4377 mov r3, r0, lsr #8 @ r3<- CC 4378 and r2, r0, #255 @ r2<- BB 4379 GET_VREG(r1, r3) @ r1<- vCC 4380 GET_VREG(r0, r2) @ r0<- vBB 4381 .if 0 4382 cmp r1, #0 @ is second operand zero? 4383 beq common_errDivideByZero 4384 .endif 4385 4386 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4387 and r1, r1, #31 @ optional op; may set condition codes 4388 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4389 GET_INST_OPCODE(ip) @ extract opcode from rINST 4390 SET_VREG(r0, r9) @ vAA<- r0 4391 GOTO_OPCODE(ip) @ jump to next instruction 4392 /* 11-14 instructions */ 4393 4394 4395 /* ------------------------------ */ 4396 .balign 64 4397 .L_OP_ADD_LONG: /* 0x9b */ 4398 /* File: armv5te/OP_ADD_LONG.S */ 4399 /* File: armv5te/binopWide.S */ 4400 /* 4401 * Generic 64-bit binary operation. Provide an "instr" line that 4402 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4403 * This could be an ARM instruction or a function call. (If the result 4404 * comes back in a register other than r0, you can override "result".) 4405 * 4406 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4407 * vCC (r1). Useful for integer division and modulus. 4408 * 4409 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4410 * xor-long, add-double, sub-double, mul-double, div-double, 4411 * rem-double 4412 * 4413 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4414 */ 4415 /* binop vAA, vBB, vCC */ 4416 FETCH(r0, 1) @ r0<- CCBB 4417 mov r9, rINST, lsr #8 @ r9<- AA 4418 and r2, r0, #255 @ r2<- BB 4419 mov r3, r0, lsr #8 @ r3<- CC 4420 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4421 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4422 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4423 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4424 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4425 .if 0 4426 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4427 beq common_errDivideByZero 4428 .endif 4429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4430 4431 adds r0, r0, r2 @ optional op; may set condition codes 4432 adc r1, r1, r3 @ result<- op, r0-r3 changed 4433 GET_INST_OPCODE(ip) @ extract opcode from rINST 4434 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4435 GOTO_OPCODE(ip) @ jump to next instruction 4436 /* 14-17 instructions */ 4437 4438 4439 /* ------------------------------ */ 4440 .balign 64 4441 .L_OP_SUB_LONG: /* 0x9c */ 4442 /* File: armv5te/OP_SUB_LONG.S */ 4443 /* File: armv5te/binopWide.S */ 4444 /* 4445 * Generic 64-bit binary operation. Provide an "instr" line that 4446 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4447 * This could be an ARM instruction or a function call. (If the result 4448 * comes back in a register other than r0, you can override "result".) 4449 * 4450 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4451 * vCC (r1). Useful for integer division and modulus. 4452 * 4453 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4454 * xor-long, add-double, sub-double, mul-double, div-double, 4455 * rem-double 4456 * 4457 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4458 */ 4459 /* binop vAA, vBB, vCC */ 4460 FETCH(r0, 1) @ r0<- CCBB 4461 mov r9, rINST, lsr #8 @ r9<- AA 4462 and r2, r0, #255 @ r2<- BB 4463 mov r3, r0, lsr #8 @ r3<- CC 4464 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4465 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4466 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4467 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4468 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4469 .if 0 4470 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4471 beq common_errDivideByZero 4472 .endif 4473 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4474 4475 subs r0, r0, r2 @ optional op; may set condition codes 4476 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4477 GET_INST_OPCODE(ip) @ extract opcode from rINST 4478 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4479 GOTO_OPCODE(ip) @ jump to next instruction 4480 /* 14-17 instructions */ 4481 4482 4483 /* ------------------------------ */ 4484 .balign 64 4485 .L_OP_MUL_LONG: /* 0x9d */ 4486 /* File: armv5te/OP_MUL_LONG.S */ 4487 /* 4488 * Signed 64-bit integer multiply. 4489 * 4490 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4491 * WX 4492 * x YZ 4493 * -------- 4494 * ZW ZX 4495 * YW YX 4496 * 4497 * The low word of the result holds ZX, the high word holds 4498 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4499 * it doesn't fit in the low 64 bits. 4500 * 4501 * Unlike most ARM math operations, multiply instructions have 4502 * restrictions on using the same register more than once (Rd and Rm 4503 * cannot be the same). 4504 */ 4505 /* mul-long vAA, vBB, vCC */ 4506 FETCH(r0, 1) @ r0<- CCBB 4507 and r2, r0, #255 @ r2<- BB 4508 mov r3, r0, lsr #8 @ r3<- CC 4509 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4510 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4511 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4512 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4513 mul ip, r2, r1 @ ip<- ZxW 4514 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4515 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4516 mov r0, rINST, lsr #8 @ r0<- AA 4517 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4518 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4519 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4520 b .LOP_MUL_LONG_finish 4521 4522 /* ------------------------------ */ 4523 .balign 64 4524 .L_OP_DIV_LONG: /* 0x9e */ 4525 /* File: armv5te/OP_DIV_LONG.S */ 4526 /* File: armv5te/binopWide.S */ 4527 /* 4528 * Generic 64-bit binary operation. Provide an "instr" line that 4529 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4530 * This could be an ARM instruction or a function call. (If the result 4531 * comes back in a register other than r0, you can override "result".) 4532 * 4533 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4534 * vCC (r1). Useful for integer division and modulus. 4535 * 4536 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4537 * xor-long, add-double, sub-double, mul-double, div-double, 4538 * rem-double 4539 * 4540 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4541 */ 4542 /* binop vAA, vBB, vCC */ 4543 FETCH(r0, 1) @ r0<- CCBB 4544 mov r9, rINST, lsr #8 @ r9<- AA 4545 and r2, r0, #255 @ r2<- BB 4546 mov r3, r0, lsr #8 @ r3<- CC 4547 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4548 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4549 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4550 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4551 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4552 .if 1 4553 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4554 beq common_errDivideByZero 4555 .endif 4556 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4557 4558 @ optional op; may set condition codes 4559 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4560 GET_INST_OPCODE(ip) @ extract opcode from rINST 4561 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4562 GOTO_OPCODE(ip) @ jump to next instruction 4563 /* 14-17 instructions */ 4564 4565 4566 /* ------------------------------ */ 4567 .balign 64 4568 .L_OP_REM_LONG: /* 0x9f */ 4569 /* File: armv5te/OP_REM_LONG.S */ 4570 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4571 /* File: armv5te/binopWide.S */ 4572 /* 4573 * Generic 64-bit binary operation. Provide an "instr" line that 4574 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4575 * This could be an ARM instruction or a function call. (If the result 4576 * comes back in a register other than r0, you can override "result".) 4577 * 4578 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4579 * vCC (r1). Useful for integer division and modulus. 4580 * 4581 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4582 * xor-long, add-double, sub-double, mul-double, div-double, 4583 * rem-double 4584 * 4585 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4586 */ 4587 /* binop vAA, vBB, vCC */ 4588 FETCH(r0, 1) @ r0<- CCBB 4589 mov r9, rINST, lsr #8 @ r9<- AA 4590 and r2, r0, #255 @ r2<- BB 4591 mov r3, r0, lsr #8 @ r3<- CC 4592 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4593 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4594 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4595 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4596 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4597 .if 1 4598 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4599 beq common_errDivideByZero 4600 .endif 4601 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4602 4603 @ optional op; may set condition codes 4604 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4605 GET_INST_OPCODE(ip) @ extract opcode from rINST 4606 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4607 GOTO_OPCODE(ip) @ jump to next instruction 4608 /* 14-17 instructions */ 4609 4610 4611 /* ------------------------------ */ 4612 .balign 64 4613 .L_OP_AND_LONG: /* 0xa0 */ 4614 /* File: armv5te/OP_AND_LONG.S */ 4615 /* File: armv5te/binopWide.S */ 4616 /* 4617 * Generic 64-bit binary operation. Provide an "instr" line that 4618 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4619 * This could be an ARM instruction or a function call. (If the result 4620 * comes back in a register other than r0, you can override "result".) 4621 * 4622 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4623 * vCC (r1). Useful for integer division and modulus. 4624 * 4625 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4626 * xor-long, add-double, sub-double, mul-double, div-double, 4627 * rem-double 4628 * 4629 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4630 */ 4631 /* binop vAA, vBB, vCC */ 4632 FETCH(r0, 1) @ r0<- CCBB 4633 mov r9, rINST, lsr #8 @ r9<- AA 4634 and r2, r0, #255 @ r2<- BB 4635 mov r3, r0, lsr #8 @ r3<- CC 4636 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4637 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4638 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4639 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4640 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4641 .if 0 4642 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4643 beq common_errDivideByZero 4644 .endif 4645 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4646 4647 and r0, r0, r2 @ optional op; may set condition codes 4648 and r1, r1, r3 @ result<- op, r0-r3 changed 4649 GET_INST_OPCODE(ip) @ extract opcode from rINST 4650 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4651 GOTO_OPCODE(ip) @ jump to next instruction 4652 /* 14-17 instructions */ 4653 4654 4655 /* ------------------------------ */ 4656 .balign 64 4657 .L_OP_OR_LONG: /* 0xa1 */ 4658 /* File: armv5te/OP_OR_LONG.S */ 4659 /* File: armv5te/binopWide.S */ 4660 /* 4661 * Generic 64-bit binary operation. Provide an "instr" line that 4662 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4663 * This could be an ARM instruction or a function call. (If the result 4664 * comes back in a register other than r0, you can override "result".) 4665 * 4666 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4667 * vCC (r1). Useful for integer division and modulus. 4668 * 4669 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4670 * xor-long, add-double, sub-double, mul-double, div-double, 4671 * rem-double 4672 * 4673 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4674 */ 4675 /* binop vAA, vBB, vCC */ 4676 FETCH(r0, 1) @ r0<- CCBB 4677 mov r9, rINST, lsr #8 @ r9<- AA 4678 and r2, r0, #255 @ r2<- BB 4679 mov r3, r0, lsr #8 @ r3<- CC 4680 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4681 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4682 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4683 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4684 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4685 .if 0 4686 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4687 beq common_errDivideByZero 4688 .endif 4689 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4690 4691 orr r0, r0, r2 @ optional op; may set condition codes 4692 orr r1, r1, r3 @ result<- op, r0-r3 changed 4693 GET_INST_OPCODE(ip) @ extract opcode from rINST 4694 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4695 GOTO_OPCODE(ip) @ jump to next instruction 4696 /* 14-17 instructions */ 4697 4698 4699 /* ------------------------------ */ 4700 .balign 64 4701 .L_OP_XOR_LONG: /* 0xa2 */ 4702 /* File: armv5te/OP_XOR_LONG.S */ 4703 /* File: armv5te/binopWide.S */ 4704 /* 4705 * Generic 64-bit binary operation. Provide an "instr" line that 4706 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4707 * This could be an ARM instruction or a function call. (If the result 4708 * comes back in a register other than r0, you can override "result".) 4709 * 4710 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4711 * vCC (r1). Useful for integer division and modulus. 4712 * 4713 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4714 * xor-long, add-double, sub-double, mul-double, div-double, 4715 * rem-double 4716 * 4717 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4718 */ 4719 /* binop vAA, vBB, vCC */ 4720 FETCH(r0, 1) @ r0<- CCBB 4721 mov r9, rINST, lsr #8 @ r9<- AA 4722 and r2, r0, #255 @ r2<- BB 4723 mov r3, r0, lsr #8 @ r3<- CC 4724 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4725 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4726 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4727 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4728 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4729 .if 0 4730 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4731 beq common_errDivideByZero 4732 .endif 4733 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4734 4735 eor r0, r0, r2 @ optional op; may set condition codes 4736 eor r1, r1, r3 @ result<- op, r0-r3 changed 4737 GET_INST_OPCODE(ip) @ extract opcode from rINST 4738 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4739 GOTO_OPCODE(ip) @ jump to next instruction 4740 /* 14-17 instructions */ 4741 4742 4743 /* ------------------------------ */ 4744 .balign 64 4745 .L_OP_SHL_LONG: /* 0xa3 */ 4746 /* File: armv5te/OP_SHL_LONG.S */ 4747 /* 4748 * Long integer shift. This is different from the generic 32/64-bit 4749 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4750 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4751 * 6 bits of the shift distance. 4752 */ 4753 /* shl-long vAA, vBB, vCC */ 4754 FETCH(r0, 1) @ r0<- CCBB 4755 mov r9, rINST, lsr #8 @ r9<- AA 4756 and r3, r0, #255 @ r3<- BB 4757 mov r0, r0, lsr #8 @ r0<- CC 4758 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4759 GET_VREG(r2, r0) @ r2<- vCC 4760 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4761 and r2, r2, #63 @ r2<- r2 & 0x3f 4762 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4763 4764 mov r1, r1, asl r2 @ r1<- r1 << r2 4765 rsb r3, r2, #32 @ r3<- 32 - r2 4766 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4767 subs ip, r2, #32 @ ip<- r2 - 32 4768 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4769 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4770 b .LOP_SHL_LONG_finish 4771 4772 /* ------------------------------ */ 4773 .balign 64 4774 .L_OP_SHR_LONG: /* 0xa4 */ 4775 /* File: armv5te/OP_SHR_LONG.S */ 4776 /* 4777 * Long integer shift. This is different from the generic 32/64-bit 4778 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4779 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4780 * 6 bits of the shift distance. 4781 */ 4782 /* shr-long vAA, vBB, vCC */ 4783 FETCH(r0, 1) @ r0<- CCBB 4784 mov r9, rINST, lsr #8 @ r9<- AA 4785 and r3, r0, #255 @ r3<- BB 4786 mov r0, r0, lsr #8 @ r0<- CC 4787 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4788 GET_VREG(r2, r0) @ r2<- vCC 4789 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4790 and r2, r2, #63 @ r0<- r0 & 0x3f 4791 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4792 4793 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4794 rsb r3, r2, #32 @ r3<- 32 - r2 4795 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4796 subs ip, r2, #32 @ ip<- r2 - 32 4797 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4799 b .LOP_SHR_LONG_finish 4800 4801 /* ------------------------------ */ 4802 .balign 64 4803 .L_OP_USHR_LONG: /* 0xa5 */ 4804 /* File: armv5te/OP_USHR_LONG.S */ 4805 /* 4806 * Long integer shift. This is different from the generic 32/64-bit 4807 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4808 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4809 * 6 bits of the shift distance. 4810 */ 4811 /* ushr-long vAA, vBB, vCC */ 4812 FETCH(r0, 1) @ r0<- CCBB 4813 mov r9, rINST, lsr #8 @ r9<- AA 4814 and r3, r0, #255 @ r3<- BB 4815 mov r0, r0, lsr #8 @ r0<- CC 4816 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4817 GET_VREG(r2, r0) @ r2<- vCC 4818 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4819 and r2, r2, #63 @ r0<- r0 & 0x3f 4820 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4821 4822 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4823 rsb r3, r2, #32 @ r3<- 32 - r2 4824 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4825 subs ip, r2, #32 @ ip<- r2 - 32 4826 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4827 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4828 b .LOP_USHR_LONG_finish 4829 4830 /* ------------------------------ */ 4831 .balign 64 4832 .L_OP_ADD_FLOAT: /* 0xa6 */ 4833 /* File: arm-vfp/OP_ADD_FLOAT.S */ 4834 /* File: arm-vfp/fbinop.S */ 4835 /* 4836 * Generic 32-bit floating-point operation. Provide an "instr" line that 4837 * specifies an instruction that performs "s2 = s0 op s1". Because we 4838 * use the "softfp" ABI, this must be an instruction, not a function call. 4839 * 4840 * For: add-float, sub-float, mul-float, div-float 4841 */ 4842 /* floatop vAA, vBB, vCC */ 4843 FETCH(r0, 1) @ r0<- CCBB 4844 mov r9, rINST, lsr #8 @ r9<- AA 4845 mov r3, r0, lsr #8 @ r3<- CC 4846 and r2, r0, #255 @ r2<- BB 4847 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4848 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4849 flds s1, [r3] @ s1<- vCC 4850 flds s0, [r2] @ s0<- vBB 4851 4852 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4853 fadds s2, s0, s1 @ s2<- op 4854 GET_INST_OPCODE(ip) @ extract opcode from rINST 4855 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4856 fsts s2, [r9] @ vAA<- s2 4857 GOTO_OPCODE(ip) @ jump to next instruction 4858 4859 4860 /* ------------------------------ */ 4861 .balign 64 4862 .L_OP_SUB_FLOAT: /* 0xa7 */ 4863 /* File: arm-vfp/OP_SUB_FLOAT.S */ 4864 /* File: arm-vfp/fbinop.S */ 4865 /* 4866 * Generic 32-bit floating-point operation. Provide an "instr" line that 4867 * specifies an instruction that performs "s2 = s0 op s1". Because we 4868 * use the "softfp" ABI, this must be an instruction, not a function call. 4869 * 4870 * For: add-float, sub-float, mul-float, div-float 4871 */ 4872 /* floatop vAA, vBB, vCC */ 4873 FETCH(r0, 1) @ r0<- CCBB 4874 mov r9, rINST, lsr #8 @ r9<- AA 4875 mov r3, r0, lsr #8 @ r3<- CC 4876 and r2, r0, #255 @ r2<- BB 4877 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4878 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4879 flds s1, [r3] @ s1<- vCC 4880 flds s0, [r2] @ s0<- vBB 4881 4882 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4883 fsubs s2, s0, s1 @ s2<- op 4884 GET_INST_OPCODE(ip) @ extract opcode from rINST 4885 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4886 fsts s2, [r9] @ vAA<- s2 4887 GOTO_OPCODE(ip) @ jump to next instruction 4888 4889 4890 /* ------------------------------ */ 4891 .balign 64 4892 .L_OP_MUL_FLOAT: /* 0xa8 */ 4893 /* File: arm-vfp/OP_MUL_FLOAT.S */ 4894 /* File: arm-vfp/fbinop.S */ 4895 /* 4896 * Generic 32-bit floating-point operation. Provide an "instr" line that 4897 * specifies an instruction that performs "s2 = s0 op s1". Because we 4898 * use the "softfp" ABI, this must be an instruction, not a function call. 4899 * 4900 * For: add-float, sub-float, mul-float, div-float 4901 */ 4902 /* floatop vAA, vBB, vCC */ 4903 FETCH(r0, 1) @ r0<- CCBB 4904 mov r9, rINST, lsr #8 @ r9<- AA 4905 mov r3, r0, lsr #8 @ r3<- CC 4906 and r2, r0, #255 @ r2<- BB 4907 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4908 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4909 flds s1, [r3] @ s1<- vCC 4910 flds s0, [r2] @ s0<- vBB 4911 4912 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4913 fmuls s2, s0, s1 @ s2<- op 4914 GET_INST_OPCODE(ip) @ extract opcode from rINST 4915 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4916 fsts s2, [r9] @ vAA<- s2 4917 GOTO_OPCODE(ip) @ jump to next instruction 4918 4919 4920 /* ------------------------------ */ 4921 .balign 64 4922 .L_OP_DIV_FLOAT: /* 0xa9 */ 4923 /* File: arm-vfp/OP_DIV_FLOAT.S */ 4924 /* File: arm-vfp/fbinop.S */ 4925 /* 4926 * Generic 32-bit floating-point operation. Provide an "instr" line that 4927 * specifies an instruction that performs "s2 = s0 op s1". Because we 4928 * use the "softfp" ABI, this must be an instruction, not a function call. 4929 * 4930 * For: add-float, sub-float, mul-float, div-float 4931 */ 4932 /* floatop vAA, vBB, vCC */ 4933 FETCH(r0, 1) @ r0<- CCBB 4934 mov r9, rINST, lsr #8 @ r9<- AA 4935 mov r3, r0, lsr #8 @ r3<- CC 4936 and r2, r0, #255 @ r2<- BB 4937 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4938 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4939 flds s1, [r3] @ s1<- vCC 4940 flds s0, [r2] @ s0<- vBB 4941 4942 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4943 fdivs s2, s0, s1 @ s2<- op 4944 GET_INST_OPCODE(ip) @ extract opcode from rINST 4945 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4946 fsts s2, [r9] @ vAA<- s2 4947 GOTO_OPCODE(ip) @ jump to next instruction 4948 4949 4950 /* ------------------------------ */ 4951 .balign 64 4952 .L_OP_REM_FLOAT: /* 0xaa */ 4953 /* File: armv5te/OP_REM_FLOAT.S */ 4954 /* EABI doesn't define a float remainder function, but libm does */ 4955 /* File: armv5te/binop.S */ 4956 /* 4957 * Generic 32-bit binary operation. Provide an "instr" line that 4958 * specifies an instruction that performs "result = r0 op r1". 4959 * This could be an ARM instruction or a function call. (If the result 4960 * comes back in a register other than r0, you can override "result".) 4961 * 4962 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4963 * vCC (r1). Useful for integer division and modulus. Note that we 4964 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4965 * handles it correctly. 4966 * 4967 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4968 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4969 * mul-float, div-float, rem-float 4970 */ 4971 /* binop vAA, vBB, vCC */ 4972 FETCH(r0, 1) @ r0<- CCBB 4973 mov r9, rINST, lsr #8 @ r9<- AA 4974 mov r3, r0, lsr #8 @ r3<- CC 4975 and r2, r0, #255 @ r2<- BB 4976 GET_VREG(r1, r3) @ r1<- vCC 4977 GET_VREG(r0, r2) @ r0<- vBB 4978 .if 0 4979 cmp r1, #0 @ is second operand zero? 4980 beq common_errDivideByZero 4981 .endif 4982 4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4984 @ optional op; may set condition codes 4985 bl fmodf @ r0<- op, r0-r3 changed 4986 GET_INST_OPCODE(ip) @ extract opcode from rINST 4987 SET_VREG(r0, r9) @ vAA<- r0 4988 GOTO_OPCODE(ip) @ jump to next instruction 4989 /* 11-14 instructions */ 4990 4991 4992 /* ------------------------------ */ 4993 .balign 64 4994 .L_OP_ADD_DOUBLE: /* 0xab */ 4995 /* File: arm-vfp/OP_ADD_DOUBLE.S */ 4996 /* File: arm-vfp/fbinopWide.S */ 4997 /* 4998 * Generic 64-bit double-precision floating point binary operation. 4999 * Provide an "instr" line that specifies an instruction that performs 5000 * "d2 = d0 op d1". 5001 * 5002 * for: add-double, sub-double, mul-double, div-double 5003 */ 5004 /* doubleop vAA, vBB, vCC */ 5005 FETCH(r0, 1) @ r0<- CCBB 5006 mov r9, rINST, lsr #8 @ r9<- AA 5007 mov r3, r0, lsr #8 @ r3<- CC 5008 and r2, r0, #255 @ r2<- BB 5009 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5010 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5011 fldd d1, [r3] @ d1<- vCC 5012 fldd d0, [r2] @ d0<- vBB 5013 5014 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5015 faddd d2, d0, d1 @ s2<- op 5016 GET_INST_OPCODE(ip) @ extract opcode from rINST 5017 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5018 fstd d2, [r9] @ vAA<- d2 5019 GOTO_OPCODE(ip) @ jump to next instruction 5020 5021 5022 /* ------------------------------ */ 5023 .balign 64 5024 .L_OP_SUB_DOUBLE: /* 0xac */ 5025 /* File: arm-vfp/OP_SUB_DOUBLE.S */ 5026 /* File: arm-vfp/fbinopWide.S */ 5027 /* 5028 * Generic 64-bit double-precision floating point binary operation. 5029 * Provide an "instr" line that specifies an instruction that performs 5030 * "d2 = d0 op d1". 5031 * 5032 * for: add-double, sub-double, mul-double, div-double 5033 */ 5034 /* doubleop vAA, vBB, vCC */ 5035 FETCH(r0, 1) @ r0<- CCBB 5036 mov r9, rINST, lsr #8 @ r9<- AA 5037 mov r3, r0, lsr #8 @ r3<- CC 5038 and r2, r0, #255 @ r2<- BB 5039 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5040 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5041 fldd d1, [r3] @ d1<- vCC 5042 fldd d0, [r2] @ d0<- vBB 5043 5044 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5045 fsubd d2, d0, d1 @ s2<- op 5046 GET_INST_OPCODE(ip) @ extract opcode from rINST 5047 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5048 fstd d2, [r9] @ vAA<- d2 5049 GOTO_OPCODE(ip) @ jump to next instruction 5050 5051 5052 /* ------------------------------ */ 5053 .balign 64 5054 .L_OP_MUL_DOUBLE: /* 0xad */ 5055 /* File: arm-vfp/OP_MUL_DOUBLE.S */ 5056 /* File: arm-vfp/fbinopWide.S */ 5057 /* 5058 * Generic 64-bit double-precision floating point binary operation. 5059 * Provide an "instr" line that specifies an instruction that performs 5060 * "d2 = d0 op d1". 5061 * 5062 * for: add-double, sub-double, mul-double, div-double 5063 */ 5064 /* doubleop vAA, vBB, vCC */ 5065 FETCH(r0, 1) @ r0<- CCBB 5066 mov r9, rINST, lsr #8 @ r9<- AA 5067 mov r3, r0, lsr #8 @ r3<- CC 5068 and r2, r0, #255 @ r2<- BB 5069 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5070 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5071 fldd d1, [r3] @ d1<- vCC 5072 fldd d0, [r2] @ d0<- vBB 5073 5074 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5075 fmuld d2, d0, d1 @ s2<- op 5076 GET_INST_OPCODE(ip) @ extract opcode from rINST 5077 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5078 fstd d2, [r9] @ vAA<- d2 5079 GOTO_OPCODE(ip) @ jump to next instruction 5080 5081 5082 /* ------------------------------ */ 5083 .balign 64 5084 .L_OP_DIV_DOUBLE: /* 0xae */ 5085 /* File: arm-vfp/OP_DIV_DOUBLE.S */ 5086 /* File: arm-vfp/fbinopWide.S */ 5087 /* 5088 * Generic 64-bit double-precision floating point binary operation. 5089 * Provide an "instr" line that specifies an instruction that performs 5090 * "d2 = d0 op d1". 5091 * 5092 * for: add-double, sub-double, mul-double, div-double 5093 */ 5094 /* doubleop vAA, vBB, vCC */ 5095 FETCH(r0, 1) @ r0<- CCBB 5096 mov r9, rINST, lsr #8 @ r9<- AA 5097 mov r3, r0, lsr #8 @ r3<- CC 5098 and r2, r0, #255 @ r2<- BB 5099 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5100 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5101 fldd d1, [r3] @ d1<- vCC 5102 fldd d0, [r2] @ d0<- vBB 5103 5104 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5105 fdivd d2, d0, d1 @ s2<- op 5106 GET_INST_OPCODE(ip) @ extract opcode from rINST 5107 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5108 fstd d2, [r9] @ vAA<- d2 5109 GOTO_OPCODE(ip) @ jump to next instruction 5110 5111 5112 /* ------------------------------ */ 5113 .balign 64 5114 .L_OP_REM_DOUBLE: /* 0xaf */ 5115 /* File: armv5te/OP_REM_DOUBLE.S */ 5116 /* EABI doesn't define a double remainder function, but libm does */ 5117 /* File: armv5te/binopWide.S */ 5118 /* 5119 * Generic 64-bit binary operation. Provide an "instr" line that 5120 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5121 * This could be an ARM instruction or a function call. (If the result 5122 * comes back in a register other than r0, you can override "result".) 5123 * 5124 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5125 * vCC (r1). Useful for integer division and modulus. 5126 * 5127 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5128 * xor-long, add-double, sub-double, mul-double, div-double, 5129 * rem-double 5130 * 5131 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5132 */ 5133 /* binop vAA, vBB, vCC */ 5134 FETCH(r0, 1) @ r0<- CCBB 5135 mov r9, rINST, lsr #8 @ r9<- AA 5136 and r2, r0, #255 @ r2<- BB 5137 mov r3, r0, lsr #8 @ r3<- CC 5138 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5139 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5140 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5141 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5142 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5143 .if 0 5144 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5145 beq common_errDivideByZero 5146 .endif 5147 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5148 5149 @ optional op; may set condition codes 5150 bl fmod @ result<- op, r0-r3 changed 5151 GET_INST_OPCODE(ip) @ extract opcode from rINST 5152 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5153 GOTO_OPCODE(ip) @ jump to next instruction 5154 /* 14-17 instructions */ 5155 5156 5157 /* ------------------------------ */ 5158 .balign 64 5159 .L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5160 /* File: armv5te/OP_ADD_INT_2ADDR.S */ 5161 /* File: armv5te/binop2addr.S */ 5162 /* 5163 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5164 * that specifies an instruction that performs "result = r0 op r1". 5165 * This could be an ARM instruction or a function call. (If the result 5166 * comes back in a register other than r0, you can override "result".) 5167 * 5168 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5169 * vCC (r1). Useful for integer division and modulus. 5170 * 5171 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5172 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5173 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5174 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5175 */ 5176 /* binop/2addr vA, vB */ 5177 mov r9, rINST, lsr #8 @ r9<- A+ 5178 mov r3, rINST, lsr #12 @ r3<- B 5179 and r9, r9, #15 5180 GET_VREG(r1, r3) @ r1<- vB 5181 GET_VREG(r0, r9) @ r0<- vA 5182 .if 0 5183 cmp r1, #0 @ is second operand zero? 5184 beq common_errDivideByZero 5185 .endif 5186 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5187 5188 @ optional op; may set condition codes 5189 add r0, r0, r1 @ r0<- op, r0-r3 changed 5190 GET_INST_OPCODE(ip) @ extract opcode from rINST 5191 SET_VREG(r0, r9) @ vAA<- r0 5192 GOTO_OPCODE(ip) @ jump to next instruction 5193 /* 10-13 instructions */ 5194 5195 5196 /* ------------------------------ */ 5197 .balign 64 5198 .L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5199 /* File: armv5te/OP_SUB_INT_2ADDR.S */ 5200 /* File: armv5te/binop2addr.S */ 5201 /* 5202 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5203 * that specifies an instruction that performs "result = r0 op r1". 5204 * This could be an ARM instruction or a function call. (If the result 5205 * comes back in a register other than r0, you can override "result".) 5206 * 5207 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5208 * vCC (r1). Useful for integer division and modulus. 5209 * 5210 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5211 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5212 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5213 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5214 */ 5215 /* binop/2addr vA, vB */ 5216 mov r9, rINST, lsr #8 @ r9<- A+ 5217 mov r3, rINST, lsr #12 @ r3<- B 5218 and r9, r9, #15 5219 GET_VREG(r1, r3) @ r1<- vB 5220 GET_VREG(r0, r9) @ r0<- vA 5221 .if 0 5222 cmp r1, #0 @ is second operand zero? 5223 beq common_errDivideByZero 5224 .endif 5225 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5226 5227 @ optional op; may set condition codes 5228 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5229 GET_INST_OPCODE(ip) @ extract opcode from rINST 5230 SET_VREG(r0, r9) @ vAA<- r0 5231 GOTO_OPCODE(ip) @ jump to next instruction 5232 /* 10-13 instructions */ 5233 5234 5235 /* ------------------------------ */ 5236 .balign 64 5237 .L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5238 /* File: armv5te/OP_MUL_INT_2ADDR.S */ 5239 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5240 /* File: armv5te/binop2addr.S */ 5241 /* 5242 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5243 * that specifies an instruction that performs "result = r0 op r1". 5244 * This could be an ARM instruction or a function call. (If the result 5245 * comes back in a register other than r0, you can override "result".) 5246 * 5247 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5248 * vCC (r1). Useful for integer division and modulus. 5249 * 5250 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5251 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5252 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5253 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5254 */ 5255 /* binop/2addr vA, vB */ 5256 mov r9, rINST, lsr #8 @ r9<- A+ 5257 mov r3, rINST, lsr #12 @ r3<- B 5258 and r9, r9, #15 5259 GET_VREG(r1, r3) @ r1<- vB 5260 GET_VREG(r0, r9) @ r0<- vA 5261 .if 0 5262 cmp r1, #0 @ is second operand zero? 5263 beq common_errDivideByZero 5264 .endif 5265 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5266 5267 @ optional op; may set condition codes 5268 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5269 GET_INST_OPCODE(ip) @ extract opcode from rINST 5270 SET_VREG(r0, r9) @ vAA<- r0 5271 GOTO_OPCODE(ip) @ jump to next instruction 5272 /* 10-13 instructions */ 5273 5274 5275 /* ------------------------------ */ 5276 .balign 64 5277 .L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5278 /* File: armv5te/OP_DIV_INT_2ADDR.S */ 5279 /* File: armv5te/binop2addr.S */ 5280 /* 5281 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5282 * that specifies an instruction that performs "result = r0 op r1". 5283 * This could be an ARM instruction or a function call. (If the result 5284 * comes back in a register other than r0, you can override "result".) 5285 * 5286 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5287 * vCC (r1). Useful for integer division and modulus. 5288 * 5289 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5290 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5291 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5292 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5293 */ 5294 /* binop/2addr vA, vB */ 5295 mov r9, rINST, lsr #8 @ r9<- A+ 5296 mov r3, rINST, lsr #12 @ r3<- B 5297 and r9, r9, #15 5298 GET_VREG(r1, r3) @ r1<- vB 5299 GET_VREG(r0, r9) @ r0<- vA 5300 .if 1 5301 cmp r1, #0 @ is second operand zero? 5302 beq common_errDivideByZero 5303 .endif 5304 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5305 5306 @ optional op; may set condition codes 5307 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5308 GET_INST_OPCODE(ip) @ extract opcode from rINST 5309 SET_VREG(r0, r9) @ vAA<- r0 5310 GOTO_OPCODE(ip) @ jump to next instruction 5311 /* 10-13 instructions */ 5312 5313 5314 /* ------------------------------ */ 5315 .balign 64 5316 .L_OP_REM_INT_2ADDR: /* 0xb4 */ 5317 /* File: armv5te/OP_REM_INT_2ADDR.S */ 5318 /* idivmod returns quotient in r0 and remainder in r1 */ 5319 /* File: armv5te/binop2addr.S */ 5320 /* 5321 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5322 * that specifies an instruction that performs "result = r0 op r1". 5323 * This could be an ARM instruction or a function call. (If the result 5324 * comes back in a register other than r0, you can override "result".) 5325 * 5326 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5327 * vCC (r1). Useful for integer division and modulus. 5328 * 5329 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5330 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5331 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5332 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5333 */ 5334 /* binop/2addr vA, vB */ 5335 mov r9, rINST, lsr #8 @ r9<- A+ 5336 mov r3, rINST, lsr #12 @ r3<- B 5337 and r9, r9, #15 5338 GET_VREG(r1, r3) @ r1<- vB 5339 GET_VREG(r0, r9) @ r0<- vA 5340 .if 1 5341 cmp r1, #0 @ is second operand zero? 5342 beq common_errDivideByZero 5343 .endif 5344 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5345 5346 @ optional op; may set condition codes 5347 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5348 GET_INST_OPCODE(ip) @ extract opcode from rINST 5349 SET_VREG(r1, r9) @ vAA<- r1 5350 GOTO_OPCODE(ip) @ jump to next instruction 5351 /* 10-13 instructions */ 5352 5353 5354 /* ------------------------------ */ 5355 .balign 64 5356 .L_OP_AND_INT_2ADDR: /* 0xb5 */ 5357 /* File: armv5te/OP_AND_INT_2ADDR.S */ 5358 /* File: armv5te/binop2addr.S */ 5359 /* 5360 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5361 * that specifies an instruction that performs "result = r0 op r1". 5362 * This could be an ARM instruction or a function call. (If the result 5363 * comes back in a register other than r0, you can override "result".) 5364 * 5365 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5366 * vCC (r1). Useful for integer division and modulus. 5367 * 5368 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5369 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5370 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5371 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5372 */ 5373 /* binop/2addr vA, vB */ 5374 mov r9, rINST, lsr #8 @ r9<- A+ 5375 mov r3, rINST, lsr #12 @ r3<- B 5376 and r9, r9, #15 5377 GET_VREG(r1, r3) @ r1<- vB 5378 GET_VREG(r0, r9) @ r0<- vA 5379 .if 0 5380 cmp r1, #0 @ is second operand zero? 5381 beq common_errDivideByZero 5382 .endif 5383 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5384 5385 @ optional op; may set condition codes 5386 and r0, r0, r1 @ r0<- op, r0-r3 changed 5387 GET_INST_OPCODE(ip) @ extract opcode from rINST 5388 SET_VREG(r0, r9) @ vAA<- r0 5389 GOTO_OPCODE(ip) @ jump to next instruction 5390 /* 10-13 instructions */ 5391 5392 5393 /* ------------------------------ */ 5394 .balign 64 5395 .L_OP_OR_INT_2ADDR: /* 0xb6 */ 5396 /* File: armv5te/OP_OR_INT_2ADDR.S */ 5397 /* File: armv5te/binop2addr.S */ 5398 /* 5399 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5400 * that specifies an instruction that performs "result = r0 op r1". 5401 * This could be an ARM instruction or a function call. (If the result 5402 * comes back in a register other than r0, you can override "result".) 5403 * 5404 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5405 * vCC (r1). Useful for integer division and modulus. 5406 * 5407 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5408 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5409 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5410 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5411 */ 5412 /* binop/2addr vA, vB */ 5413 mov r9, rINST, lsr #8 @ r9<- A+ 5414 mov r3, rINST, lsr #12 @ r3<- B 5415 and r9, r9, #15 5416 GET_VREG(r1, r3) @ r1<- vB 5417 GET_VREG(r0, r9) @ r0<- vA 5418 .if 0 5419 cmp r1, #0 @ is second operand zero? 5420 beq common_errDivideByZero 5421 .endif 5422 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5423 5424 @ optional op; may set condition codes 5425 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5426 GET_INST_OPCODE(ip) @ extract opcode from rINST 5427 SET_VREG(r0, r9) @ vAA<- r0 5428 GOTO_OPCODE(ip) @ jump to next instruction 5429 /* 10-13 instructions */ 5430 5431 5432 /* ------------------------------ */ 5433 .balign 64 5434 .L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5435 /* File: armv5te/OP_XOR_INT_2ADDR.S */ 5436 /* File: armv5te/binop2addr.S */ 5437 /* 5438 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5439 * that specifies an instruction that performs "result = r0 op r1". 5440 * This could be an ARM instruction or a function call. (If the result 5441 * comes back in a register other than r0, you can override "result".) 5442 * 5443 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5444 * vCC (r1). Useful for integer division and modulus. 5445 * 5446 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5447 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5448 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5449 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5450 */ 5451 /* binop/2addr vA, vB */ 5452 mov r9, rINST, lsr #8 @ r9<- A+ 5453 mov r3, rINST, lsr #12 @ r3<- B 5454 and r9, r9, #15 5455 GET_VREG(r1, r3) @ r1<- vB 5456 GET_VREG(r0, r9) @ r0<- vA 5457 .if 0 5458 cmp r1, #0 @ is second operand zero? 5459 beq common_errDivideByZero 5460 .endif 5461 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5462 5463 @ optional op; may set condition codes 5464 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5465 GET_INST_OPCODE(ip) @ extract opcode from rINST 5466 SET_VREG(r0, r9) @ vAA<- r0 5467 GOTO_OPCODE(ip) @ jump to next instruction 5468 /* 10-13 instructions */ 5469 5470 5471 /* ------------------------------ */ 5472 .balign 64 5473 .L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5474 /* File: armv5te/OP_SHL_INT_2ADDR.S */ 5475 /* File: armv5te/binop2addr.S */ 5476 /* 5477 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5478 * that specifies an instruction that performs "result = r0 op r1". 5479 * This could be an ARM instruction or a function call. (If the result 5480 * comes back in a register other than r0, you can override "result".) 5481 * 5482 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5483 * vCC (r1). Useful for integer division and modulus. 5484 * 5485 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5486 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5487 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5488 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5489 */ 5490 /* binop/2addr vA, vB */ 5491 mov r9, rINST, lsr #8 @ r9<- A+ 5492 mov r3, rINST, lsr #12 @ r3<- B 5493 and r9, r9, #15 5494 GET_VREG(r1, r3) @ r1<- vB 5495 GET_VREG(r0, r9) @ r0<- vA 5496 .if 0 5497 cmp r1, #0 @ is second operand zero? 5498 beq common_errDivideByZero 5499 .endif 5500 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5501 5502 and r1, r1, #31 @ optional op; may set condition codes 5503 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5504 GET_INST_OPCODE(ip) @ extract opcode from rINST 5505 SET_VREG(r0, r9) @ vAA<- r0 5506 GOTO_OPCODE(ip) @ jump to next instruction 5507 /* 10-13 instructions */ 5508 5509 5510 /* ------------------------------ */ 5511 .balign 64 5512 .L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5513 /* File: armv5te/OP_SHR_INT_2ADDR.S */ 5514 /* File: armv5te/binop2addr.S */ 5515 /* 5516 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5517 * that specifies an instruction that performs "result = r0 op r1". 5518 * This could be an ARM instruction or a function call. (If the result 5519 * comes back in a register other than r0, you can override "result".) 5520 * 5521 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5522 * vCC (r1). Useful for integer division and modulus. 5523 * 5524 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5525 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5526 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5527 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5528 */ 5529 /* binop/2addr vA, vB */ 5530 mov r9, rINST, lsr #8 @ r9<- A+ 5531 mov r3, rINST, lsr #12 @ r3<- B 5532 and r9, r9, #15 5533 GET_VREG(r1, r3) @ r1<- vB 5534 GET_VREG(r0, r9) @ r0<- vA 5535 .if 0 5536 cmp r1, #0 @ is second operand zero? 5537 beq common_errDivideByZero 5538 .endif 5539 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5540 5541 and r1, r1, #31 @ optional op; may set condition codes 5542 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5543 GET_INST_OPCODE(ip) @ extract opcode from rINST 5544 SET_VREG(r0, r9) @ vAA<- r0 5545 GOTO_OPCODE(ip) @ jump to next instruction 5546 /* 10-13 instructions */ 5547 5548 5549 /* ------------------------------ */ 5550 .balign 64 5551 .L_OP_USHR_INT_2ADDR: /* 0xba */ 5552 /* File: armv5te/OP_USHR_INT_2ADDR.S */ 5553 /* File: armv5te/binop2addr.S */ 5554 /* 5555 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5556 * that specifies an instruction that performs "result = r0 op r1". 5557 * This could be an ARM instruction or a function call. (If the result 5558 * comes back in a register other than r0, you can override "result".) 5559 * 5560 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5561 * vCC (r1). Useful for integer division and modulus. 5562 * 5563 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5564 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5565 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5566 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5567 */ 5568 /* binop/2addr vA, vB */ 5569 mov r9, rINST, lsr #8 @ r9<- A+ 5570 mov r3, rINST, lsr #12 @ r3<- B 5571 and r9, r9, #15 5572 GET_VREG(r1, r3) @ r1<- vB 5573 GET_VREG(r0, r9) @ r0<- vA 5574 .if 0 5575 cmp r1, #0 @ is second operand zero? 5576 beq common_errDivideByZero 5577 .endif 5578 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5579 5580 and r1, r1, #31 @ optional op; may set condition codes 5581 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5582 GET_INST_OPCODE(ip) @ extract opcode from rINST 5583 SET_VREG(r0, r9) @ vAA<- r0 5584 GOTO_OPCODE(ip) @ jump to next instruction 5585 /* 10-13 instructions */ 5586 5587 5588 /* ------------------------------ */ 5589 .balign 64 5590 .L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5591 /* File: armv5te/OP_ADD_LONG_2ADDR.S */ 5592 /* File: armv5te/binopWide2addr.S */ 5593 /* 5594 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5595 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5596 * This could be an ARM instruction or a function call. (If the result 5597 * comes back in a register other than r0, you can override "result".) 5598 * 5599 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5600 * vCC (r1). Useful for integer division and modulus. 5601 * 5602 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5603 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5604 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5605 * rem-double/2addr 5606 */ 5607 /* binop/2addr vA, vB */ 5608 mov r9, rINST, lsr #8 @ r9<- A+ 5609 mov r1, rINST, lsr #12 @ r1<- B 5610 and r9, r9, #15 5611 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5612 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5613 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5614 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5615 .if 0 5616 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5617 beq common_errDivideByZero 5618 .endif 5619 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5620 5621 adds r0, r0, r2 @ optional op; may set condition codes 5622 adc r1, r1, r3 @ result<- op, r0-r3 changed 5623 GET_INST_OPCODE(ip) @ extract opcode from rINST 5624 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5625 GOTO_OPCODE(ip) @ jump to next instruction 5626 /* 12-15 instructions */ 5627 5628 5629 /* ------------------------------ */ 5630 .balign 64 5631 .L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5632 /* File: armv5te/OP_SUB_LONG_2ADDR.S */ 5633 /* File: armv5te/binopWide2addr.S */ 5634 /* 5635 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5636 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5637 * This could be an ARM instruction or a function call. (If the result 5638 * comes back in a register other than r0, you can override "result".) 5639 * 5640 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5641 * vCC (r1). Useful for integer division and modulus. 5642 * 5643 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5644 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5645 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5646 * rem-double/2addr 5647 */ 5648 /* binop/2addr vA, vB */ 5649 mov r9, rINST, lsr #8 @ r9<- A+ 5650 mov r1, rINST, lsr #12 @ r1<- B 5651 and r9, r9, #15 5652 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5653 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5654 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5655 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5656 .if 0 5657 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5658 beq common_errDivideByZero 5659 .endif 5660 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5661 5662 subs r0, r0, r2 @ optional op; may set condition codes 5663 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5664 GET_INST_OPCODE(ip) @ extract opcode from rINST 5665 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5666 GOTO_OPCODE(ip) @ jump to next instruction 5667 /* 12-15 instructions */ 5668 5669 5670 /* ------------------------------ */ 5671 .balign 64 5672 .L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5673 /* File: armv5te/OP_MUL_LONG_2ADDR.S */ 5674 /* 5675 * Signed 64-bit integer multiply, "/2addr" version. 5676 * 5677 * See OP_MUL_LONG for an explanation. 5678 * 5679 * We get a little tight on registers, so to avoid looking up &fp[A] 5680 * again we stuff it into rINST. 5681 */ 5682 /* mul-long/2addr vA, vB */ 5683 mov r9, rINST, lsr #8 @ r9<- A+ 5684 mov r1, rINST, lsr #12 @ r1<- B 5685 and r9, r9, #15 5686 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5687 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5688 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5689 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5690 mul ip, r2, r1 @ ip<- ZxW 5691 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5692 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5693 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5694 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5695 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5696 GET_INST_OPCODE(ip) @ extract opcode from rINST 5697 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5698 GOTO_OPCODE(ip) @ jump to next instruction 5699 5700 /* ------------------------------ */ 5701 .balign 64 5702 .L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5703 /* File: armv5te/OP_DIV_LONG_2ADDR.S */ 5704 /* File: armv5te/binopWide2addr.S */ 5705 /* 5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5708 * This could be an ARM instruction or a function call. (If the result 5709 * comes back in a register other than r0, you can override "result".) 5710 * 5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5712 * vCC (r1). Useful for integer division and modulus. 5713 * 5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5716 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5717 * rem-double/2addr 5718 */ 5719 /* binop/2addr vA, vB */ 5720 mov r9, rINST, lsr #8 @ r9<- A+ 5721 mov r1, rINST, lsr #12 @ r1<- B 5722 and r9, r9, #15 5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5727 .if 1 5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5729 beq common_errDivideByZero 5730 .endif 5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5732 5733 @ optional op; may set condition codes 5734 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5735 GET_INST_OPCODE(ip) @ extract opcode from rINST 5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5737 GOTO_OPCODE(ip) @ jump to next instruction 5738 /* 12-15 instructions */ 5739 5740 5741 /* ------------------------------ */ 5742 .balign 64 5743 .L_OP_REM_LONG_2ADDR: /* 0xbf */ 5744 /* File: armv5te/OP_REM_LONG_2ADDR.S */ 5745 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5746 /* File: armv5te/binopWide2addr.S */ 5747 /* 5748 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5749 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5750 * This could be an ARM instruction or a function call. (If the result 5751 * comes back in a register other than r0, you can override "result".) 5752 * 5753 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5754 * vCC (r1). Useful for integer division and modulus. 5755 * 5756 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5757 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5758 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5759 * rem-double/2addr 5760 */ 5761 /* binop/2addr vA, vB */ 5762 mov r9, rINST, lsr #8 @ r9<- A+ 5763 mov r1, rINST, lsr #12 @ r1<- B 5764 and r9, r9, #15 5765 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5766 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5767 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5768 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5769 .if 1 5770 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5771 beq common_errDivideByZero 5772 .endif 5773 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5774 5775 @ optional op; may set condition codes 5776 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5777 GET_INST_OPCODE(ip) @ extract opcode from rINST 5778 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5779 GOTO_OPCODE(ip) @ jump to next instruction 5780 /* 12-15 instructions */ 5781 5782 5783 /* ------------------------------ */ 5784 .balign 64 5785 .L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5786 /* File: armv5te/OP_AND_LONG_2ADDR.S */ 5787 /* File: armv5te/binopWide2addr.S */ 5788 /* 5789 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5790 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5791 * This could be an ARM instruction or a function call. (If the result 5792 * comes back in a register other than r0, you can override "result".) 5793 * 5794 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5795 * vCC (r1). Useful for integer division and modulus. 5796 * 5797 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5798 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5799 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5800 * rem-double/2addr 5801 */ 5802 /* binop/2addr vA, vB */ 5803 mov r9, rINST, lsr #8 @ r9<- A+ 5804 mov r1, rINST, lsr #12 @ r1<- B 5805 and r9, r9, #15 5806 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5807 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5808 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5809 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5810 .if 0 5811 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5812 beq common_errDivideByZero 5813 .endif 5814 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5815 5816 and r0, r0, r2 @ optional op; may set condition codes 5817 and r1, r1, r3 @ result<- op, r0-r3 changed 5818 GET_INST_OPCODE(ip) @ extract opcode from rINST 5819 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5820 GOTO_OPCODE(ip) @ jump to next instruction 5821 /* 12-15 instructions */ 5822 5823 5824 /* ------------------------------ */ 5825 .balign 64 5826 .L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5827 /* File: armv5te/OP_OR_LONG_2ADDR.S */ 5828 /* File: armv5te/binopWide2addr.S */ 5829 /* 5830 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5831 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5832 * This could be an ARM instruction or a function call. (If the result 5833 * comes back in a register other than r0, you can override "result".) 5834 * 5835 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5836 * vCC (r1). Useful for integer division and modulus. 5837 * 5838 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5839 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5840 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5841 * rem-double/2addr 5842 */ 5843 /* binop/2addr vA, vB */ 5844 mov r9, rINST, lsr #8 @ r9<- A+ 5845 mov r1, rINST, lsr #12 @ r1<- B 5846 and r9, r9, #15 5847 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5848 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5849 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5850 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5851 .if 0 5852 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5853 beq common_errDivideByZero 5854 .endif 5855 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5856 5857 orr r0, r0, r2 @ optional op; may set condition codes 5858 orr r1, r1, r3 @ result<- op, r0-r3 changed 5859 GET_INST_OPCODE(ip) @ extract opcode from rINST 5860 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5861 GOTO_OPCODE(ip) @ jump to next instruction 5862 /* 12-15 instructions */ 5863 5864 5865 /* ------------------------------ */ 5866 .balign 64 5867 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5868 /* File: armv5te/OP_XOR_LONG_2ADDR.S */ 5869 /* File: armv5te/binopWide2addr.S */ 5870 /* 5871 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5872 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5873 * This could be an ARM instruction or a function call. (If the result 5874 * comes back in a register other than r0, you can override "result".) 5875 * 5876 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5877 * vCC (r1). Useful for integer division and modulus. 5878 * 5879 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5880 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5881 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5882 * rem-double/2addr 5883 */ 5884 /* binop/2addr vA, vB */ 5885 mov r9, rINST, lsr #8 @ r9<- A+ 5886 mov r1, rINST, lsr #12 @ r1<- B 5887 and r9, r9, #15 5888 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5889 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5890 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5891 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5892 .if 0 5893 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5894 beq common_errDivideByZero 5895 .endif 5896 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5897 5898 eor r0, r0, r2 @ optional op; may set condition codes 5899 eor r1, r1, r3 @ result<- op, r0-r3 changed 5900 GET_INST_OPCODE(ip) @ extract opcode from rINST 5901 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5902 GOTO_OPCODE(ip) @ jump to next instruction 5903 /* 12-15 instructions */ 5904 5905 5906 /* ------------------------------ */ 5907 .balign 64 5908 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5909 /* File: armv5te/OP_SHL_LONG_2ADDR.S */ 5910 /* 5911 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5912 * 32-bit shift distance. 5913 */ 5914 /* shl-long/2addr vA, vB */ 5915 mov r9, rINST, lsr #8 @ r9<- A+ 5916 mov r3, rINST, lsr #12 @ r3<- B 5917 and r9, r9, #15 5918 GET_VREG(r2, r3) @ r2<- vB 5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5920 and r2, r2, #63 @ r2<- r2 & 0x3f 5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5922 5923 mov r1, r1, asl r2 @ r1<- r1 << r2 5924 rsb r3, r2, #32 @ r3<- 32 - r2 5925 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5926 subs ip, r2, #32 @ ip<- r2 - 32 5927 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5928 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 5929 mov r0, r0, asl r2 @ r0<- r0 << r2 5930 b .LOP_SHL_LONG_2ADDR_finish 5931 5932 /* ------------------------------ */ 5933 .balign 64 5934 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 5935 /* File: armv5te/OP_SHR_LONG_2ADDR.S */ 5936 /* 5937 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5938 * 32-bit shift distance. 5939 */ 5940 /* shr-long/2addr vA, vB */ 5941 mov r9, rINST, lsr #8 @ r9<- A+ 5942 mov r3, rINST, lsr #12 @ r3<- B 5943 and r9, r9, #15 5944 GET_VREG(r2, r3) @ r2<- vB 5945 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5946 and r2, r2, #63 @ r2<- r2 & 0x3f 5947 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5948 5949 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5950 rsb r3, r2, #32 @ r3<- 32 - r2 5951 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5952 subs ip, r2, #32 @ ip<- r2 - 32 5953 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5954 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 5955 mov r1, r1, asr r2 @ r1<- r1 >> r2 5956 b .LOP_SHR_LONG_2ADDR_finish 5957 5958 /* ------------------------------ */ 5959 .balign 64 5960 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 5961 /* File: armv5te/OP_USHR_LONG_2ADDR.S */ 5962 /* 5963 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5964 * 32-bit shift distance. 5965 */ 5966 /* ushr-long/2addr vA, vB */ 5967 mov r9, rINST, lsr #8 @ r9<- A+ 5968 mov r3, rINST, lsr #12 @ r3<- B 5969 and r9, r9, #15 5970 GET_VREG(r2, r3) @ r2<- vB 5971 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5972 and r2, r2, #63 @ r2<- r2 & 0x3f 5973 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5974 5975 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5976 rsb r3, r2, #32 @ r3<- 32 - r2 5977 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5978 subs ip, r2, #32 @ ip<- r2 - 32 5979 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5980 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 5981 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 5982 b .LOP_USHR_LONG_2ADDR_finish 5983 5984 /* ------------------------------ */ 5985 .balign 64 5986 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 5987 /* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 5988 /* File: arm-vfp/fbinop2addr.S */ 5989 /* 5990 * Generic 32-bit floating point "/2addr" binary operation. Provide 5991 * an "instr" line that specifies an instruction that performs 5992 * "s2 = s0 op s1". 5993 * 5994 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5995 */ 5996 /* binop/2addr vA, vB */ 5997 mov r3, rINST, lsr #12 @ r3<- B 5998 mov r9, rINST, lsr #8 @ r9<- A+ 5999 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6000 and r9, r9, #15 @ r9<- A 6001 flds s1, [r3] @ s1<- vB 6002 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6003 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6004 flds s0, [r9] @ s0<- vA 6005 6006 fadds s2, s0, s1 @ s2<- op 6007 GET_INST_OPCODE(ip) @ extract opcode from rINST 6008 fsts s2, [r9] @ vAA<- s2 6009 GOTO_OPCODE(ip) @ jump to next instruction 6010 6011 6012 /* ------------------------------ */ 6013 .balign 64 6014 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6015 /* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6016 /* File: arm-vfp/fbinop2addr.S */ 6017 /* 6018 * Generic 32-bit floating point "/2addr" binary operation. Provide 6019 * an "instr" line that specifies an instruction that performs 6020 * "s2 = s0 op s1". 6021 * 6022 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6023 */ 6024 /* binop/2addr vA, vB */ 6025 mov r3, rINST, lsr #12 @ r3<- B 6026 mov r9, rINST, lsr #8 @ r9<- A+ 6027 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6028 and r9, r9, #15 @ r9<- A 6029 flds s1, [r3] @ s1<- vB 6030 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6031 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6032 flds s0, [r9] @ s0<- vA 6033 6034 fsubs s2, s0, s1 @ s2<- op 6035 GET_INST_OPCODE(ip) @ extract opcode from rINST 6036 fsts s2, [r9] @ vAA<- s2 6037 GOTO_OPCODE(ip) @ jump to next instruction 6038 6039 6040 /* ------------------------------ */ 6041 .balign 64 6042 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6043 /* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6044 /* File: arm-vfp/fbinop2addr.S */ 6045 /* 6046 * Generic 32-bit floating point "/2addr" binary operation. Provide 6047 * an "instr" line that specifies an instruction that performs 6048 * "s2 = s0 op s1". 6049 * 6050 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6051 */ 6052 /* binop/2addr vA, vB */ 6053 mov r3, rINST, lsr #12 @ r3<- B 6054 mov r9, rINST, lsr #8 @ r9<- A+ 6055 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6056 and r9, r9, #15 @ r9<- A 6057 flds s1, [r3] @ s1<- vB 6058 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6059 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6060 flds s0, [r9] @ s0<- vA 6061 6062 fmuls s2, s0, s1 @ s2<- op 6063 GET_INST_OPCODE(ip) @ extract opcode from rINST 6064 fsts s2, [r9] @ vAA<- s2 6065 GOTO_OPCODE(ip) @ jump to next instruction 6066 6067 6068 /* ------------------------------ */ 6069 .balign 64 6070 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6071 /* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6072 /* File: arm-vfp/fbinop2addr.S */ 6073 /* 6074 * Generic 32-bit floating point "/2addr" binary operation. Provide 6075 * an "instr" line that specifies an instruction that performs 6076 * "s2 = s0 op s1". 6077 * 6078 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6079 */ 6080 /* binop/2addr vA, vB */ 6081 mov r3, rINST, lsr #12 @ r3<- B 6082 mov r9, rINST, lsr #8 @ r9<- A+ 6083 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6084 and r9, r9, #15 @ r9<- A 6085 flds s1, [r3] @ s1<- vB 6086 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6087 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6088 flds s0, [r9] @ s0<- vA 6089 6090 fdivs s2, s0, s1 @ s2<- op 6091 GET_INST_OPCODE(ip) @ extract opcode from rINST 6092 fsts s2, [r9] @ vAA<- s2 6093 GOTO_OPCODE(ip) @ jump to next instruction 6094 6095 6096 /* ------------------------------ */ 6097 .balign 64 6098 .L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6099 /* File: armv5te/OP_REM_FLOAT_2ADDR.S */ 6100 /* EABI doesn't define a float remainder function, but libm does */ 6101 /* File: armv5te/binop2addr.S */ 6102 /* 6103 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6104 * that specifies an instruction that performs "result = r0 op r1". 6105 * This could be an ARM instruction or a function call. (If the result 6106 * comes back in a register other than r0, you can override "result".) 6107 * 6108 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6109 * vCC (r1). Useful for integer division and modulus. 6110 * 6111 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6112 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6113 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6114 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6115 */ 6116 /* binop/2addr vA, vB */ 6117 mov r9, rINST, lsr #8 @ r9<- A+ 6118 mov r3, rINST, lsr #12 @ r3<- B 6119 and r9, r9, #15 6120 GET_VREG(r1, r3) @ r1<- vB 6121 GET_VREG(r0, r9) @ r0<- vA 6122 .if 0 6123 cmp r1, #0 @ is second operand zero? 6124 beq common_errDivideByZero 6125 .endif 6126 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6127 6128 @ optional op; may set condition codes 6129 bl fmodf @ r0<- op, r0-r3 changed 6130 GET_INST_OPCODE(ip) @ extract opcode from rINST 6131 SET_VREG(r0, r9) @ vAA<- r0 6132 GOTO_OPCODE(ip) @ jump to next instruction 6133 /* 10-13 instructions */ 6134 6135 6136 /* ------------------------------ */ 6137 .balign 64 6138 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6139 /* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6140 /* File: arm-vfp/fbinopWide2addr.S */ 6141 /* 6142 * Generic 64-bit floating point "/2addr" binary operation. Provide 6143 * an "instr" line that specifies an instruction that performs 6144 * "d2 = d0 op d1". 6145 * 6146 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6147 * div-double/2addr 6148 */ 6149 /* binop/2addr vA, vB */ 6150 mov r3, rINST, lsr #12 @ r3<- B 6151 mov r9, rINST, lsr #8 @ r9<- A+ 6152 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6153 and r9, r9, #15 @ r9<- A 6154 fldd d1, [r3] @ d1<- vB 6155 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6156 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6157 fldd d0, [r9] @ d0<- vA 6158 6159 faddd d2, d0, d1 @ d2<- op 6160 GET_INST_OPCODE(ip) @ extract opcode from rINST 6161 fstd d2, [r9] @ vAA<- d2 6162 GOTO_OPCODE(ip) @ jump to next instruction 6163 6164 6165 /* ------------------------------ */ 6166 .balign 64 6167 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6168 /* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6169 /* File: arm-vfp/fbinopWide2addr.S */ 6170 /* 6171 * Generic 64-bit floating point "/2addr" binary operation. Provide 6172 * an "instr" line that specifies an instruction that performs 6173 * "d2 = d0 op d1". 6174 * 6175 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6176 * div-double/2addr 6177 */ 6178 /* binop/2addr vA, vB */ 6179 mov r3, rINST, lsr #12 @ r3<- B 6180 mov r9, rINST, lsr #8 @ r9<- A+ 6181 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6182 and r9, r9, #15 @ r9<- A 6183 fldd d1, [r3] @ d1<- vB 6184 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6185 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6186 fldd d0, [r9] @ d0<- vA 6187 6188 fsubd d2, d0, d1 @ d2<- op 6189 GET_INST_OPCODE(ip) @ extract opcode from rINST 6190 fstd d2, [r9] @ vAA<- d2 6191 GOTO_OPCODE(ip) @ jump to next instruction 6192 6193 6194 /* ------------------------------ */ 6195 .balign 64 6196 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6197 /* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6198 /* File: arm-vfp/fbinopWide2addr.S */ 6199 /* 6200 * Generic 64-bit floating point "/2addr" binary operation. Provide 6201 * an "instr" line that specifies an instruction that performs 6202 * "d2 = d0 op d1". 6203 * 6204 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6205 * div-double/2addr 6206 */ 6207 /* binop/2addr vA, vB */ 6208 mov r3, rINST, lsr #12 @ r3<- B 6209 mov r9, rINST, lsr #8 @ r9<- A+ 6210 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6211 and r9, r9, #15 @ r9<- A 6212 fldd d1, [r3] @ d1<- vB 6213 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6214 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6215 fldd d0, [r9] @ d0<- vA 6216 6217 fmuld d2, d0, d1 @ d2<- op 6218 GET_INST_OPCODE(ip) @ extract opcode from rINST 6219 fstd d2, [r9] @ vAA<- d2 6220 GOTO_OPCODE(ip) @ jump to next instruction 6221 6222 6223 /* ------------------------------ */ 6224 .balign 64 6225 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6226 /* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6227 /* File: arm-vfp/fbinopWide2addr.S */ 6228 /* 6229 * Generic 64-bit floating point "/2addr" binary operation. Provide 6230 * an "instr" line that specifies an instruction that performs 6231 * "d2 = d0 op d1". 6232 * 6233 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6234 * div-double/2addr 6235 */ 6236 /* binop/2addr vA, vB */ 6237 mov r3, rINST, lsr #12 @ r3<- B 6238 mov r9, rINST, lsr #8 @ r9<- A+ 6239 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6240 and r9, r9, #15 @ r9<- A 6241 fldd d1, [r3] @ d1<- vB 6242 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6243 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6244 fldd d0, [r9] @ d0<- vA 6245 6246 fdivd d2, d0, d1 @ d2<- op 6247 GET_INST_OPCODE(ip) @ extract opcode from rINST 6248 fstd d2, [r9] @ vAA<- d2 6249 GOTO_OPCODE(ip) @ jump to next instruction 6250 6251 6252 /* ------------------------------ */ 6253 .balign 64 6254 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6255 /* File: armv5te/OP_REM_DOUBLE_2ADDR.S */ 6256 /* EABI doesn't define a double remainder function, but libm does */ 6257 /* File: armv5te/binopWide2addr.S */ 6258 /* 6259 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6260 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6261 * This could be an ARM instruction or a function call. (If the result 6262 * comes back in a register other than r0, you can override "result".) 6263 * 6264 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6265 * vCC (r1). Useful for integer division and modulus. 6266 * 6267 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6268 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6269 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6270 * rem-double/2addr 6271 */ 6272 /* binop/2addr vA, vB */ 6273 mov r9, rINST, lsr #8 @ r9<- A+ 6274 mov r1, rINST, lsr #12 @ r1<- B 6275 and r9, r9, #15 6276 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6277 add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6278 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6279 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6280 .if 0 6281 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6282 beq common_errDivideByZero 6283 .endif 6284 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6285 6286 @ optional op; may set condition codes 6287 bl fmod @ result<- op, r0-r3 changed 6288 GET_INST_OPCODE(ip) @ extract opcode from rINST 6289 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6290 GOTO_OPCODE(ip) @ jump to next instruction 6291 /* 12-15 instructions */ 6292 6293 6294 /* ------------------------------ */ 6295 .balign 64 6296 .L_OP_ADD_INT_LIT16: /* 0xd0 */ 6297 /* File: armv5te/OP_ADD_INT_LIT16.S */ 6298 /* File: armv5te/binopLit16.S */ 6299 /* 6300 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6301 * that specifies an instruction that performs "result = r0 op r1". 6302 * This could be an ARM instruction or a function call. (If the result 6303 * comes back in a register other than r0, you can override "result".) 6304 * 6305 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6306 * vCC (r1). Useful for integer division and modulus. 6307 * 6308 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6309 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6310 */ 6311 /* binop/lit16 vA, vB, #+CCCC */ 6312 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6313 mov r2, rINST, lsr #12 @ r2<- B 6314 mov r9, rINST, lsr #8 @ r9<- A+ 6315 GET_VREG(r0, r2) @ r0<- vB 6316 and r9, r9, #15 6317 .if 0 6318 cmp r1, #0 @ is second operand zero? 6319 beq common_errDivideByZero 6320 .endif 6321 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6322 6323 add r0, r0, r1 @ r0<- op, r0-r3 changed 6324 GET_INST_OPCODE(ip) @ extract opcode from rINST 6325 SET_VREG(r0, r9) @ vAA<- r0 6326 GOTO_OPCODE(ip) @ jump to next instruction 6327 /* 10-13 instructions */ 6328 6329 6330 /* ------------------------------ */ 6331 .balign 64 6332 .L_OP_RSUB_INT: /* 0xd1 */ 6333 /* File: armv5te/OP_RSUB_INT.S */ 6334 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6335 /* File: armv5te/binopLit16.S */ 6336 /* 6337 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6338 * that specifies an instruction that performs "result = r0 op r1". 6339 * This could be an ARM instruction or a function call. (If the result 6340 * comes back in a register other than r0, you can override "result".) 6341 * 6342 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6343 * vCC (r1). Useful for integer division and modulus. 6344 * 6345 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6346 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6347 */ 6348 /* binop/lit16 vA, vB, #+CCCC */ 6349 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6350 mov r2, rINST, lsr #12 @ r2<- B 6351 mov r9, rINST, lsr #8 @ r9<- A+ 6352 GET_VREG(r0, r2) @ r0<- vB 6353 and r9, r9, #15 6354 .if 0 6355 cmp r1, #0 @ is second operand zero? 6356 beq common_errDivideByZero 6357 .endif 6358 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6359 6360 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6361 GET_INST_OPCODE(ip) @ extract opcode from rINST 6362 SET_VREG(r0, r9) @ vAA<- r0 6363 GOTO_OPCODE(ip) @ jump to next instruction 6364 /* 10-13 instructions */ 6365 6366 6367 /* ------------------------------ */ 6368 .balign 64 6369 .L_OP_MUL_INT_LIT16: /* 0xd2 */ 6370 /* File: armv5te/OP_MUL_INT_LIT16.S */ 6371 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6372 /* File: armv5te/binopLit16.S */ 6373 /* 6374 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6375 * that specifies an instruction that performs "result = r0 op r1". 6376 * This could be an ARM instruction or a function call. (If the result 6377 * comes back in a register other than r0, you can override "result".) 6378 * 6379 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6380 * vCC (r1). Useful for integer division and modulus. 6381 * 6382 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6383 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6384 */ 6385 /* binop/lit16 vA, vB, #+CCCC */ 6386 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6387 mov r2, rINST, lsr #12 @ r2<- B 6388 mov r9, rINST, lsr #8 @ r9<- A+ 6389 GET_VREG(r0, r2) @ r0<- vB 6390 and r9, r9, #15 6391 .if 0 6392 cmp r1, #0 @ is second operand zero? 6393 beq common_errDivideByZero 6394 .endif 6395 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6396 6397 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6398 GET_INST_OPCODE(ip) @ extract opcode from rINST 6399 SET_VREG(r0, r9) @ vAA<- r0 6400 GOTO_OPCODE(ip) @ jump to next instruction 6401 /* 10-13 instructions */ 6402 6403 6404 /* ------------------------------ */ 6405 .balign 64 6406 .L_OP_DIV_INT_LIT16: /* 0xd3 */ 6407 /* File: armv5te/OP_DIV_INT_LIT16.S */ 6408 /* File: armv5te/binopLit16.S */ 6409 /* 6410 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6411 * that specifies an instruction that performs "result = r0 op r1". 6412 * This could be an ARM instruction or a function call. (If the result 6413 * comes back in a register other than r0, you can override "result".) 6414 * 6415 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6416 * vCC (r1). Useful for integer division and modulus. 6417 * 6418 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6419 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6420 */ 6421 /* binop/lit16 vA, vB, #+CCCC */ 6422 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6423 mov r2, rINST, lsr #12 @ r2<- B 6424 mov r9, rINST, lsr #8 @ r9<- A+ 6425 GET_VREG(r0, r2) @ r0<- vB 6426 and r9, r9, #15 6427 .if 1 6428 cmp r1, #0 @ is second operand zero? 6429 beq common_errDivideByZero 6430 .endif 6431 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6432 6433 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6434 GET_INST_OPCODE(ip) @ extract opcode from rINST 6435 SET_VREG(r0, r9) @ vAA<- r0 6436 GOTO_OPCODE(ip) @ jump to next instruction 6437 /* 10-13 instructions */ 6438 6439 6440 /* ------------------------------ */ 6441 .balign 64 6442 .L_OP_REM_INT_LIT16: /* 0xd4 */ 6443 /* File: armv5te/OP_REM_INT_LIT16.S */ 6444 /* idivmod returns quotient in r0 and remainder in r1 */ 6445 /* File: armv5te/binopLit16.S */ 6446 /* 6447 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6448 * that specifies an instruction that performs "result = r0 op r1". 6449 * This could be an ARM instruction or a function call. (If the result 6450 * comes back in a register other than r0, you can override "result".) 6451 * 6452 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6453 * vCC (r1). Useful for integer division and modulus. 6454 * 6455 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6456 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6457 */ 6458 /* binop/lit16 vA, vB, #+CCCC */ 6459 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6460 mov r2, rINST, lsr #12 @ r2<- B 6461 mov r9, rINST, lsr #8 @ r9<- A+ 6462 GET_VREG(r0, r2) @ r0<- vB 6463 and r9, r9, #15 6464 .if 1 6465 cmp r1, #0 @ is second operand zero? 6466 beq common_errDivideByZero 6467 .endif 6468 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6469 6470 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6471 GET_INST_OPCODE(ip) @ extract opcode from rINST 6472 SET_VREG(r1, r9) @ vAA<- r1 6473 GOTO_OPCODE(ip) @ jump to next instruction 6474 /* 10-13 instructions */ 6475 6476 6477 /* ------------------------------ */ 6478 .balign 64 6479 .L_OP_AND_INT_LIT16: /* 0xd5 */ 6480 /* File: armv5te/OP_AND_INT_LIT16.S */ 6481 /* File: armv5te/binopLit16.S */ 6482 /* 6483 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6484 * that specifies an instruction that performs "result = r0 op r1". 6485 * This could be an ARM instruction or a function call. (If the result 6486 * comes back in a register other than r0, you can override "result".) 6487 * 6488 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6489 * vCC (r1). Useful for integer division and modulus. 6490 * 6491 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6492 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6493 */ 6494 /* binop/lit16 vA, vB, #+CCCC */ 6495 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6496 mov r2, rINST, lsr #12 @ r2<- B 6497 mov r9, rINST, lsr #8 @ r9<- A+ 6498 GET_VREG(r0, r2) @ r0<- vB 6499 and r9, r9, #15 6500 .if 0 6501 cmp r1, #0 @ is second operand zero? 6502 beq common_errDivideByZero 6503 .endif 6504 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6505 6506 and r0, r0, r1 @ r0<- op, r0-r3 changed 6507 GET_INST_OPCODE(ip) @ extract opcode from rINST 6508 SET_VREG(r0, r9) @ vAA<- r0 6509 GOTO_OPCODE(ip) @ jump to next instruction 6510 /* 10-13 instructions */ 6511 6512 6513 /* ------------------------------ */ 6514 .balign 64 6515 .L_OP_OR_INT_LIT16: /* 0xd6 */ 6516 /* File: armv5te/OP_OR_INT_LIT16.S */ 6517 /* File: armv5te/binopLit16.S */ 6518 /* 6519 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6520 * that specifies an instruction that performs "result = r0 op r1". 6521 * This could be an ARM instruction or a function call. (If the result 6522 * comes back in a register other than r0, you can override "result".) 6523 * 6524 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6525 * vCC (r1). Useful for integer division and modulus. 6526 * 6527 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6528 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6529 */ 6530 /* binop/lit16 vA, vB, #+CCCC */ 6531 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6532 mov r2, rINST, lsr #12 @ r2<- B 6533 mov r9, rINST, lsr #8 @ r9<- A+ 6534 GET_VREG(r0, r2) @ r0<- vB 6535 and r9, r9, #15 6536 .if 0 6537 cmp r1, #0 @ is second operand zero? 6538 beq common_errDivideByZero 6539 .endif 6540 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6541 6542 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6543 GET_INST_OPCODE(ip) @ extract opcode from rINST 6544 SET_VREG(r0, r9) @ vAA<- r0 6545 GOTO_OPCODE(ip) @ jump to next instruction 6546 /* 10-13 instructions */ 6547 6548 6549 /* ------------------------------ */ 6550 .balign 64 6551 .L_OP_XOR_INT_LIT16: /* 0xd7 */ 6552 /* File: armv5te/OP_XOR_INT_LIT16.S */ 6553 /* File: armv5te/binopLit16.S */ 6554 /* 6555 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6556 * that specifies an instruction that performs "result = r0 op r1". 6557 * This could be an ARM instruction or a function call. (If the result 6558 * comes back in a register other than r0, you can override "result".) 6559 * 6560 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6561 * vCC (r1). Useful for integer division and modulus. 6562 * 6563 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6564 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6565 */ 6566 /* binop/lit16 vA, vB, #+CCCC */ 6567 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6568 mov r2, rINST, lsr #12 @ r2<- B 6569 mov r9, rINST, lsr #8 @ r9<- A+ 6570 GET_VREG(r0, r2) @ r0<- vB 6571 and r9, r9, #15 6572 .if 0 6573 cmp r1, #0 @ is second operand zero? 6574 beq common_errDivideByZero 6575 .endif 6576 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6577 6578 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6579 GET_INST_OPCODE(ip) @ extract opcode from rINST 6580 SET_VREG(r0, r9) @ vAA<- r0 6581 GOTO_OPCODE(ip) @ jump to next instruction 6582 /* 10-13 instructions */ 6583 6584 6585 /* ------------------------------ */ 6586 .balign 64 6587 .L_OP_ADD_INT_LIT8: /* 0xd8 */ 6588 /* File: armv5te/OP_ADD_INT_LIT8.S */ 6589 /* File: armv5te/binopLit8.S */ 6590 /* 6591 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6592 * that specifies an instruction that performs "result = r0 op r1". 6593 * This could be an ARM instruction or a function call. (If the result 6594 * comes back in a register other than r0, you can override "result".) 6595 * 6596 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6597 * vCC (r1). Useful for integer division and modulus. 6598 * 6599 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6600 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6601 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6602 */ 6603 /* binop/lit8 vAA, vBB, #+CC */ 6604 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6605 mov r9, rINST, lsr #8 @ r9<- AA 6606 and r2, r3, #255 @ r2<- BB 6607 GET_VREG(r0, r2) @ r0<- vBB 6608 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6609 .if 0 6610 @cmp r1, #0 @ is second operand zero? 6611 beq common_errDivideByZero 6612 .endif 6613 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6614 6615 @ optional op; may set condition codes 6616 add r0, r0, r1 @ r0<- op, r0-r3 changed 6617 GET_INST_OPCODE(ip) @ extract opcode from rINST 6618 SET_VREG(r0, r9) @ vAA<- r0 6619 GOTO_OPCODE(ip) @ jump to next instruction 6620 /* 10-12 instructions */ 6621 6622 6623 /* ------------------------------ */ 6624 .balign 64 6625 .L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6626 /* File: armv5te/OP_RSUB_INT_LIT8.S */ 6627 /* File: armv5te/binopLit8.S */ 6628 /* 6629 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6630 * that specifies an instruction that performs "result = r0 op r1". 6631 * This could be an ARM instruction or a function call. (If the result 6632 * comes back in a register other than r0, you can override "result".) 6633 * 6634 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6635 * vCC (r1). Useful for integer division and modulus. 6636 * 6637 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6638 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6639 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6640 */ 6641 /* binop/lit8 vAA, vBB, #+CC */ 6642 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6643 mov r9, rINST, lsr #8 @ r9<- AA 6644 and r2, r3, #255 @ r2<- BB 6645 GET_VREG(r0, r2) @ r0<- vBB 6646 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6647 .if 0 6648 @cmp r1, #0 @ is second operand zero? 6649 beq common_errDivideByZero 6650 .endif 6651 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6652 6653 @ optional op; may set condition codes 6654 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6655 GET_INST_OPCODE(ip) @ extract opcode from rINST 6656 SET_VREG(r0, r9) @ vAA<- r0 6657 GOTO_OPCODE(ip) @ jump to next instruction 6658 /* 10-12 instructions */ 6659 6660 6661 /* ------------------------------ */ 6662 .balign 64 6663 .L_OP_MUL_INT_LIT8: /* 0xda */ 6664 /* File: armv5te/OP_MUL_INT_LIT8.S */ 6665 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6666 /* File: armv5te/binopLit8.S */ 6667 /* 6668 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6669 * that specifies an instruction that performs "result = r0 op r1". 6670 * This could be an ARM instruction or a function call. (If the result 6671 * comes back in a register other than r0, you can override "result".) 6672 * 6673 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6674 * vCC (r1). Useful for integer division and modulus. 6675 * 6676 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6677 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6678 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6679 */ 6680 /* binop/lit8 vAA, vBB, #+CC */ 6681 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6682 mov r9, rINST, lsr #8 @ r9<- AA 6683 and r2, r3, #255 @ r2<- BB 6684 GET_VREG(r0, r2) @ r0<- vBB 6685 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6686 .if 0 6687 @cmp r1, #0 @ is second operand zero? 6688 beq common_errDivideByZero 6689 .endif 6690 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6691 6692 @ optional op; may set condition codes 6693 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6694 GET_INST_OPCODE(ip) @ extract opcode from rINST 6695 SET_VREG(r0, r9) @ vAA<- r0 6696 GOTO_OPCODE(ip) @ jump to next instruction 6697 /* 10-12 instructions */ 6698 6699 6700 /* ------------------------------ */ 6701 .balign 64 6702 .L_OP_DIV_INT_LIT8: /* 0xdb */ 6703 /* File: armv5te/OP_DIV_INT_LIT8.S */ 6704 /* File: armv5te/binopLit8.S */ 6705 /* 6706 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6707 * that specifies an instruction that performs "result = r0 op r1". 6708 * This could be an ARM instruction or a function call. (If the result 6709 * comes back in a register other than r0, you can override "result".) 6710 * 6711 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6712 * vCC (r1). Useful for integer division and modulus. 6713 * 6714 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6715 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6716 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6717 */ 6718 /* binop/lit8 vAA, vBB, #+CC */ 6719 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6720 mov r9, rINST, lsr #8 @ r9<- AA 6721 and r2, r3, #255 @ r2<- BB 6722 GET_VREG(r0, r2) @ r0<- vBB 6723 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6724 .if 1 6725 @cmp r1, #0 @ is second operand zero? 6726 beq common_errDivideByZero 6727 .endif 6728 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6729 6730 @ optional op; may set condition codes 6731 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6732 GET_INST_OPCODE(ip) @ extract opcode from rINST 6733 SET_VREG(r0, r9) @ vAA<- r0 6734 GOTO_OPCODE(ip) @ jump to next instruction 6735 /* 10-12 instructions */ 6736 6737 6738 /* ------------------------------ */ 6739 .balign 64 6740 .L_OP_REM_INT_LIT8: /* 0xdc */ 6741 /* File: armv5te/OP_REM_INT_LIT8.S */ 6742 /* idivmod returns quotient in r0 and remainder in r1 */ 6743 /* File: armv5te/binopLit8.S */ 6744 /* 6745 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6746 * that specifies an instruction that performs "result = r0 op r1". 6747 * This could be an ARM instruction or a function call. (If the result 6748 * comes back in a register other than r0, you can override "result".) 6749 * 6750 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6751 * vCC (r1). Useful for integer division and modulus. 6752 * 6753 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6754 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6755 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6756 */ 6757 /* binop/lit8 vAA, vBB, #+CC */ 6758 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6759 mov r9, rINST, lsr #8 @ r9<- AA 6760 and r2, r3, #255 @ r2<- BB 6761 GET_VREG(r0, r2) @ r0<- vBB 6762 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6763 .if 1 6764 @cmp r1, #0 @ is second operand zero? 6765 beq common_errDivideByZero 6766 .endif 6767 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6768 6769 @ optional op; may set condition codes 6770 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6771 GET_INST_OPCODE(ip) @ extract opcode from rINST 6772 SET_VREG(r1, r9) @ vAA<- r1 6773 GOTO_OPCODE(ip) @ jump to next instruction 6774 /* 10-12 instructions */ 6775 6776 6777 /* ------------------------------ */ 6778 .balign 64 6779 .L_OP_AND_INT_LIT8: /* 0xdd */ 6780 /* File: armv5te/OP_AND_INT_LIT8.S */ 6781 /* File: armv5te/binopLit8.S */ 6782 /* 6783 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6784 * that specifies an instruction that performs "result = r0 op r1". 6785 * This could be an ARM instruction or a function call. (If the result 6786 * comes back in a register other than r0, you can override "result".) 6787 * 6788 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6789 * vCC (r1). Useful for integer division and modulus. 6790 * 6791 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6792 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6793 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6794 */ 6795 /* binop/lit8 vAA, vBB, #+CC */ 6796 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6797 mov r9, rINST, lsr #8 @ r9<- AA 6798 and r2, r3, #255 @ r2<- BB 6799 GET_VREG(r0, r2) @ r0<- vBB 6800 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6801 .if 0 6802 @cmp r1, #0 @ is second operand zero? 6803 beq common_errDivideByZero 6804 .endif 6805 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6806 6807 @ optional op; may set condition codes 6808 and r0, r0, r1 @ r0<- op, r0-r3 changed 6809 GET_INST_OPCODE(ip) @ extract opcode from rINST 6810 SET_VREG(r0, r9) @ vAA<- r0 6811 GOTO_OPCODE(ip) @ jump to next instruction 6812 /* 10-12 instructions */ 6813 6814 6815 /* ------------------------------ */ 6816 .balign 64 6817 .L_OP_OR_INT_LIT8: /* 0xde */ 6818 /* File: armv5te/OP_OR_INT_LIT8.S */ 6819 /* File: armv5te/binopLit8.S */ 6820 /* 6821 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6822 * that specifies an instruction that performs "result = r0 op r1". 6823 * This could be an ARM instruction or a function call. (If the result 6824 * comes back in a register other than r0, you can override "result".) 6825 * 6826 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6827 * vCC (r1). Useful for integer division and modulus. 6828 * 6829 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6830 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6831 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6832 */ 6833 /* binop/lit8 vAA, vBB, #+CC */ 6834 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6835 mov r9, rINST, lsr #8 @ r9<- AA 6836 and r2, r3, #255 @ r2<- BB 6837 GET_VREG(r0, r2) @ r0<- vBB 6838 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6839 .if 0 6840 @cmp r1, #0 @ is second operand zero? 6841 beq common_errDivideByZero 6842 .endif 6843 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6844 6845 @ optional op; may set condition codes 6846 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6847 GET_INST_OPCODE(ip) @ extract opcode from rINST 6848 SET_VREG(r0, r9) @ vAA<- r0 6849 GOTO_OPCODE(ip) @ jump to next instruction 6850 /* 10-12 instructions */ 6851 6852 6853 /* ------------------------------ */ 6854 .balign 64 6855 .L_OP_XOR_INT_LIT8: /* 0xdf */ 6856 /* File: armv5te/OP_XOR_INT_LIT8.S */ 6857 /* File: armv5te/binopLit8.S */ 6858 /* 6859 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6860 * that specifies an instruction that performs "result = r0 op r1". 6861 * This could be an ARM instruction or a function call. (If the result 6862 * comes back in a register other than r0, you can override "result".) 6863 * 6864 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6865 * vCC (r1). Useful for integer division and modulus. 6866 * 6867 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6868 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6869 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6870 */ 6871 /* binop/lit8 vAA, vBB, #+CC */ 6872 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6873 mov r9, rINST, lsr #8 @ r9<- AA 6874 and r2, r3, #255 @ r2<- BB 6875 GET_VREG(r0, r2) @ r0<- vBB 6876 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6877 .if 0 6878 @cmp r1, #0 @ is second operand zero? 6879 beq common_errDivideByZero 6880 .endif 6881 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6882 6883 @ optional op; may set condition codes 6884 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6885 GET_INST_OPCODE(ip) @ extract opcode from rINST 6886 SET_VREG(r0, r9) @ vAA<- r0 6887 GOTO_OPCODE(ip) @ jump to next instruction 6888 /* 10-12 instructions */ 6889 6890 6891 /* ------------------------------ */ 6892 .balign 64 6893 .L_OP_SHL_INT_LIT8: /* 0xe0 */ 6894 /* File: armv5te/OP_SHL_INT_LIT8.S */ 6895 /* File: armv5te/binopLit8.S */ 6896 /* 6897 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6898 * that specifies an instruction that performs "result = r0 op r1". 6899 * This could be an ARM instruction or a function call. (If the result 6900 * comes back in a register other than r0, you can override "result".) 6901 * 6902 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6903 * vCC (r1). Useful for integer division and modulus. 6904 * 6905 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6906 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6907 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6908 */ 6909 /* binop/lit8 vAA, vBB, #+CC */ 6910 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6911 mov r9, rINST, lsr #8 @ r9<- AA 6912 and r2, r3, #255 @ r2<- BB 6913 GET_VREG(r0, r2) @ r0<- vBB 6914 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6915 .if 0 6916 @cmp r1, #0 @ is second operand zero? 6917 beq common_errDivideByZero 6918 .endif 6919 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6920 6921 and r1, r1, #31 @ optional op; may set condition codes 6922 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6923 GET_INST_OPCODE(ip) @ extract opcode from rINST 6924 SET_VREG(r0, r9) @ vAA<- r0 6925 GOTO_OPCODE(ip) @ jump to next instruction 6926 /* 10-12 instructions */ 6927 6928 6929 /* ------------------------------ */ 6930 .balign 64 6931 .L_OP_SHR_INT_LIT8: /* 0xe1 */ 6932 /* File: armv5te/OP_SHR_INT_LIT8.S */ 6933 /* File: armv5te/binopLit8.S */ 6934 /* 6935 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6936 * that specifies an instruction that performs "result = r0 op r1". 6937 * This could be an ARM instruction or a function call. (If the result 6938 * comes back in a register other than r0, you can override "result".) 6939 * 6940 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6941 * vCC (r1). Useful for integer division and modulus. 6942 * 6943 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6944 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6945 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6946 */ 6947 /* binop/lit8 vAA, vBB, #+CC */ 6948 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6949 mov r9, rINST, lsr #8 @ r9<- AA 6950 and r2, r3, #255 @ r2<- BB 6951 GET_VREG(r0, r2) @ r0<- vBB 6952 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6953 .if 0 6954 @cmp r1, #0 @ is second operand zero? 6955 beq common_errDivideByZero 6956 .endif 6957 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6958 6959 and r1, r1, #31 @ optional op; may set condition codes 6960 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 6961 GET_INST_OPCODE(ip) @ extract opcode from rINST 6962 SET_VREG(r0, r9) @ vAA<- r0 6963 GOTO_OPCODE(ip) @ jump to next instruction 6964 /* 10-12 instructions */ 6965 6966 6967 /* ------------------------------ */ 6968 .balign 64 6969 .L_OP_USHR_INT_LIT8: /* 0xe2 */ 6970 /* File: armv5te/OP_USHR_INT_LIT8.S */ 6971 /* File: armv5te/binopLit8.S */ 6972 /* 6973 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6974 * that specifies an instruction that performs "result = r0 op r1". 6975 * This could be an ARM instruction or a function call. (If the result 6976 * comes back in a register other than r0, you can override "result".) 6977 * 6978 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6979 * vCC (r1). Useful for integer division and modulus. 6980 * 6981 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6982 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6983 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6984 */ 6985 /* binop/lit8 vAA, vBB, #+CC */ 6986 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6987 mov r9, rINST, lsr #8 @ r9<- AA 6988 and r2, r3, #255 @ r2<- BB 6989 GET_VREG(r0, r2) @ r0<- vBB 6990 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6991 .if 0 6992 @cmp r1, #0 @ is second operand zero? 6993 beq common_errDivideByZero 6994 .endif 6995 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6996 6997 and r1, r1, #31 @ optional op; may set condition codes 6998 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 6999 GET_INST_OPCODE(ip) @ extract opcode from rINST 7000 SET_VREG(r0, r9) @ vAA<- r0 7001 GOTO_OPCODE(ip) @ jump to next instruction 7002 /* 10-12 instructions */ 7003 7004 7005 /* ------------------------------ */ 7006 .balign 64 7007 .L_OP_IGET_VOLATILE: /* 0xe3 */ 7008 /* File: armv5te/OP_IGET_VOLATILE.S */ 7009 /* File: armv5te/OP_IGET.S */ 7010 /* 7011 * General 32-bit instance field get. 7012 * 7013 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7014 */ 7015 /* op vA, vB, field@CCCC */ 7016 mov r0, rINST, lsr #12 @ r0<- B 7017 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7018 FETCH(r1, 1) @ r1<- field ref CCCC 7019 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7020 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7021 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7022 cmp r0, #0 @ is resolved entry null? 7023 bne .LOP_IGET_VOLATILE_finish @ no, already resolved 7024 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7025 EXPORT_PC() @ resolve() could throw 7026 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7027 bl dvmResolveInstField @ r0<- resolved InstField ptr 7028 cmp r0, #0 7029 bne .LOP_IGET_VOLATILE_finish 7030 b common_exceptionThrown 7031 7032 7033 /* ------------------------------ */ 7034 .balign 64 7035 .L_OP_IPUT_VOLATILE: /* 0xe4 */ 7036 /* File: armv5te/OP_IPUT_VOLATILE.S */ 7037 /* File: armv5te/OP_IPUT.S */ 7038 /* 7039 * General 32-bit instance field put. 7040 * 7041 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7042 */ 7043 /* op vA, vB, field@CCCC */ 7044 mov r0, rINST, lsr #12 @ r0<- B 7045 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7046 FETCH(r1, 1) @ r1<- field ref CCCC 7047 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7048 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7049 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7050 cmp r0, #0 @ is resolved entry null? 7051 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 7052 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7053 EXPORT_PC() @ resolve() could throw 7054 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7055 bl dvmResolveInstField @ r0<- resolved InstField ptr 7056 cmp r0, #0 @ success? 7057 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7058 b common_exceptionThrown 7059 7060 7061 /* ------------------------------ */ 7062 .balign 64 7063 .L_OP_SGET_VOLATILE: /* 0xe5 */ 7064 /* File: armv5te/OP_SGET_VOLATILE.S */ 7065 /* File: armv5te/OP_SGET.S */ 7066 /* 7067 * General 32-bit SGET handler. 7068 * 7069 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7070 */ 7071 /* op vAA, field@BBBB */ 7072 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7073 FETCH(r1, 1) @ r1<- field ref BBBB 7074 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 7075 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 7076 cmp r0, #0 @ is resolved entry null? 7077 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7078 .LOP_SGET_VOLATILE_finish: @ field ptr in r0 7079 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7080 SMP_DMB @ acquiring load 7081 mov r2, rINST, lsr #8 @ r2<- AA 7082 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7083 SET_VREG(r1, r2) @ fp[AA]<- r1 7084 GET_INST_OPCODE(ip) @ extract opcode from rINST 7085 GOTO_OPCODE(ip) @ jump to next instruction 7086 7087 7088 /* ------------------------------ */ 7089 .balign 64 7090 .L_OP_SPUT_VOLATILE: /* 0xe6 */ 7091 /* File: armv5te/OP_SPUT_VOLATILE.S */ 7092 /* File: armv5te/OP_SPUT.S */ 7093 /* 7094 * General 32-bit SPUT handler. 7095 * 7096 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7097 */ 7098 /* op vAA, field@BBBB */ 7099 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7100 FETCH(r1, 1) @ r1<- field ref BBBB 7101 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 7102 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 7103 cmp r0, #0 @ is resolved entry null? 7104 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7105 .LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7106 mov r2, rINST, lsr #8 @ r2<- AA 7107 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7108 GET_VREG(r1, r2) @ r1<- fp[AA] 7109 GET_INST_OPCODE(ip) @ extract opcode from rINST 7110 SMP_DMB_ST @ releasing store 7111 str r1, [r0, #offStaticField_value] @ field<- vAA 7112 SMP_DMB 7113 GOTO_OPCODE(ip) @ jump to next instruction 7114 7115 7116 /* ------------------------------ */ 7117 .balign 64 7118 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7119 /* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7120 /* File: armv5te/OP_IGET.S */ 7121 /* 7122 * General 32-bit instance field get. 7123 * 7124 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7125 */ 7126 /* op vA, vB, field@CCCC */ 7127 mov r0, rINST, lsr #12 @ r0<- B 7128 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7129 FETCH(r1, 1) @ r1<- field ref CCCC 7130 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7131 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7132 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7133 cmp r0, #0 @ is resolved entry null? 7134 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 7135 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7136 EXPORT_PC() @ resolve() could throw 7137 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7138 bl dvmResolveInstField @ r0<- resolved InstField ptr 7139 cmp r0, #0 7140 bne .LOP_IGET_OBJECT_VOLATILE_finish 7141 b common_exceptionThrown 7142 7143 7144 /* ------------------------------ */ 7145 .balign 64 7146 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 7147 /* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 7148 /* File: armv5te/OP_IGET_WIDE.S */ 7149 /* 7150 * Wide 32-bit instance field get. 7151 */ 7152 /* iget-wide vA, vB, field@CCCC */ 7153 mov r0, rINST, lsr #12 @ r0<- B 7154 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7155 FETCH(r1, 1) @ r1<- field ref CCCC 7156 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7157 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7158 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7159 cmp r0, #0 @ is resolved entry null? 7160 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 7161 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7162 EXPORT_PC() @ resolve() could throw 7163 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7164 bl dvmResolveInstField @ r0<- resolved InstField ptr 7165 cmp r0, #0 7166 bne .LOP_IGET_WIDE_VOLATILE_finish 7167 b common_exceptionThrown 7168 7169 7170 /* ------------------------------ */ 7171 .balign 64 7172 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 7173 /* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 7174 /* File: armv5te/OP_IPUT_WIDE.S */ 7175 /* iput-wide vA, vB, field@CCCC */ 7176 mov r0, rINST, lsr #12 @ r0<- B 7177 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7178 FETCH(r1, 1) @ r1<- field ref CCCC 7179 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7180 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7181 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7182 cmp r0, #0 @ is resolved entry null? 7183 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 7184 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7185 EXPORT_PC() @ resolve() could throw 7186 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7187 bl dvmResolveInstField @ r0<- resolved InstField ptr 7188 cmp r0, #0 @ success? 7189 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 7190 b common_exceptionThrown 7191 7192 7193 /* ------------------------------ */ 7194 .balign 64 7195 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 7196 /* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 7197 /* File: armv5te/OP_SGET_WIDE.S */ 7198 /* 7199 * 64-bit SGET handler. 7200 */ 7201 /* sget-wide vAA, field@BBBB */ 7202 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7203 FETCH(r1, 1) @ r1<- field ref BBBB 7204 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 7205 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 7206 cmp r0, #0 @ is resolved entry null? 7207 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 7208 .LOP_SGET_WIDE_VOLATILE_finish: 7209 mov r9, rINST, lsr #8 @ r9<- AA 7210 .if 1 7211 add r0, r0, #offStaticField_value @ r0<- pointer to data 7212 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7213 .else 7214 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7215 .endif 7216 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7217 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7218 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 7219 GET_INST_OPCODE(ip) @ extract opcode from rINST 7220 GOTO_OPCODE(ip) @ jump to next instruction 7221 7222 7223 /* ------------------------------ */ 7224 .balign 64 7225 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 7226 /* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 7227 /* File: armv5te/OP_SPUT_WIDE.S */ 7228 /* 7229 * 64-bit SPUT handler. 7230 */ 7231 /* sput-wide vAA, field@BBBB */ 7232 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 7233 FETCH(r1, 1) @ r1<- field ref BBBB 7234 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 7235 mov r9, rINST, lsr #8 @ r9<- AA 7236 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr 7237 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7238 cmp r2, #0 @ is resolved entry null? 7239 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7240 .LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 7241 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7242 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7243 GET_INST_OPCODE(r10) @ extract opcode from rINST 7244 .if 1 7245 add r2, r2, #offStaticField_value @ r2<- pointer to data 7246 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 7247 .else 7248 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7249 .endif 7250 GOTO_OPCODE(r10) @ jump to next instruction 7251 7252 7253 /* ------------------------------ */ 7254 .balign 64 7255 .L_OP_BREAKPOINT: /* 0xec */ 7256 /* File: armv5te/OP_BREAKPOINT.S */ 7257 /* 7258 * Breakpoint handler. 7259 * 7260 * Restart this instruction with the original opcode. By 7261 * the time we get here, the breakpoint will have already been 7262 * handled. 7263 */ 7264 mov r0, rPC 7265 bl dvmGetOriginalOpcode @ (rPC) 7266 FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst 7267 ldr r1, [rSELF, #offThread_mainHandlerTable] 7268 and rINST, #0xff00 7269 orr rINST, rINST, r0 7270 GOTO_OPCODE_BASE(r1, r0) 7271 7272 /* ------------------------------ */ 7273 .balign 64 7274 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7275 /* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7276 /* 7277 * Handle a throw-verification-error instruction. This throws an 7278 * exception for an error discovered during verification. The 7279 * exception is indicated by AA, with some detail provided by BBBB. 7280 */ 7281 /* op AA, ref@BBBB */ 7282 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 7283 FETCH(r2, 1) @ r2<- BBBB 7284 EXPORT_PC() @ export the PC 7285 mov r1, rINST, lsr #8 @ r1<- AA 7286 bl dvmThrowVerificationError @ always throws 7287 b common_exceptionThrown @ handle exception 7288 7289 /* ------------------------------ */ 7290 .balign 64 7291 .L_OP_EXECUTE_INLINE: /* 0xee */ 7292 /* File: armv5te/OP_EXECUTE_INLINE.S */ 7293 /* 7294 * Execute a "native inline" instruction. 7295 * 7296 * We need to call an InlineOp4Func: 7297 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7298 * 7299 * The first four args are in r0-r3, pointer to return value storage 7300 * is on the stack. The function's return value is a flag that tells 7301 * us if an exception was thrown. 7302 * 7303 * TUNING: could maintain two tables, pointer in Thread and 7304 * swap if profiler/debuggger active. 7305 */ 7306 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7307 ldrh r2, [rSELF, #offThread_subMode] 7308 FETCH(r10, 1) @ r10<- BBBB 7309 EXPORT_PC() @ can throw 7310 ands r2, #kSubModeDebugProfile @ Any going on? 7311 bne .LOP_EXECUTE_INLINE_debugmode @ yes - take slow path 7312 .LOP_EXECUTE_INLINE_resume: 7313 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7314 sub sp, sp, #8 @ make room for arg, +64 bit align 7315 mov r0, rINST, lsr #12 @ r0<- B 7316 str r1, [sp] @ push &self->retval 7317 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7318 add sp, sp, #8 @ pop stack 7319 cmp r0, #0 @ test boolean result of inline 7320 beq common_exceptionThrown @ returned false, handle exception 7321 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7322 GET_INST_OPCODE(ip) @ extract opcode from rINST 7323 GOTO_OPCODE(ip) @ jump to next instruction 7324 7325 /* ------------------------------ */ 7326 .balign 64 7327 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7328 /* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7329 /* 7330 * Execute a "native inline" instruction, using "/range" semantics. 7331 * Same idea as execute-inline, but we get the args differently. 7332 * 7333 * We need to call an InlineOp4Func: 7334 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7335 * 7336 * The first four args are in r0-r3, pointer to return value storage 7337 * is on the stack. The function's return value is a flag that tells 7338 * us if an exception was thrown. 7339 */ 7340 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7341 ldrh r2, [rSELF, #offThread_subMode] 7342 FETCH(r10, 1) @ r10<- BBBB 7343 EXPORT_PC() @ can throw 7344 ands r2, #kSubModeDebugProfile @ Any going on? 7345 bne .LOP_EXECUTE_INLINE_RANGE_debugmode @ yes - take slow path 7346 .LOP_EXECUTE_INLINE_RANGE_resume: 7347 add r1, rSELF, #offThread_retval @ r1<- &self->retval 7348 sub sp, sp, #8 @ make room for arg, +64 bit align 7349 mov r0, rINST, lsr #8 @ r0<- AA 7350 str r1, [sp] @ push &self->retval 7351 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7352 add sp, sp, #8 @ pop stack 7353 cmp r0, #0 @ test boolean result of inline 7354 beq common_exceptionThrown @ returned false, handle exception 7355 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7356 GET_INST_OPCODE(ip) @ extract opcode from rINST 7357 GOTO_OPCODE(ip) @ jump to next instruction 7358 7359 /* ------------------------------ */ 7360 .balign 64 7361 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 7362 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 7363 /* 7364 * Invoke Object.<init> on an object. In practice we know that 7365 * Object's nullary constructor doesn't do anything, so we just 7366 * skip it unless a debugger is active. 7367 */ 7368 FETCH(r1, 2) @ r1<- CCCC 7369 GET_VREG(r0, r1) @ r0<- "this" ptr 7370 cmp r0, #0 @ check for NULL 7371 beq common_errNullObject @ export PC and throw NPE 7372 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 7373 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 7374 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 7375 bne .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal @ yes, go 7376 .LOP_INVOKE_OBJECT_INIT_RANGE_finish: 7377 ldrh r1, [rSELF, #offThread_subMode] 7378 ands r1, #kSubModeDebuggerActive @ debugger active? 7379 bne .LOP_INVOKE_OBJECT_INIT_RANGE_debugger @ Yes - skip optimization 7380 FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST 7381 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7382 GOTO_OPCODE(ip) @ execute it 7383 7384 /* ------------------------------ */ 7385 .balign 64 7386 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 7387 /* File: armv5te/OP_RETURN_VOID_BARRIER.S */ 7388 SMP_DMB_ST 7389 b common_returnFromMethod 7390 7391 /* ------------------------------ */ 7392 .balign 64 7393 .L_OP_IGET_QUICK: /* 0xf2 */ 7394 /* File: armv5te/OP_IGET_QUICK.S */ 7395 /* For: iget-quick, iget-object-quick */ 7396 /* op vA, vB, offset@CCCC */ 7397 mov r2, rINST, lsr #12 @ r2<- B 7398 GET_VREG(r3, r2) @ r3<- object we're operating on 7399 FETCH(r1, 1) @ r1<- field byte offset 7400 cmp r3, #0 @ check object for null 7401 mov r2, rINST, lsr #8 @ r2<- A(+) 7402 beq common_errNullObject @ object was null 7403 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7404 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7405 and r2, r2, #15 7406 GET_INST_OPCODE(ip) @ extract opcode from rINST 7407 SET_VREG(r0, r2) @ fp[A]<- r0 7408 GOTO_OPCODE(ip) @ jump to next instruction 7409 7410 /* ------------------------------ */ 7411 .balign 64 7412 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7413 /* File: armv5te/OP_IGET_WIDE_QUICK.S */ 7414 /* iget-wide-quick vA, vB, offset@CCCC */ 7415 mov r2, rINST, lsr #12 @ r2<- B 7416 GET_VREG(r3, r2) @ r3<- object we're operating on 7417 FETCH(ip, 1) @ ip<- field byte offset 7418 cmp r3, #0 @ check object for null 7419 mov r2, rINST, lsr #8 @ r2<- A(+) 7420 beq common_errNullObject @ object was null 7421 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7422 and r2, r2, #15 7423 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7424 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7425 GET_INST_OPCODE(ip) @ extract opcode from rINST 7426 stmia r3, {r0-r1} @ fp[A]<- r0/r1 7427 GOTO_OPCODE(ip) @ jump to next instruction 7428 7429 /* ------------------------------ */ 7430 .balign 64 7431 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7432 /* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7433 /* File: armv5te/OP_IGET_QUICK.S */ 7434 /* For: iget-quick, iget-object-quick */ 7435 /* op vA, vB, offset@CCCC */ 7436 mov r2, rINST, lsr #12 @ r2<- B 7437 GET_VREG(r3, r2) @ r3<- object we're operating on 7438 FETCH(r1, 1) @ r1<- field byte offset 7439 cmp r3, #0 @ check object for null 7440 mov r2, rINST, lsr #8 @ r2<- A(+) 7441 beq common_errNullObject @ object was null 7442 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7443 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7444 and r2, r2, #15 7445 GET_INST_OPCODE(ip) @ extract opcode from rINST 7446 SET_VREG(r0, r2) @ fp[A]<- r0 7447 GOTO_OPCODE(ip) @ jump to next instruction 7448 7449 7450 /* ------------------------------ */ 7451 .balign 64 7452 .L_OP_IPUT_QUICK: /* 0xf5 */ 7453 /* File: armv5te/OP_IPUT_QUICK.S */ 7454 /* For: iput-quick */ 7455 /* op vA, vB, offset@CCCC */ 7456 mov r2, rINST, lsr #12 @ r2<- B 7457 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7458 FETCH(r1, 1) @ r1<- field byte offset 7459 cmp r3, #0 @ check object for null 7460 mov r2, rINST, lsr #8 @ r2<- A(+) 7461 beq common_errNullObject @ object was null 7462 and r2, r2, #15 7463 GET_VREG(r0, r2) @ r0<- fp[A] 7464 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7465 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7466 GET_INST_OPCODE(ip) @ extract opcode from rINST 7467 GOTO_OPCODE(ip) @ jump to next instruction 7468 7469 /* ------------------------------ */ 7470 .balign 64 7471 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7472 /* File: armv5te/OP_IPUT_WIDE_QUICK.S */ 7473 /* iput-wide-quick vA, vB, offset@CCCC */ 7474 mov r0, rINST, lsr #8 @ r0<- A(+) 7475 mov r1, rINST, lsr #12 @ r1<- B 7476 and r0, r0, #15 7477 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7478 add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7479 cmp r2, #0 @ check object for null 7480 ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7481 beq common_errNullObject @ object was null 7482 FETCH(r3, 1) @ r3<- field byte offset 7483 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7484 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7485 GET_INST_OPCODE(ip) @ extract opcode from rINST 7486 GOTO_OPCODE(ip) @ jump to next instruction 7487 7488 /* ------------------------------ */ 7489 .balign 64 7490 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7491 /* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7492 /* For: iput-object-quick */ 7493 /* op vA, vB, offset@CCCC */ 7494 mov r2, rINST, lsr #12 @ r2<- B 7495 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7496 FETCH(r1, 1) @ r1<- field byte offset 7497 cmp r3, #0 @ check object for null 7498 mov r2, rINST, lsr #8 @ r2<- A(+) 7499 beq common_errNullObject @ object was null 7500 and r2, r2, #15 7501 GET_VREG(r0, r2) @ r0<- fp[A] 7502 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7503 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7504 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7505 cmp r0, #0 7506 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7507 GET_INST_OPCODE(ip) @ extract opcode from rINST 7508 GOTO_OPCODE(ip) @ jump to next instruction 7509 7510 /* ------------------------------ */ 7511 .balign 64 7512 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7513 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7514 /* 7515 * Handle an optimized virtual method call. 7516 * 7517 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7518 */ 7519 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7520 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7521 FETCH(r3, 2) @ r3<- FEDC or CCCC 7522 FETCH(r1, 1) @ r1<- BBBB 7523 .if (!0) 7524 and r3, r3, #15 @ r3<- C (or stays CCCC) 7525 .endif 7526 GET_VREG(r9, r3) @ r9<- vC ("this" ptr) 7527 cmp r9, #0 @ is "this" null? 7528 beq common_errNullObject @ null "this", throw exception 7529 ldr r2, [r9, #offObject_clazz] @ r2<- thisPtr->clazz 7530 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7531 EXPORT_PC() @ invoke must export 7532 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7533 bl common_invokeMethodNoRange @ (r0=method, r9="this") 7534 7535 /* ------------------------------ */ 7536 .balign 64 7537 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7538 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7539 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7540 /* 7541 * Handle an optimized virtual method call. 7542 * 7543 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7544 */ 7545 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7546 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7547 FETCH(r3, 2) @ r3<- FEDC or CCCC 7548 FETCH(r1, 1) @ r1<- BBBB 7549 .if (!1) 7550 and r3, r3, #15 @ r3<- C (or stays CCCC) 7551 .endif 7552 GET_VREG(r9, r3) @ r9<- vC ("this" ptr) 7553 cmp r9, #0 @ is "this" null? 7554 beq common_errNullObject @ null "this", throw exception 7555 ldr r2, [r9, #offObject_clazz] @ r2<- thisPtr->clazz 7556 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7557 EXPORT_PC() @ invoke must export 7558 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7559 bl common_invokeMethodRange @ (r0=method, r9="this") 7560 7561 7562 /* ------------------------------ */ 7563 .balign 64 7564 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7565 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7566 /* 7567 * Handle an optimized "super" method call. 7568 * 7569 * for: [opt] invoke-super-quick, invoke-super-quick/range 7570 */ 7571 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7572 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7573 FETCH(r10, 2) @ r10<- GFED or CCCC 7574 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7575 .if (!0) 7576 and r10, r10, #15 @ r10<- D (or stays CCCC) 7577 .endif 7578 FETCH(r1, 1) @ r1<- BBBB 7579 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7580 EXPORT_PC() @ must export for invoke 7581 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7582 GET_VREG(r9, r10) @ r9<- "this" 7583 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7584 cmp r9, #0 @ null "this" ref? 7585 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7586 beq common_errNullObject @ "this" is null, throw exception 7587 bl common_invokeMethodNoRange @ (r0=method, r9="this") 7588 7589 /* ------------------------------ */ 7590 .balign 64 7591 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7592 /* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7593 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7594 /* 7595 * Handle an optimized "super" method call. 7596 * 7597 * for: [opt] invoke-super-quick, invoke-super-quick/range 7598 */ 7599 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7600 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7601 FETCH(r10, 2) @ r10<- GFED or CCCC 7602 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7603 .if (!1) 7604 and r10, r10, #15 @ r10<- D (or stays CCCC) 7605 .endif 7606 FETCH(r1, 1) @ r1<- BBBB 7607 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7608 EXPORT_PC() @ must export for invoke 7609 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7610 GET_VREG(r9, r10) @ r9<- "this" 7611 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7612 cmp r9, #0 @ null "this" ref? 7613 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7614 beq common_errNullObject @ "this" is null, throw exception 7615 bl common_invokeMethodRange @ (r0=method, r9="this") 7616 7617 7618 /* ------------------------------ */ 7619 .balign 64 7620 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7621 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7622 /* File: armv5te/OP_IPUT_OBJECT.S */ 7623 /* 7624 * 32-bit instance field put. 7625 * 7626 * for: iput-object, iput-object-volatile 7627 */ 7628 /* op vA, vB, field@CCCC */ 7629 mov r0, rINST, lsr #12 @ r0<- B 7630 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7631 FETCH(r1, 1) @ r1<- field ref CCCC 7632 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7633 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7634 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7635 cmp r0, #0 @ is resolved entry null? 7636 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 7637 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7638 EXPORT_PC() @ resolve() could throw 7639 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7640 bl dvmResolveInstField @ r0<- resolved InstField ptr 7641 cmp r0, #0 @ success? 7642 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7643 b common_exceptionThrown 7644 7645 7646 /* ------------------------------ */ 7647 .balign 64 7648 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7649 /* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7650 /* File: armv5te/OP_SGET.S */ 7651 /* 7652 * General 32-bit SGET handler. 7653 * 7654 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7655 */ 7656 /* op vAA, field@BBBB */ 7657 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7658 FETCH(r1, 1) @ r1<- field ref BBBB 7659 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 7660 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 7661 cmp r0, #0 @ is resolved entry null? 7662 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7663 .LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7664 ldr r1, [r0, #offStaticField_value] @ r1<- field value 7665 SMP_DMB @ acquiring load 7666 mov r2, rINST, lsr #8 @ r2<- AA 7667 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7668 SET_VREG(r1, r2) @ fp[AA]<- r1 7669 GET_INST_OPCODE(ip) @ extract opcode from rINST 7670 GOTO_OPCODE(ip) @ jump to next instruction 7671 7672 7673 /* ------------------------------ */ 7674 .balign 64 7675 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7676 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7677 /* File: armv5te/OP_SPUT_OBJECT.S */ 7678 /* 7679 * 32-bit SPUT handler for objects 7680 * 7681 * for: sput-object, sput-object-volatile 7682 */ 7683 /* op vAA, field@BBBB */ 7684 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 7685 FETCH(r1, 1) @ r1<- field ref BBBB 7686 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 7687 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 7688 cmp r0, #0 @ is resolved entry null? 7689 beq .LOP_SPUT_OBJECT_VOLATILE_resolve @ yes, do resolve 7690 .LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 7691 mov r2, rINST, lsr #8 @ r2<- AA 7692 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7693 GET_VREG(r1, r2) @ r1<- fp[AA] 7694 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 7695 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 7696 GET_INST_OPCODE(ip) @ extract opcode from rINST 7697 SMP_DMB_ST @ releasing store 7698 b .LOP_SPUT_OBJECT_VOLATILE_end 7699 7700 7701 /* ------------------------------ */ 7702 .balign 64 7703 .L_OP_DISPATCH_FF: /* 0xff */ 7704 /* File: armv5te/OP_DISPATCH_FF.S */ 7705 mov ip, rINST, lsr #8 @ ip<- extended opcode 7706 add ip, ip, #256 @ add offset for extended opcodes 7707 GOTO_OPCODE(ip) @ go to proper extended handler 7708 7709 7710 /* ------------------------------ */ 7711 .balign 64 7712 .L_OP_CONST_CLASS_JUMBO: /* 0x100 */ 7713 /* File: armv5te/OP_CONST_CLASS_JUMBO.S */ 7714 /* const-class/jumbo vBBBB, Class@AAAAAAAA */ 7715 FETCH(r0, 1) @ r0<- aaaa (lo) 7716 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex 7717 FETCH(r1, 2) @ r1<- AAAA (hi) 7718 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 7719 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7720 FETCH(r9, 3) @ r9<- BBBB 7721 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa] 7722 cmp r0, #0 @ not yet resolved? 7723 beq .LOP_CONST_CLASS_JUMBO_resolve 7724 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 7725 GET_INST_OPCODE(ip) @ extract opcode from rINST 7726 SET_VREG(r0, r9) @ vBBBB<- r0 7727 GOTO_OPCODE(ip) @ jump to next instruction 7728 7729 /* ------------------------------ */ 7730 .balign 64 7731 .L_OP_CHECK_CAST_JUMBO: /* 0x101 */ 7732 /* File: armv5te/OP_CHECK_CAST_JUMBO.S */ 7733 /* 7734 * Check to see if a cast from one class to another is allowed. 7735 */ 7736 /* check-cast/jumbo vBBBB, class@AAAAAAAA */ 7737 FETCH(r0, 1) @ r0<- aaaa (lo) 7738 FETCH(r2, 2) @ r2<- AAAA (hi) 7739 FETCH(r3, 3) @ r3<- BBBB 7740 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa 7741 GET_VREG(r9, r3) @ r9<- object 7742 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex 7743 cmp r9, #0 @ is object null? 7744 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 7745 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds 7746 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 7747 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7748 cmp r1, #0 @ have we resolved this before? 7749 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now 7750 .LOP_CHECK_CAST_JUMBO_resolved: 7751 cmp r0, r1 @ same class (trivial success)? 7752 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check 7753 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up 7754 7755 /* ------------------------------ */ 7756 .balign 64 7757 .L_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 7758 /* File: armv5te/OP_INSTANCE_OF_JUMBO.S */ 7759 /* 7760 * Check to see if an object reference is an instance of a class. 7761 * 7762 * Most common situation is a non-null object, being compared against 7763 * an already-resolved class. 7764 * 7765 * TODO: convert most of this into a common subroutine, shared with 7766 * OP_INSTANCE_OF.S. 7767 */ 7768 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7769 FETCH(r3, 4) @ r3<- vCCCC 7770 FETCH(r9, 3) @ r9<- vBBBB 7771 GET_VREG(r0, r3) @ r0<- vCCCC (object) 7772 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex 7773 cmp r0, #0 @ is object null? 7774 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0 7775 FETCH(r1, 1) @ r1<- aaaa (lo) 7776 FETCH(r3, 2) @ r3<- AAAA (hi) 7777 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 7778 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa 7779 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 7780 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7781 cmp r1, #0 @ have we resolved this before? 7782 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now 7783 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue 7784 7785 /* ------------------------------ */ 7786 .balign 64 7787 .L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 7788 /* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */ 7789 /* 7790 * Create a new instance of a class. 7791 */ 7792 /* new-instance/jumbo vBBBB, class@AAAAAAAA */ 7793 FETCH(r0, 1) @ r0<- aaaa (lo) 7794 FETCH(r1, 2) @ r1<- AAAA (hi) 7795 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7796 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7797 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7798 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7799 #if defined(WITH_JIT) 7800 add r10, r3, r1, lsl #2 @ r10<- &resolved_class 7801 #endif 7802 EXPORT_PC() @ req'd for init, resolve, alloc 7803 cmp r0, #0 @ already resolved? 7804 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now 7805 .LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class 7806 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 7807 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 7808 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now 7809 .LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class 7810 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 7811 bl dvmAllocObject @ r0<- new object 7812 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue 7813 7814 /* ------------------------------ */ 7815 .balign 64 7816 .L_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 7817 /* File: armv5te/OP_NEW_ARRAY_JUMBO.S */ 7818 /* 7819 * Allocate an array of objects, specified with the array class 7820 * and a count. 7821 * 7822 * The verifier guarantees that this is an array class, so we don't 7823 * check for it here. 7824 */ 7825 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */ 7826 FETCH(r2, 1) @ r2<- aaaa (lo) 7827 FETCH(r3, 2) @ r3<- AAAA (hi) 7828 FETCH(r0, 4) @ r0<- vCCCC 7829 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa 7830 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7831 GET_VREG(r1, r0) @ r1<- vCCCC (array length) 7832 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7833 cmp r1, #0 @ check length 7834 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 7835 bmi common_errNegativeArraySize @ negative length, bail - len in r1 7836 cmp r0, #0 @ already resolved? 7837 EXPORT_PC() @ req'd for resolve, alloc 7838 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue 7839 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now 7840 7841 /* ------------------------------ */ 7842 .balign 64 7843 .L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 7844 /* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */ 7845 /* 7846 * Create a new array with elements filled from registers. 7847 * 7848 * TODO: convert most of this into a common subroutine, shared with 7849 * OP_FILLED_NEW_ARRAY.S. 7850 */ 7851 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */ 7852 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 7853 FETCH(r0, 1) @ r0<- aaaa (lo) 7854 FETCH(r1, 2) @ r1<- AAAA (hi) 7855 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 7856 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 7857 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 7858 EXPORT_PC() @ need for resolve and alloc 7859 cmp r0, #0 @ already resolved? 7860 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on 7861 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method 7862 mov r2, #0 @ r2<- false 7863 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7864 bl dvmResolveClass @ r0<- call(clazz, ref) 7865 cmp r0, #0 @ got null? 7866 beq common_exceptionThrown @ yes, handle exception 7867 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue 7868 7869 /* ------------------------------ */ 7870 .balign 64 7871 .L_OP_IGET_JUMBO: /* 0x106 */ 7872 /* File: armv5te/OP_IGET_JUMBO.S */ 7873 /* 7874 * Jumbo 32-bit instance field get. 7875 * 7876 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7877 * iget-char/jumbo, iget-short/jumbo 7878 */ 7879 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7880 FETCH(r1, 1) @ r1<- aaaa (lo) 7881 FETCH(r2, 2) @ r2<- AAAA (hi) 7882 FETCH(r0, 4) @ r0<- CCCC 7883 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7884 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7885 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7886 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7887 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7888 cmp r0, #0 @ is resolved entry null? 7889 bne .LOP_IGET_JUMBO_finish @ no, already resolved 7890 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7891 EXPORT_PC() @ resolve() could throw 7892 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7893 bl dvmResolveInstField @ r0<- resolved InstField ptr 7894 b .LOP_IGET_JUMBO_resolved @ resolved, continue 7895 7896 /* ------------------------------ */ 7897 .balign 64 7898 .L_OP_IGET_WIDE_JUMBO: /* 0x107 */ 7899 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 7900 /* 7901 * Jumbo 64-bit instance field get. 7902 */ 7903 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 7904 FETCH(r1, 1) @ r1<- aaaa (lo) 7905 FETCH(r2, 2) @ r2<- AAAA (hi) 7906 FETCH(r0, 4) @ r0<- CCCC 7907 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7908 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7909 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 7910 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7911 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7912 cmp r0, #0 @ is resolved entry null? 7913 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved 7914 ldr r2, [rSELF, #offThread_method] @ r2<- current method 7915 EXPORT_PC() @ resolve() could throw 7916 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7917 bl dvmResolveInstField @ r0<- resolved InstField ptr 7918 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue 7919 7920 /* ------------------------------ */ 7921 .balign 64 7922 .L_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 7923 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 7924 /* File: armv5te/OP_IGET_JUMBO.S */ 7925 /* 7926 * Jumbo 32-bit instance field get. 7927 * 7928 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7929 * iget-char/jumbo, iget-short/jumbo 7930 */ 7931 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7932 FETCH(r1, 1) @ r1<- aaaa (lo) 7933 FETCH(r2, 2) @ r2<- AAAA (hi) 7934 FETCH(r0, 4) @ r0<- CCCC 7935 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7936 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7937 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7938 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7939 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7940 cmp r0, #0 @ is resolved entry null? 7941 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved 7942 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7943 EXPORT_PC() @ resolve() could throw 7944 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7945 bl dvmResolveInstField @ r0<- resolved InstField ptr 7946 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue 7947 7948 7949 /* ------------------------------ */ 7950 .balign 64 7951 .L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 7952 /* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */ 7953 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" } 7954 /* File: armv5te/OP_IGET_JUMBO.S */ 7955 /* 7956 * Jumbo 32-bit instance field get. 7957 * 7958 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7959 * iget-char/jumbo, iget-short/jumbo 7960 */ 7961 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7962 FETCH(r1, 1) @ r1<- aaaa (lo) 7963 FETCH(r2, 2) @ r2<- AAAA (hi) 7964 FETCH(r0, 4) @ r0<- CCCC 7965 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7966 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7967 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7968 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7969 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7970 cmp r0, #0 @ is resolved entry null? 7971 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved 7972 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 7973 EXPORT_PC() @ resolve() could throw 7974 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7975 bl dvmResolveInstField @ r0<- resolved InstField ptr 7976 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue 7977 7978 7979 /* ------------------------------ */ 7980 .balign 64 7981 .L_OP_IGET_BYTE_JUMBO: /* 0x10a */ 7982 /* File: armv5te/OP_IGET_BYTE_JUMBO.S */ 7983 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" } 7984 /* File: armv5te/OP_IGET_JUMBO.S */ 7985 /* 7986 * Jumbo 32-bit instance field get. 7987 * 7988 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 7989 * iget-char/jumbo, iget-short/jumbo 7990 */ 7991 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 7992 FETCH(r1, 1) @ r1<- aaaa (lo) 7993 FETCH(r2, 2) @ r2<- AAAA (hi) 7994 FETCH(r0, 4) @ r0<- CCCC 7995 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 7996 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 7997 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7998 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 7999 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8000 cmp r0, #0 @ is resolved entry null? 8001 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved 8002 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8003 EXPORT_PC() @ resolve() could throw 8004 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8005 bl dvmResolveInstField @ r0<- resolved InstField ptr 8006 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue 8007 8008 8009 /* ------------------------------ */ 8010 .balign 64 8011 .L_OP_IGET_CHAR_JUMBO: /* 0x10b */ 8012 /* File: armv5te/OP_IGET_CHAR_JUMBO.S */ 8013 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" } 8014 /* File: armv5te/OP_IGET_JUMBO.S */ 8015 /* 8016 * Jumbo 32-bit instance field get. 8017 * 8018 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8019 * iget-char/jumbo, iget-short/jumbo 8020 */ 8021 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8022 FETCH(r1, 1) @ r1<- aaaa (lo) 8023 FETCH(r2, 2) @ r2<- AAAA (hi) 8024 FETCH(r0, 4) @ r0<- CCCC 8025 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8026 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8027 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8028 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8029 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8030 cmp r0, #0 @ is resolved entry null? 8031 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved 8032 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8033 EXPORT_PC() @ resolve() could throw 8034 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8035 bl dvmResolveInstField @ r0<- resolved InstField ptr 8036 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue 8037 8038 8039 /* ------------------------------ */ 8040 .balign 64 8041 .L_OP_IGET_SHORT_JUMBO: /* 0x10c */ 8042 /* File: armv5te/OP_IGET_SHORT_JUMBO.S */ 8043 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" } 8044 /* File: armv5te/OP_IGET_JUMBO.S */ 8045 /* 8046 * Jumbo 32-bit instance field get. 8047 * 8048 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 8049 * iget-char/jumbo, iget-short/jumbo 8050 */ 8051 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8052 FETCH(r1, 1) @ r1<- aaaa (lo) 8053 FETCH(r2, 2) @ r2<- AAAA (hi) 8054 FETCH(r0, 4) @ r0<- CCCC 8055 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8056 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8057 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8058 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8059 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8060 cmp r0, #0 @ is resolved entry null? 8061 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved 8062 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8063 EXPORT_PC() @ resolve() could throw 8064 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8065 bl dvmResolveInstField @ r0<- resolved InstField ptr 8066 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue 8067 8068 8069 /* ------------------------------ */ 8070 .balign 64 8071 .L_OP_IPUT_JUMBO: /* 0x10d */ 8072 /* File: armv5te/OP_IPUT_JUMBO.S */ 8073 /* 8074 * Jumbo 32-bit instance field put. 8075 * 8076 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8077 * iput-short/jumbo 8078 */ 8079 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8080 FETCH(r1, 1) @ r1<- aaaa (lo) 8081 FETCH(r2, 2) @ r2<- AAAA (hi) 8082 FETCH(r0, 4) @ r0<- CCCC 8083 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8084 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8085 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8086 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8087 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8088 cmp r0, #0 @ is resolved entry null? 8089 bne .LOP_IPUT_JUMBO_finish @ no, already resolved 8090 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8091 EXPORT_PC() @ resolve() could throw 8092 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8093 bl dvmResolveInstField @ r0<- resolved InstField ptr 8094 b .LOP_IPUT_JUMBO_resolved @ resolved, continue 8095 8096 /* ------------------------------ */ 8097 .balign 64 8098 .L_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 8099 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 8100 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8101 FETCH(r1, 1) @ r1<- aaaa (lo) 8102 FETCH(r2, 2) @ r2<- AAAA (hi) 8103 FETCH(r0, 4) @ r0<- CCCC 8104 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8105 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8106 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 8107 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 8108 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8109 cmp r0, #0 @ is resolved entry null? 8110 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved 8111 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8112 EXPORT_PC() @ resolve() could throw 8113 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8114 bl dvmResolveInstField @ r0<- resolved InstField ptr 8115 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue 8116 8117 /* ------------------------------ */ 8118 .balign 64 8119 .L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 8120 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 8121 /* 8122 * Jumbo 32-bit instance field put. 8123 */ 8124 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 8125 FETCH(r1, 1) @ r1<- aaaa (lo) 8126 FETCH(r2, 2) @ r2<- AAAA (hi) 8127 FETCH(r0, 4) @ r0<- CCCC 8128 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8129 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8130 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8131 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8132 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8133 cmp r0, #0 @ is resolved entry null? 8134 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved 8135 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8136 EXPORT_PC() @ resolve() could throw 8137 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8138 bl dvmResolveInstField @ r0<- resolved InstField ptr 8139 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue 8140 8141 /* ------------------------------ */ 8142 .balign 64 8143 .L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 8144 /* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */ 8145 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" } 8146 /* File: armv5te/OP_IPUT_JUMBO.S */ 8147 /* 8148 * Jumbo 32-bit instance field put. 8149 * 8150 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8151 * iput-short/jumbo 8152 */ 8153 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8154 FETCH(r1, 1) @ r1<- aaaa (lo) 8155 FETCH(r2, 2) @ r2<- AAAA (hi) 8156 FETCH(r0, 4) @ r0<- CCCC 8157 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8158 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8159 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8160 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8161 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8162 cmp r0, #0 @ is resolved entry null? 8163 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved 8164 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8165 EXPORT_PC() @ resolve() could throw 8166 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8167 bl dvmResolveInstField @ r0<- resolved InstField ptr 8168 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue 8169 8170 8171 /* ------------------------------ */ 8172 .balign 64 8173 .L_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 8174 /* File: armv5te/OP_IPUT_BYTE_JUMBO.S */ 8175 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" } 8176 /* File: armv5te/OP_IPUT_JUMBO.S */ 8177 /* 8178 * Jumbo 32-bit instance field put. 8179 * 8180 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8181 * iput-short/jumbo 8182 */ 8183 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8184 FETCH(r1, 1) @ r1<- aaaa (lo) 8185 FETCH(r2, 2) @ r2<- AAAA (hi) 8186 FETCH(r0, 4) @ r0<- CCCC 8187 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8188 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8189 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8190 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8191 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8192 cmp r0, #0 @ is resolved entry null? 8193 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved 8194 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8195 EXPORT_PC() @ resolve() could throw 8196 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8197 bl dvmResolveInstField @ r0<- resolved InstField ptr 8198 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue 8199 8200 8201 /* ------------------------------ */ 8202 .balign 64 8203 .L_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 8204 /* File: armv5te/OP_IPUT_CHAR_JUMBO.S */ 8205 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" } 8206 /* File: armv5te/OP_IPUT_JUMBO.S */ 8207 /* 8208 * Jumbo 32-bit instance field put. 8209 * 8210 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8211 * iput-short/jumbo 8212 */ 8213 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8214 FETCH(r1, 1) @ r1<- aaaa (lo) 8215 FETCH(r2, 2) @ r2<- AAAA (hi) 8216 FETCH(r0, 4) @ r0<- CCCC 8217 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8218 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8219 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8220 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8221 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8222 cmp r0, #0 @ is resolved entry null? 8223 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved 8224 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8225 EXPORT_PC() @ resolve() could throw 8226 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8227 bl dvmResolveInstField @ r0<- resolved InstField ptr 8228 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue 8229 8230 8231 /* ------------------------------ */ 8232 .balign 64 8233 .L_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 8234 /* File: armv5te/OP_IPUT_SHORT_JUMBO.S */ 8235 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" } 8236 /* File: armv5te/OP_IPUT_JUMBO.S */ 8237 /* 8238 * Jumbo 32-bit instance field put. 8239 * 8240 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 8241 * iput-short/jumbo 8242 */ 8243 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 8244 FETCH(r1, 1) @ r1<- aaaa (lo) 8245 FETCH(r2, 2) @ r2<- AAAA (hi) 8246 FETCH(r0, 4) @ r0<- CCCC 8247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 8248 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 8250 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 8251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 8252 cmp r0, #0 @ is resolved entry null? 8253 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved 8254 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 8255 EXPORT_PC() @ resolve() could throw 8256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8257 bl dvmResolveInstField @ r0<- resolved InstField ptr 8258 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue 8259 8260 8261 /* ------------------------------ */ 8262 .balign 64 8263 .L_OP_SGET_JUMBO: /* 0x114 */ 8264 /* File: armv5te/OP_SGET_JUMBO.S */ 8265 /* 8266 * Jumbo 32-bit SGET handler. 8267 * 8268 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8269 * sget-char/jumbo, sget-short/jumbo 8270 */ 8271 /* exop vBBBB, field@AAAAAAAA */ 8272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8273 FETCH(r0, 1) @ r0<- aaaa (lo) 8274 FETCH(r1, 2) @ r1<- AAAA (hi) 8275 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8276 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8277 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8278 cmp r0, #0 @ is resolved entry null? 8279 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve 8280 .LOP_SGET_JUMBO_finish: @ field ptr in r0 8281 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8282 @ no-op @ acquiring load 8283 FETCH(r2, 3) @ r2<- BBBB 8284 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8285 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8286 GET_INST_OPCODE(ip) @ extract opcode from rINST 8287 GOTO_OPCODE(ip) @ jump to next instruction 8288 8289 /* ------------------------------ */ 8290 .balign 64 8291 .L_OP_SGET_WIDE_JUMBO: /* 0x115 */ 8292 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 8293 /* 8294 * Jumbo 64-bit SGET handler. 8295 */ 8296 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 8297 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8298 FETCH(r0, 1) @ r0<- aaaa (lo) 8299 FETCH(r1, 2) @ r1<- AAAA (hi) 8300 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 8301 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8302 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 8303 cmp r0, #0 @ is resolved entry null? 8304 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve 8305 .LOP_SGET_WIDE_JUMBO_finish: 8306 FETCH(r9, 3) @ r9<- BBBB 8307 .if 0 8308 add r0, r0, #offStaticField_value @ r0<- pointer to data 8309 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 8310 .else 8311 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 8312 .endif 8313 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8314 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8315 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 8316 GET_INST_OPCODE(ip) @ extract opcode from rINST 8317 GOTO_OPCODE(ip) @ jump to next instruction 8318 8319 /* ------------------------------ */ 8320 .balign 64 8321 .L_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 8322 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 8323 /* File: armv5te/OP_SGET_JUMBO.S */ 8324 /* 8325 * Jumbo 32-bit SGET handler. 8326 * 8327 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8328 * sget-char/jumbo, sget-short/jumbo 8329 */ 8330 /* exop vBBBB, field@AAAAAAAA */ 8331 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8332 FETCH(r0, 1) @ r0<- aaaa (lo) 8333 FETCH(r1, 2) @ r1<- AAAA (hi) 8334 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8335 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8336 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8337 cmp r0, #0 @ is resolved entry null? 8338 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve 8339 .LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0 8340 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8341 @ no-op @ acquiring load 8342 FETCH(r2, 3) @ r2<- BBBB 8343 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8344 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8345 GET_INST_OPCODE(ip) @ extract opcode from rINST 8346 GOTO_OPCODE(ip) @ jump to next instruction 8347 8348 8349 /* ------------------------------ */ 8350 .balign 64 8351 .L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 8352 /* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */ 8353 /* File: armv5te/OP_SGET_JUMBO.S */ 8354 /* 8355 * Jumbo 32-bit SGET handler. 8356 * 8357 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8358 * sget-char/jumbo, sget-short/jumbo 8359 */ 8360 /* exop vBBBB, field@AAAAAAAA */ 8361 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8362 FETCH(r0, 1) @ r0<- aaaa (lo) 8363 FETCH(r1, 2) @ r1<- AAAA (hi) 8364 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8365 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8366 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8367 cmp r0, #0 @ is resolved entry null? 8368 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve 8369 .LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0 8370 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8371 @ no-op @ acquiring load 8372 FETCH(r2, 3) @ r2<- BBBB 8373 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8374 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8375 GET_INST_OPCODE(ip) @ extract opcode from rINST 8376 GOTO_OPCODE(ip) @ jump to next instruction 8377 8378 8379 /* ------------------------------ */ 8380 .balign 64 8381 .L_OP_SGET_BYTE_JUMBO: /* 0x118 */ 8382 /* File: armv5te/OP_SGET_BYTE_JUMBO.S */ 8383 /* File: armv5te/OP_SGET_JUMBO.S */ 8384 /* 8385 * Jumbo 32-bit SGET handler. 8386 * 8387 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8388 * sget-char/jumbo, sget-short/jumbo 8389 */ 8390 /* exop vBBBB, field@AAAAAAAA */ 8391 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8392 FETCH(r0, 1) @ r0<- aaaa (lo) 8393 FETCH(r1, 2) @ r1<- AAAA (hi) 8394 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8395 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8396 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8397 cmp r0, #0 @ is resolved entry null? 8398 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve 8399 .LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0 8400 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8401 @ no-op @ acquiring load 8402 FETCH(r2, 3) @ r2<- BBBB 8403 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8404 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8405 GET_INST_OPCODE(ip) @ extract opcode from rINST 8406 GOTO_OPCODE(ip) @ jump to next instruction 8407 8408 8409 /* ------------------------------ */ 8410 .balign 64 8411 .L_OP_SGET_CHAR_JUMBO: /* 0x119 */ 8412 /* File: armv5te/OP_SGET_CHAR_JUMBO.S */ 8413 /* File: armv5te/OP_SGET_JUMBO.S */ 8414 /* 8415 * Jumbo 32-bit SGET handler. 8416 * 8417 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8418 * sget-char/jumbo, sget-short/jumbo 8419 */ 8420 /* exop vBBBB, field@AAAAAAAA */ 8421 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8422 FETCH(r0, 1) @ r0<- aaaa (lo) 8423 FETCH(r1, 2) @ r1<- AAAA (hi) 8424 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8425 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8426 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8427 cmp r0, #0 @ is resolved entry null? 8428 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve 8429 .LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0 8430 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8431 @ no-op @ acquiring load 8432 FETCH(r2, 3) @ r2<- BBBB 8433 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8434 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8435 GET_INST_OPCODE(ip) @ extract opcode from rINST 8436 GOTO_OPCODE(ip) @ jump to next instruction 8437 8438 8439 /* ------------------------------ */ 8440 .balign 64 8441 .L_OP_SGET_SHORT_JUMBO: /* 0x11a */ 8442 /* File: armv5te/OP_SGET_SHORT_JUMBO.S */ 8443 /* File: armv5te/OP_SGET_JUMBO.S */ 8444 /* 8445 * Jumbo 32-bit SGET handler. 8446 * 8447 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 8448 * sget-char/jumbo, sget-short/jumbo 8449 */ 8450 /* exop vBBBB, field@AAAAAAAA */ 8451 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8452 FETCH(r0, 1) @ r0<- aaaa (lo) 8453 FETCH(r1, 2) @ r1<- AAAA (hi) 8454 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8455 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8456 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8457 cmp r0, #0 @ is resolved entry null? 8458 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve 8459 .LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0 8460 ldr r1, [r0, #offStaticField_value] @ r1<- field value 8461 @ no-op @ acquiring load 8462 FETCH(r2, 3) @ r2<- BBBB 8463 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8464 SET_VREG(r1, r2) @ fp[BBBB]<- r1 8465 GET_INST_OPCODE(ip) @ extract opcode from rINST 8466 GOTO_OPCODE(ip) @ jump to next instruction 8467 8468 8469 /* ------------------------------ */ 8470 .balign 64 8471 .L_OP_SPUT_JUMBO: /* 0x11b */ 8472 /* File: armv5te/OP_SPUT_JUMBO.S */ 8473 /* 8474 * Jumbo 32-bit SPUT handler. 8475 * 8476 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8477 * sput-short/jumbo 8478 */ 8479 /* exop vBBBB, field@AAAAAAAA */ 8480 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8481 FETCH(r0, 1) @ r0<- aaaa (lo) 8482 FETCH(r1, 2) @ r1<- AAAA (hi) 8483 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8484 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8485 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8486 cmp r0, #0 @ is resolved entry null? 8487 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve 8488 .LOP_SPUT_JUMBO_finish: @ field ptr in r0 8489 FETCH(r2, 3) @ r2<- BBBB 8490 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8491 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8492 GET_INST_OPCODE(ip) @ extract opcode from rINST 8493 @ no-op @ releasing store 8494 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8495 @ no-op 8496 GOTO_OPCODE(ip) @ jump to next instruction 8497 8498 /* ------------------------------ */ 8499 .balign 64 8500 .L_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 8501 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 8502 /* 8503 * Jumbo 64-bit SPUT handler. 8504 */ 8505 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 8506 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 8507 FETCH(r1, 1) @ r1<- aaaa (lo) 8508 FETCH(r2, 2) @ r2<- AAAA (hi) 8509 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8510 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 8511 FETCH(r9, 3) @ r9<- BBBB 8512 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr 8513 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 8514 cmp r2, #0 @ is resolved entry null? 8515 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve 8516 .LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9 8517 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8518 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 8519 GET_INST_OPCODE(r10) @ extract opcode from rINST 8520 .if 0 8521 add r2, r2, #offStaticField_value @ r2<- pointer to data 8522 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 8523 .else 8524 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 8525 .endif 8526 GOTO_OPCODE(r10) @ jump to next instruction 8527 8528 /* ------------------------------ */ 8529 .balign 64 8530 .L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 8531 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 8532 /* 8533 * Jumbo 32-bit SPUT handler for objects 8534 */ 8535 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 8536 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8537 FETCH(r0, 1) @ r0<- aaaa (lo) 8538 FETCH(r1, 2) @ r1<- AAAA (hi) 8539 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8540 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8541 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8542 cmp r0, #0 @ is resolved entry null? 8543 beq .LOP_SPUT_OBJECT_JUMBO_resolve @ yes, do resolve 8544 .LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0 8545 FETCH(r2, 3) @ r2<- BBBB 8546 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8547 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8548 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 8549 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 8550 GET_INST_OPCODE(ip) @ extract opcode from rINST 8551 @ no-op @ releasing store 8552 b .LOP_SPUT_OBJECT_JUMBO_end 8553 8554 /* ------------------------------ */ 8555 .balign 64 8556 .L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 8557 /* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */ 8558 /* File: armv5te/OP_SPUT_JUMBO.S */ 8559 /* 8560 * Jumbo 32-bit SPUT handler. 8561 * 8562 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8563 * sput-short/jumbo 8564 */ 8565 /* exop vBBBB, field@AAAAAAAA */ 8566 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8567 FETCH(r0, 1) @ r0<- aaaa (lo) 8568 FETCH(r1, 2) @ r1<- AAAA (hi) 8569 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8570 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8571 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8572 cmp r0, #0 @ is resolved entry null? 8573 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve 8574 .LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0 8575 FETCH(r2, 3) @ r2<- BBBB 8576 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8577 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8578 GET_INST_OPCODE(ip) @ extract opcode from rINST 8579 @ no-op @ releasing store 8580 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8581 @ no-op 8582 GOTO_OPCODE(ip) @ jump to next instruction 8583 8584 8585 /* ------------------------------ */ 8586 .balign 64 8587 .L_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 8588 /* File: armv5te/OP_SPUT_BYTE_JUMBO.S */ 8589 /* File: armv5te/OP_SPUT_JUMBO.S */ 8590 /* 8591 * Jumbo 32-bit SPUT handler. 8592 * 8593 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8594 * sput-short/jumbo 8595 */ 8596 /* exop vBBBB, field@AAAAAAAA */ 8597 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8598 FETCH(r0, 1) @ r0<- aaaa (lo) 8599 FETCH(r1, 2) @ r1<- AAAA (hi) 8600 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8601 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8602 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8603 cmp r0, #0 @ is resolved entry null? 8604 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve 8605 .LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0 8606 FETCH(r2, 3) @ r2<- BBBB 8607 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8608 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8609 GET_INST_OPCODE(ip) @ extract opcode from rINST 8610 @ no-op @ releasing store 8611 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8612 @ no-op 8613 GOTO_OPCODE(ip) @ jump to next instruction 8614 8615 8616 /* ------------------------------ */ 8617 .balign 64 8618 .L_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 8619 /* File: armv5te/OP_SPUT_CHAR_JUMBO.S */ 8620 /* File: armv5te/OP_SPUT_JUMBO.S */ 8621 /* 8622 * Jumbo 32-bit SPUT handler. 8623 * 8624 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8625 * sput-short/jumbo 8626 */ 8627 /* exop vBBBB, field@AAAAAAAA */ 8628 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8629 FETCH(r0, 1) @ r0<- aaaa (lo) 8630 FETCH(r1, 2) @ r1<- AAAA (hi) 8631 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8632 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8633 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8634 cmp r0, #0 @ is resolved entry null? 8635 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve 8636 .LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0 8637 FETCH(r2, 3) @ r2<- BBBB 8638 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8639 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8640 GET_INST_OPCODE(ip) @ extract opcode from rINST 8641 @ no-op @ releasing store 8642 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8643 @ no-op 8644 GOTO_OPCODE(ip) @ jump to next instruction 8645 8646 8647 /* ------------------------------ */ 8648 .balign 64 8649 .L_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 8650 /* File: armv5te/OP_SPUT_SHORT_JUMBO.S */ 8651 /* File: armv5te/OP_SPUT_JUMBO.S */ 8652 /* 8653 * Jumbo 32-bit SPUT handler. 8654 * 8655 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 8656 * sput-short/jumbo 8657 */ 8658 /* exop vBBBB, field@AAAAAAAA */ 8659 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 8660 FETCH(r0, 1) @ r0<- aaaa (lo) 8661 FETCH(r1, 2) @ r1<- AAAA (hi) 8662 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 8663 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8664 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 8665 cmp r0, #0 @ is resolved entry null? 8666 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve 8667 .LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0 8668 FETCH(r2, 3) @ r2<- BBBB 8669 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 8670 GET_VREG(r1, r2) @ r1<- fp[BBBB] 8671 GET_INST_OPCODE(ip) @ extract opcode from rINST 8672 @ no-op @ releasing store 8673 str r1, [r0, #offStaticField_value] @ field<- vBBBB 8674 @ no-op 8675 GOTO_OPCODE(ip) @ jump to next instruction 8676 8677 8678 /* ------------------------------ */ 8679 .balign 64 8680 .L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 8681 /* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */ 8682 /* 8683 * Handle a virtual method call. 8684 */ 8685 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8686 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8687 FETCH(r0, 1) @ r1<- aaaa (lo) 8688 FETCH(r1, 2) @ r1<- AAAA (hi) 8689 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8690 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8691 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8692 cmp r0, #0 @ already resolved? 8693 EXPORT_PC() @ must export for invoke 8694 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on 8695 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 8696 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8697 mov r2, #METHOD_VIRTUAL @ resolver method type 8698 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8699 cmp r0, #0 @ got null? 8700 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue 8701 b common_exceptionThrown @ yes, handle exception 8702 8703 /* ------------------------------ */ 8704 .balign 64 8705 .L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 8706 /* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */ 8707 /* 8708 * Handle a "super" method call. 8709 */ 8710 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8711 FETCH(r10, 4) @ r10<- CCCC 8712 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8713 FETCH(r0, 1) @ r1<- aaaa (lo) 8714 FETCH(r1, 2) @ r1<- AAAA (hi) 8715 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8716 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8717 GET_VREG(r9, r10) @ r9<- "this" ptr 8718 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 8719 cmp r9, #0 @ null "this"? 8720 ldr r10, [rSELF, #offThread_method] @ r10<- current method 8721 beq common_errNullObject @ null "this", throw exception 8722 cmp r0, #0 @ already resolved? 8723 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz 8724 EXPORT_PC() @ must export for invoke 8725 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on 8726 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now 8727 8728 /* ------------------------------ */ 8729 .balign 64 8730 .L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 8731 /* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */ 8732 /* 8733 * Handle a direct method call. 8734 * 8735 * (We could defer the "is 'this' pointer null" test to the common 8736 * method invocation code, and use a flag to indicate that static 8737 * calls don't count. If we do this as part of copying the arguments 8738 * out we could avoiding loading the first arg twice.) 8739 * 8740 */ 8741 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8742 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8743 FETCH(r0, 1) @ r1<- aaaa (lo) 8744 FETCH(r1, 2) @ r1<- AAAA (hi) 8745 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8746 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8747 FETCH(r10, 4) @ r10<- CCCC 8748 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8749 cmp r0, #0 @ already resolved? 8750 EXPORT_PC() @ must export for invoke 8751 GET_VREG(r9, r10) @ r9<- "this" ptr 8752 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now 8753 .LOP_INVOKE_DIRECT_JUMBO_finish: 8754 cmp r9, #0 @ null "this" ref? 8755 bne common_invokeMethodJumbo @ (r0=method, r9="this") 8756 b common_errNullObject @ yes, throw exception 8757 8758 /* ------------------------------ */ 8759 .balign 64 8760 .L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 8761 /* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */ 8762 /* 8763 * Handle a static method call. 8764 */ 8765 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8766 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 8767 FETCH(r0, 1) @ r1<- aaaa (lo) 8768 FETCH(r1, 2) @ r1<- AAAA (hi) 8769 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 8770 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8771 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 8772 #if defined(WITH_JIT) 8773 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall 8774 #endif 8775 cmp r0, #0 @ already resolved? 8776 EXPORT_PC() @ must export for invoke 8777 bne common_invokeMethodJumboNoThis @ (r0=method) 8778 b .LOP_INVOKE_STATIC_JUMBO_resolve 8779 8780 /* ------------------------------ */ 8781 .balign 64 8782 .L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 8783 /* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */ 8784 /* 8785 * Handle an interface method call. 8786 */ 8787 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */ 8788 FETCH(r2, 4) @ r2<- CCCC 8789 FETCH(r0, 1) @ r0<- aaaa (lo) 8790 FETCH(r1, 2) @ r1<- AAAA (hi) 8791 EXPORT_PC() @ must export for invoke 8792 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 8793 GET_VREG(r9, r2) @ r9<- first arg ("this") 8794 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex 8795 cmp r9, #0 @ null obj? 8796 ldr r2, [rSELF, #offThread_method] @ r2<- method 8797 beq common_errNullObject @ yes, fail 8798 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz 8799 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 8800 cmp r0, #0 @ failed? 8801 beq common_exceptionThrown @ yes, handle exception 8802 b common_invokeMethodJumbo @ (r0=method, r9="this") 8803 8804 /* ------------------------------ */ 8805 .balign 64 8806 .L_OP_UNUSED_27FF: /* 0x127 */ 8807 /* File: armv5te/OP_UNUSED_27FF.S */ 8808 /* File: armv5te/unused.S */ 8809 bl common_abort 8810 8811 8812 /* ------------------------------ */ 8813 .balign 64 8814 .L_OP_UNUSED_28FF: /* 0x128 */ 8815 /* File: armv5te/OP_UNUSED_28FF.S */ 8816 /* File: armv5te/unused.S */ 8817 bl common_abort 8818 8819 8820 /* ------------------------------ */ 8821 .balign 64 8822 .L_OP_UNUSED_29FF: /* 0x129 */ 8823 /* File: armv5te/OP_UNUSED_29FF.S */ 8824 /* File: armv5te/unused.S */ 8825 bl common_abort 8826 8827 8828 /* ------------------------------ */ 8829 .balign 64 8830 .L_OP_UNUSED_2AFF: /* 0x12a */ 8831 /* File: armv5te/OP_UNUSED_2AFF.S */ 8832 /* File: armv5te/unused.S */ 8833 bl common_abort 8834 8835 8836 /* ------------------------------ */ 8837 .balign 64 8838 .L_OP_UNUSED_2BFF: /* 0x12b */ 8839 /* File: armv5te/OP_UNUSED_2BFF.S */ 8840 /* File: armv5te/unused.S */ 8841 bl common_abort 8842 8843 8844 /* ------------------------------ */ 8845 .balign 64 8846 .L_OP_UNUSED_2CFF: /* 0x12c */ 8847 /* File: armv5te/OP_UNUSED_2CFF.S */ 8848 /* File: armv5te/unused.S */ 8849 bl common_abort 8850 8851 8852 /* ------------------------------ */ 8853 .balign 64 8854 .L_OP_UNUSED_2DFF: /* 0x12d */ 8855 /* File: armv5te/OP_UNUSED_2DFF.S */ 8856 /* File: armv5te/unused.S */ 8857 bl common_abort 8858 8859 8860 /* ------------------------------ */ 8861 .balign 64 8862 .L_OP_UNUSED_2EFF: /* 0x12e */ 8863 /* File: armv5te/OP_UNUSED_2EFF.S */ 8864 /* File: armv5te/unused.S */ 8865 bl common_abort 8866 8867 8868 /* ------------------------------ */ 8869 .balign 64 8870 .L_OP_UNUSED_2FFF: /* 0x12f */ 8871 /* File: armv5te/OP_UNUSED_2FFF.S */ 8872 /* File: armv5te/unused.S */ 8873 bl common_abort 8874 8875 8876 /* ------------------------------ */ 8877 .balign 64 8878 .L_OP_UNUSED_30FF: /* 0x130 */ 8879 /* File: armv5te/OP_UNUSED_30FF.S */ 8880 /* File: armv5te/unused.S */ 8881 bl common_abort 8882 8883 8884 /* ------------------------------ */ 8885 .balign 64 8886 .L_OP_UNUSED_31FF: /* 0x131 */ 8887 /* File: armv5te/OP_UNUSED_31FF.S */ 8888 /* File: armv5te/unused.S */ 8889 bl common_abort 8890 8891 8892 /* ------------------------------ */ 8893 .balign 64 8894 .L_OP_UNUSED_32FF: /* 0x132 */ 8895 /* File: armv5te/OP_UNUSED_32FF.S */ 8896 /* File: armv5te/unused.S */ 8897 bl common_abort 8898 8899 8900 /* ------------------------------ */ 8901 .balign 64 8902 .L_OP_UNUSED_33FF: /* 0x133 */ 8903 /* File: armv5te/OP_UNUSED_33FF.S */ 8904 /* File: armv5te/unused.S */ 8905 bl common_abort 8906 8907 8908 /* ------------------------------ */ 8909 .balign 64 8910 .L_OP_UNUSED_34FF: /* 0x134 */ 8911 /* File: armv5te/OP_UNUSED_34FF.S */ 8912 /* File: armv5te/unused.S */ 8913 bl common_abort 8914 8915 8916 /* ------------------------------ */ 8917 .balign 64 8918 .L_OP_UNUSED_35FF: /* 0x135 */ 8919 /* File: armv5te/OP_UNUSED_35FF.S */ 8920 /* File: armv5te/unused.S */ 8921 bl common_abort 8922 8923 8924 /* ------------------------------ */ 8925 .balign 64 8926 .L_OP_UNUSED_36FF: /* 0x136 */ 8927 /* File: armv5te/OP_UNUSED_36FF.S */ 8928 /* File: armv5te/unused.S */ 8929 bl common_abort 8930 8931 8932 /* ------------------------------ */ 8933 .balign 64 8934 .L_OP_UNUSED_37FF: /* 0x137 */ 8935 /* File: armv5te/OP_UNUSED_37FF.S */ 8936 /* File: armv5te/unused.S */ 8937 bl common_abort 8938 8939 8940 /* ------------------------------ */ 8941 .balign 64 8942 .L_OP_UNUSED_38FF: /* 0x138 */ 8943 /* File: armv5te/OP_UNUSED_38FF.S */ 8944 /* File: armv5te/unused.S */ 8945 bl common_abort 8946 8947 8948 /* ------------------------------ */ 8949 .balign 64 8950 .L_OP_UNUSED_39FF: /* 0x139 */ 8951 /* File: armv5te/OP_UNUSED_39FF.S */ 8952 /* File: armv5te/unused.S */ 8953 bl common_abort 8954 8955 8956 /* ------------------------------ */ 8957 .balign 64 8958 .L_OP_UNUSED_3AFF: /* 0x13a */ 8959 /* File: armv5te/OP_UNUSED_3AFF.S */ 8960 /* File: armv5te/unused.S */ 8961 bl common_abort 8962 8963 8964 /* ------------------------------ */ 8965 .balign 64 8966 .L_OP_UNUSED_3BFF: /* 0x13b */ 8967 /* File: armv5te/OP_UNUSED_3BFF.S */ 8968 /* File: armv5te/unused.S */ 8969 bl common_abort 8970 8971 8972 /* ------------------------------ */ 8973 .balign 64 8974 .L_OP_UNUSED_3CFF: /* 0x13c */ 8975 /* File: armv5te/OP_UNUSED_3CFF.S */ 8976 /* File: armv5te/unused.S */ 8977 bl common_abort 8978 8979 8980 /* ------------------------------ */ 8981 .balign 64 8982 .L_OP_UNUSED_3DFF: /* 0x13d */ 8983 /* File: armv5te/OP_UNUSED_3DFF.S */ 8984 /* File: armv5te/unused.S */ 8985 bl common_abort 8986 8987 8988 /* ------------------------------ */ 8989 .balign 64 8990 .L_OP_UNUSED_3EFF: /* 0x13e */ 8991 /* File: armv5te/OP_UNUSED_3EFF.S */ 8992 /* File: armv5te/unused.S */ 8993 bl common_abort 8994 8995 8996 /* ------------------------------ */ 8997 .balign 64 8998 .L_OP_UNUSED_3FFF: /* 0x13f */ 8999 /* File: armv5te/OP_UNUSED_3FFF.S */ 9000 /* File: armv5te/unused.S */ 9001 bl common_abort 9002 9003 9004 /* ------------------------------ */ 9005 .balign 64 9006 .L_OP_UNUSED_40FF: /* 0x140 */ 9007 /* File: armv5te/OP_UNUSED_40FF.S */ 9008 /* File: armv5te/unused.S */ 9009 bl common_abort 9010 9011 9012 /* ------------------------------ */ 9013 .balign 64 9014 .L_OP_UNUSED_41FF: /* 0x141 */ 9015 /* File: armv5te/OP_UNUSED_41FF.S */ 9016 /* File: armv5te/unused.S */ 9017 bl common_abort 9018 9019 9020 /* ------------------------------ */ 9021 .balign 64 9022 .L_OP_UNUSED_42FF: /* 0x142 */ 9023 /* File: armv5te/OP_UNUSED_42FF.S */ 9024 /* File: armv5te/unused.S */ 9025 bl common_abort 9026 9027 9028 /* ------------------------------ */ 9029 .balign 64 9030 .L_OP_UNUSED_43FF: /* 0x143 */ 9031 /* File: armv5te/OP_UNUSED_43FF.S */ 9032 /* File: armv5te/unused.S */ 9033 bl common_abort 9034 9035 9036 /* ------------------------------ */ 9037 .balign 64 9038 .L_OP_UNUSED_44FF: /* 0x144 */ 9039 /* File: armv5te/OP_UNUSED_44FF.S */ 9040 /* File: armv5te/unused.S */ 9041 bl common_abort 9042 9043 9044 /* ------------------------------ */ 9045 .balign 64 9046 .L_OP_UNUSED_45FF: /* 0x145 */ 9047 /* File: armv5te/OP_UNUSED_45FF.S */ 9048 /* File: armv5te/unused.S */ 9049 bl common_abort 9050 9051 9052 /* ------------------------------ */ 9053 .balign 64 9054 .L_OP_UNUSED_46FF: /* 0x146 */ 9055 /* File: armv5te/OP_UNUSED_46FF.S */ 9056 /* File: armv5te/unused.S */ 9057 bl common_abort 9058 9059 9060 /* ------------------------------ */ 9061 .balign 64 9062 .L_OP_UNUSED_47FF: /* 0x147 */ 9063 /* File: armv5te/OP_UNUSED_47FF.S */ 9064 /* File: armv5te/unused.S */ 9065 bl common_abort 9066 9067 9068 /* ------------------------------ */ 9069 .balign 64 9070 .L_OP_UNUSED_48FF: /* 0x148 */ 9071 /* File: armv5te/OP_UNUSED_48FF.S */ 9072 /* File: armv5te/unused.S */ 9073 bl common_abort 9074 9075 9076 /* ------------------------------ */ 9077 .balign 64 9078 .L_OP_UNUSED_49FF: /* 0x149 */ 9079 /* File: armv5te/OP_UNUSED_49FF.S */ 9080 /* File: armv5te/unused.S */ 9081 bl common_abort 9082 9083 9084 /* ------------------------------ */ 9085 .balign 64 9086 .L_OP_UNUSED_4AFF: /* 0x14a */ 9087 /* File: armv5te/OP_UNUSED_4AFF.S */ 9088 /* File: armv5te/unused.S */ 9089 bl common_abort 9090 9091 9092 /* ------------------------------ */ 9093 .balign 64 9094 .L_OP_UNUSED_4BFF: /* 0x14b */ 9095 /* File: armv5te/OP_UNUSED_4BFF.S */ 9096 /* File: armv5te/unused.S */ 9097 bl common_abort 9098 9099 9100 /* ------------------------------ */ 9101 .balign 64 9102 .L_OP_UNUSED_4CFF: /* 0x14c */ 9103 /* File: armv5te/OP_UNUSED_4CFF.S */ 9104 /* File: armv5te/unused.S */ 9105 bl common_abort 9106 9107 9108 /* ------------------------------ */ 9109 .balign 64 9110 .L_OP_UNUSED_4DFF: /* 0x14d */ 9111 /* File: armv5te/OP_UNUSED_4DFF.S */ 9112 /* File: armv5te/unused.S */ 9113 bl common_abort 9114 9115 9116 /* ------------------------------ */ 9117 .balign 64 9118 .L_OP_UNUSED_4EFF: /* 0x14e */ 9119 /* File: armv5te/OP_UNUSED_4EFF.S */ 9120 /* File: armv5te/unused.S */ 9121 bl common_abort 9122 9123 9124 /* ------------------------------ */ 9125 .balign 64 9126 .L_OP_UNUSED_4FFF: /* 0x14f */ 9127 /* File: armv5te/OP_UNUSED_4FFF.S */ 9128 /* File: armv5te/unused.S */ 9129 bl common_abort 9130 9131 9132 /* ------------------------------ */ 9133 .balign 64 9134 .L_OP_UNUSED_50FF: /* 0x150 */ 9135 /* File: armv5te/OP_UNUSED_50FF.S */ 9136 /* File: armv5te/unused.S */ 9137 bl common_abort 9138 9139 9140 /* ------------------------------ */ 9141 .balign 64 9142 .L_OP_UNUSED_51FF: /* 0x151 */ 9143 /* File: armv5te/OP_UNUSED_51FF.S */ 9144 /* File: armv5te/unused.S */ 9145 bl common_abort 9146 9147 9148 /* ------------------------------ */ 9149 .balign 64 9150 .L_OP_UNUSED_52FF: /* 0x152 */ 9151 /* File: armv5te/OP_UNUSED_52FF.S */ 9152 /* File: armv5te/unused.S */ 9153 bl common_abort 9154 9155 9156 /* ------------------------------ */ 9157 .balign 64 9158 .L_OP_UNUSED_53FF: /* 0x153 */ 9159 /* File: armv5te/OP_UNUSED_53FF.S */ 9160 /* File: armv5te/unused.S */ 9161 bl common_abort 9162 9163 9164 /* ------------------------------ */ 9165 .balign 64 9166 .L_OP_UNUSED_54FF: /* 0x154 */ 9167 /* File: armv5te/OP_UNUSED_54FF.S */ 9168 /* File: armv5te/unused.S */ 9169 bl common_abort 9170 9171 9172 /* ------------------------------ */ 9173 .balign 64 9174 .L_OP_UNUSED_55FF: /* 0x155 */ 9175 /* File: armv5te/OP_UNUSED_55FF.S */ 9176 /* File: armv5te/unused.S */ 9177 bl common_abort 9178 9179 9180 /* ------------------------------ */ 9181 .balign 64 9182 .L_OP_UNUSED_56FF: /* 0x156 */ 9183 /* File: armv5te/OP_UNUSED_56FF.S */ 9184 /* File: armv5te/unused.S */ 9185 bl common_abort 9186 9187 9188 /* ------------------------------ */ 9189 .balign 64 9190 .L_OP_UNUSED_57FF: /* 0x157 */ 9191 /* File: armv5te/OP_UNUSED_57FF.S */ 9192 /* File: armv5te/unused.S */ 9193 bl common_abort 9194 9195 9196 /* ------------------------------ */ 9197 .balign 64 9198 .L_OP_UNUSED_58FF: /* 0x158 */ 9199 /* File: armv5te/OP_UNUSED_58FF.S */ 9200 /* File: armv5te/unused.S */ 9201 bl common_abort 9202 9203 9204 /* ------------------------------ */ 9205 .balign 64 9206 .L_OP_UNUSED_59FF: /* 0x159 */ 9207 /* File: armv5te/OP_UNUSED_59FF.S */ 9208 /* File: armv5te/unused.S */ 9209 bl common_abort 9210 9211 9212 /* ------------------------------ */ 9213 .balign 64 9214 .L_OP_UNUSED_5AFF: /* 0x15a */ 9215 /* File: armv5te/OP_UNUSED_5AFF.S */ 9216 /* File: armv5te/unused.S */ 9217 bl common_abort 9218 9219 9220 /* ------------------------------ */ 9221 .balign 64 9222 .L_OP_UNUSED_5BFF: /* 0x15b */ 9223 /* File: armv5te/OP_UNUSED_5BFF.S */ 9224 /* File: armv5te/unused.S */ 9225 bl common_abort 9226 9227 9228 /* ------------------------------ */ 9229 .balign 64 9230 .L_OP_UNUSED_5CFF: /* 0x15c */ 9231 /* File: armv5te/OP_UNUSED_5CFF.S */ 9232 /* File: armv5te/unused.S */ 9233 bl common_abort 9234 9235 9236 /* ------------------------------ */ 9237 .balign 64 9238 .L_OP_UNUSED_5DFF: /* 0x15d */ 9239 /* File: armv5te/OP_UNUSED_5DFF.S */ 9240 /* File: armv5te/unused.S */ 9241 bl common_abort 9242 9243 9244 /* ------------------------------ */ 9245 .balign 64 9246 .L_OP_UNUSED_5EFF: /* 0x15e */ 9247 /* File: armv5te/OP_UNUSED_5EFF.S */ 9248 /* File: armv5te/unused.S */ 9249 bl common_abort 9250 9251 9252 /* ------------------------------ */ 9253 .balign 64 9254 .L_OP_UNUSED_5FFF: /* 0x15f */ 9255 /* File: armv5te/OP_UNUSED_5FFF.S */ 9256 /* File: armv5te/unused.S */ 9257 bl common_abort 9258 9259 9260 /* ------------------------------ */ 9261 .balign 64 9262 .L_OP_UNUSED_60FF: /* 0x160 */ 9263 /* File: armv5te/OP_UNUSED_60FF.S */ 9264 /* File: armv5te/unused.S */ 9265 bl common_abort 9266 9267 9268 /* ------------------------------ */ 9269 .balign 64 9270 .L_OP_UNUSED_61FF: /* 0x161 */ 9271 /* File: armv5te/OP_UNUSED_61FF.S */ 9272 /* File: armv5te/unused.S */ 9273 bl common_abort 9274 9275 9276 /* ------------------------------ */ 9277 .balign 64 9278 .L_OP_UNUSED_62FF: /* 0x162 */ 9279 /* File: armv5te/OP_UNUSED_62FF.S */ 9280 /* File: armv5te/unused.S */ 9281 bl common_abort 9282 9283 9284 /* ------------------------------ */ 9285 .balign 64 9286 .L_OP_UNUSED_63FF: /* 0x163 */ 9287 /* File: armv5te/OP_UNUSED_63FF.S */ 9288 /* File: armv5te/unused.S */ 9289 bl common_abort 9290 9291 9292 /* ------------------------------ */ 9293 .balign 64 9294 .L_OP_UNUSED_64FF: /* 0x164 */ 9295 /* File: armv5te/OP_UNUSED_64FF.S */ 9296 /* File: armv5te/unused.S */ 9297 bl common_abort 9298 9299 9300 /* ------------------------------ */ 9301 .balign 64 9302 .L_OP_UNUSED_65FF: /* 0x165 */ 9303 /* File: armv5te/OP_UNUSED_65FF.S */ 9304 /* File: armv5te/unused.S */ 9305 bl common_abort 9306 9307 9308 /* ------------------------------ */ 9309 .balign 64 9310 .L_OP_UNUSED_66FF: /* 0x166 */ 9311 /* File: armv5te/OP_UNUSED_66FF.S */ 9312 /* File: armv5te/unused.S */ 9313 bl common_abort 9314 9315 9316 /* ------------------------------ */ 9317 .balign 64 9318 .L_OP_UNUSED_67FF: /* 0x167 */ 9319 /* File: armv5te/OP_UNUSED_67FF.S */ 9320 /* File: armv5te/unused.S */ 9321 bl common_abort 9322 9323 9324 /* ------------------------------ */ 9325 .balign 64 9326 .L_OP_UNUSED_68FF: /* 0x168 */ 9327 /* File: armv5te/OP_UNUSED_68FF.S */ 9328 /* File: armv5te/unused.S */ 9329 bl common_abort 9330 9331 9332 /* ------------------------------ */ 9333 .balign 64 9334 .L_OP_UNUSED_69FF: /* 0x169 */ 9335 /* File: armv5te/OP_UNUSED_69FF.S */ 9336 /* File: armv5te/unused.S */ 9337 bl common_abort 9338 9339 9340 /* ------------------------------ */ 9341 .balign 64 9342 .L_OP_UNUSED_6AFF: /* 0x16a */ 9343 /* File: armv5te/OP_UNUSED_6AFF.S */ 9344 /* File: armv5te/unused.S */ 9345 bl common_abort 9346 9347 9348 /* ------------------------------ */ 9349 .balign 64 9350 .L_OP_UNUSED_6BFF: /* 0x16b */ 9351 /* File: armv5te/OP_UNUSED_6BFF.S */ 9352 /* File: armv5te/unused.S */ 9353 bl common_abort 9354 9355 9356 /* ------------------------------ */ 9357 .balign 64 9358 .L_OP_UNUSED_6CFF: /* 0x16c */ 9359 /* File: armv5te/OP_UNUSED_6CFF.S */ 9360 /* File: armv5te/unused.S */ 9361 bl common_abort 9362 9363 9364 /* ------------------------------ */ 9365 .balign 64 9366 .L_OP_UNUSED_6DFF: /* 0x16d */ 9367 /* File: armv5te/OP_UNUSED_6DFF.S */ 9368 /* File: armv5te/unused.S */ 9369 bl common_abort 9370 9371 9372 /* ------------------------------ */ 9373 .balign 64 9374 .L_OP_UNUSED_6EFF: /* 0x16e */ 9375 /* File: armv5te/OP_UNUSED_6EFF.S */ 9376 /* File: armv5te/unused.S */ 9377 bl common_abort 9378 9379 9380 /* ------------------------------ */ 9381 .balign 64 9382 .L_OP_UNUSED_6FFF: /* 0x16f */ 9383 /* File: armv5te/OP_UNUSED_6FFF.S */ 9384 /* File: armv5te/unused.S */ 9385 bl common_abort 9386 9387 9388 /* ------------------------------ */ 9389 .balign 64 9390 .L_OP_UNUSED_70FF: /* 0x170 */ 9391 /* File: armv5te/OP_UNUSED_70FF.S */ 9392 /* File: armv5te/unused.S */ 9393 bl common_abort 9394 9395 9396 /* ------------------------------ */ 9397 .balign 64 9398 .L_OP_UNUSED_71FF: /* 0x171 */ 9399 /* File: armv5te/OP_UNUSED_71FF.S */ 9400 /* File: armv5te/unused.S */ 9401 bl common_abort 9402 9403 9404 /* ------------------------------ */ 9405 .balign 64 9406 .L_OP_UNUSED_72FF: /* 0x172 */ 9407 /* File: armv5te/OP_UNUSED_72FF.S */ 9408 /* File: armv5te/unused.S */ 9409 bl common_abort 9410 9411 9412 /* ------------------------------ */ 9413 .balign 64 9414 .L_OP_UNUSED_73FF: /* 0x173 */ 9415 /* File: armv5te/OP_UNUSED_73FF.S */ 9416 /* File: armv5te/unused.S */ 9417 bl common_abort 9418 9419 9420 /* ------------------------------ */ 9421 .balign 64 9422 .L_OP_UNUSED_74FF: /* 0x174 */ 9423 /* File: armv5te/OP_UNUSED_74FF.S */ 9424 /* File: armv5te/unused.S */ 9425 bl common_abort 9426 9427 9428 /* ------------------------------ */ 9429 .balign 64 9430 .L_OP_UNUSED_75FF: /* 0x175 */ 9431 /* File: armv5te/OP_UNUSED_75FF.S */ 9432 /* File: armv5te/unused.S */ 9433 bl common_abort 9434 9435 9436 /* ------------------------------ */ 9437 .balign 64 9438 .L_OP_UNUSED_76FF: /* 0x176 */ 9439 /* File: armv5te/OP_UNUSED_76FF.S */ 9440 /* File: armv5te/unused.S */ 9441 bl common_abort 9442 9443 9444 /* ------------------------------ */ 9445 .balign 64 9446 .L_OP_UNUSED_77FF: /* 0x177 */ 9447 /* File: armv5te/OP_UNUSED_77FF.S */ 9448 /* File: armv5te/unused.S */ 9449 bl common_abort 9450 9451 9452 /* ------------------------------ */ 9453 .balign 64 9454 .L_OP_UNUSED_78FF: /* 0x178 */ 9455 /* File: armv5te/OP_UNUSED_78FF.S */ 9456 /* File: armv5te/unused.S */ 9457 bl common_abort 9458 9459 9460 /* ------------------------------ */ 9461 .balign 64 9462 .L_OP_UNUSED_79FF: /* 0x179 */ 9463 /* File: armv5te/OP_UNUSED_79FF.S */ 9464 /* File: armv5te/unused.S */ 9465 bl common_abort 9466 9467 9468 /* ------------------------------ */ 9469 .balign 64 9470 .L_OP_UNUSED_7AFF: /* 0x17a */ 9471 /* File: armv5te/OP_UNUSED_7AFF.S */ 9472 /* File: armv5te/unused.S */ 9473 bl common_abort 9474 9475 9476 /* ------------------------------ */ 9477 .balign 64 9478 .L_OP_UNUSED_7BFF: /* 0x17b */ 9479 /* File: armv5te/OP_UNUSED_7BFF.S */ 9480 /* File: armv5te/unused.S */ 9481 bl common_abort 9482 9483 9484 /* ------------------------------ */ 9485 .balign 64 9486 .L_OP_UNUSED_7CFF: /* 0x17c */ 9487 /* File: armv5te/OP_UNUSED_7CFF.S */ 9488 /* File: armv5te/unused.S */ 9489 bl common_abort 9490 9491 9492 /* ------------------------------ */ 9493 .balign 64 9494 .L_OP_UNUSED_7DFF: /* 0x17d */ 9495 /* File: armv5te/OP_UNUSED_7DFF.S */ 9496 /* File: armv5te/unused.S */ 9497 bl common_abort 9498 9499 9500 /* ------------------------------ */ 9501 .balign 64 9502 .L_OP_UNUSED_7EFF: /* 0x17e */ 9503 /* File: armv5te/OP_UNUSED_7EFF.S */ 9504 /* File: armv5te/unused.S */ 9505 bl common_abort 9506 9507 9508 /* ------------------------------ */ 9509 .balign 64 9510 .L_OP_UNUSED_7FFF: /* 0x17f */ 9511 /* File: armv5te/OP_UNUSED_7FFF.S */ 9512 /* File: armv5te/unused.S */ 9513 bl common_abort 9514 9515 9516 /* ------------------------------ */ 9517 .balign 64 9518 .L_OP_UNUSED_80FF: /* 0x180 */ 9519 /* File: armv5te/OP_UNUSED_80FF.S */ 9520 /* File: armv5te/unused.S */ 9521 bl common_abort 9522 9523 9524 /* ------------------------------ */ 9525 .balign 64 9526 .L_OP_UNUSED_81FF: /* 0x181 */ 9527 /* File: armv5te/OP_UNUSED_81FF.S */ 9528 /* File: armv5te/unused.S */ 9529 bl common_abort 9530 9531 9532 /* ------------------------------ */ 9533 .balign 64 9534 .L_OP_UNUSED_82FF: /* 0x182 */ 9535 /* File: armv5te/OP_UNUSED_82FF.S */ 9536 /* File: armv5te/unused.S */ 9537 bl common_abort 9538 9539 9540 /* ------------------------------ */ 9541 .balign 64 9542 .L_OP_UNUSED_83FF: /* 0x183 */ 9543 /* File: armv5te/OP_UNUSED_83FF.S */ 9544 /* File: armv5te/unused.S */ 9545 bl common_abort 9546 9547 9548 /* ------------------------------ */ 9549 .balign 64 9550 .L_OP_UNUSED_84FF: /* 0x184 */ 9551 /* File: armv5te/OP_UNUSED_84FF.S */ 9552 /* File: armv5te/unused.S */ 9553 bl common_abort 9554 9555 9556 /* ------------------------------ */ 9557 .balign 64 9558 .L_OP_UNUSED_85FF: /* 0x185 */ 9559 /* File: armv5te/OP_UNUSED_85FF.S */ 9560 /* File: armv5te/unused.S */ 9561 bl common_abort 9562 9563 9564 /* ------------------------------ */ 9565 .balign 64 9566 .L_OP_UNUSED_86FF: /* 0x186 */ 9567 /* File: armv5te/OP_UNUSED_86FF.S */ 9568 /* File: armv5te/unused.S */ 9569 bl common_abort 9570 9571 9572 /* ------------------------------ */ 9573 .balign 64 9574 .L_OP_UNUSED_87FF: /* 0x187 */ 9575 /* File: armv5te/OP_UNUSED_87FF.S */ 9576 /* File: armv5te/unused.S */ 9577 bl common_abort 9578 9579 9580 /* ------------------------------ */ 9581 .balign 64 9582 .L_OP_UNUSED_88FF: /* 0x188 */ 9583 /* File: armv5te/OP_UNUSED_88FF.S */ 9584 /* File: armv5te/unused.S */ 9585 bl common_abort 9586 9587 9588 /* ------------------------------ */ 9589 .balign 64 9590 .L_OP_UNUSED_89FF: /* 0x189 */ 9591 /* File: armv5te/OP_UNUSED_89FF.S */ 9592 /* File: armv5te/unused.S */ 9593 bl common_abort 9594 9595 9596 /* ------------------------------ */ 9597 .balign 64 9598 .L_OP_UNUSED_8AFF: /* 0x18a */ 9599 /* File: armv5te/OP_UNUSED_8AFF.S */ 9600 /* File: armv5te/unused.S */ 9601 bl common_abort 9602 9603 9604 /* ------------------------------ */ 9605 .balign 64 9606 .L_OP_UNUSED_8BFF: /* 0x18b */ 9607 /* File: armv5te/OP_UNUSED_8BFF.S */ 9608 /* File: armv5te/unused.S */ 9609 bl common_abort 9610 9611 9612 /* ------------------------------ */ 9613 .balign 64 9614 .L_OP_UNUSED_8CFF: /* 0x18c */ 9615 /* File: armv5te/OP_UNUSED_8CFF.S */ 9616 /* File: armv5te/unused.S */ 9617 bl common_abort 9618 9619 9620 /* ------------------------------ */ 9621 .balign 64 9622 .L_OP_UNUSED_8DFF: /* 0x18d */ 9623 /* File: armv5te/OP_UNUSED_8DFF.S */ 9624 /* File: armv5te/unused.S */ 9625 bl common_abort 9626 9627 9628 /* ------------------------------ */ 9629 .balign 64 9630 .L_OP_UNUSED_8EFF: /* 0x18e */ 9631 /* File: armv5te/OP_UNUSED_8EFF.S */ 9632 /* File: armv5te/unused.S */ 9633 bl common_abort 9634 9635 9636 /* ------------------------------ */ 9637 .balign 64 9638 .L_OP_UNUSED_8FFF: /* 0x18f */ 9639 /* File: armv5te/OP_UNUSED_8FFF.S */ 9640 /* File: armv5te/unused.S */ 9641 bl common_abort 9642 9643 9644 /* ------------------------------ */ 9645 .balign 64 9646 .L_OP_UNUSED_90FF: /* 0x190 */ 9647 /* File: armv5te/OP_UNUSED_90FF.S */ 9648 /* File: armv5te/unused.S */ 9649 bl common_abort 9650 9651 9652 /* ------------------------------ */ 9653 .balign 64 9654 .L_OP_UNUSED_91FF: /* 0x191 */ 9655 /* File: armv5te/OP_UNUSED_91FF.S */ 9656 /* File: armv5te/unused.S */ 9657 bl common_abort 9658 9659 9660 /* ------------------------------ */ 9661 .balign 64 9662 .L_OP_UNUSED_92FF: /* 0x192 */ 9663 /* File: armv5te/OP_UNUSED_92FF.S */ 9664 /* File: armv5te/unused.S */ 9665 bl common_abort 9666 9667 9668 /* ------------------------------ */ 9669 .balign 64 9670 .L_OP_UNUSED_93FF: /* 0x193 */ 9671 /* File: armv5te/OP_UNUSED_93FF.S */ 9672 /* File: armv5te/unused.S */ 9673 bl common_abort 9674 9675 9676 /* ------------------------------ */ 9677 .balign 64 9678 .L_OP_UNUSED_94FF: /* 0x194 */ 9679 /* File: armv5te/OP_UNUSED_94FF.S */ 9680 /* File: armv5te/unused.S */ 9681 bl common_abort 9682 9683 9684 /* ------------------------------ */ 9685 .balign 64 9686 .L_OP_UNUSED_95FF: /* 0x195 */ 9687 /* File: armv5te/OP_UNUSED_95FF.S */ 9688 /* File: armv5te/unused.S */ 9689 bl common_abort 9690 9691 9692 /* ------------------------------ */ 9693 .balign 64 9694 .L_OP_UNUSED_96FF: /* 0x196 */ 9695 /* File: armv5te/OP_UNUSED_96FF.S */ 9696 /* File: armv5te/unused.S */ 9697 bl common_abort 9698 9699 9700 /* ------------------------------ */ 9701 .balign 64 9702 .L_OP_UNUSED_97FF: /* 0x197 */ 9703 /* File: armv5te/OP_UNUSED_97FF.S */ 9704 /* File: armv5te/unused.S */ 9705 bl common_abort 9706 9707 9708 /* ------------------------------ */ 9709 .balign 64 9710 .L_OP_UNUSED_98FF: /* 0x198 */ 9711 /* File: armv5te/OP_UNUSED_98FF.S */ 9712 /* File: armv5te/unused.S */ 9713 bl common_abort 9714 9715 9716 /* ------------------------------ */ 9717 .balign 64 9718 .L_OP_UNUSED_99FF: /* 0x199 */ 9719 /* File: armv5te/OP_UNUSED_99FF.S */ 9720 /* File: armv5te/unused.S */ 9721 bl common_abort 9722 9723 9724 /* ------------------------------ */ 9725 .balign 64 9726 .L_OP_UNUSED_9AFF: /* 0x19a */ 9727 /* File: armv5te/OP_UNUSED_9AFF.S */ 9728 /* File: armv5te/unused.S */ 9729 bl common_abort 9730 9731 9732 /* ------------------------------ */ 9733 .balign 64 9734 .L_OP_UNUSED_9BFF: /* 0x19b */ 9735 /* File: armv5te/OP_UNUSED_9BFF.S */ 9736 /* File: armv5te/unused.S */ 9737 bl common_abort 9738 9739 9740 /* ------------------------------ */ 9741 .balign 64 9742 .L_OP_UNUSED_9CFF: /* 0x19c */ 9743 /* File: armv5te/OP_UNUSED_9CFF.S */ 9744 /* File: armv5te/unused.S */ 9745 bl common_abort 9746 9747 9748 /* ------------------------------ */ 9749 .balign 64 9750 .L_OP_UNUSED_9DFF: /* 0x19d */ 9751 /* File: armv5te/OP_UNUSED_9DFF.S */ 9752 /* File: armv5te/unused.S */ 9753 bl common_abort 9754 9755 9756 /* ------------------------------ */ 9757 .balign 64 9758 .L_OP_UNUSED_9EFF: /* 0x19e */ 9759 /* File: armv5te/OP_UNUSED_9EFF.S */ 9760 /* File: armv5te/unused.S */ 9761 bl common_abort 9762 9763 9764 /* ------------------------------ */ 9765 .balign 64 9766 .L_OP_UNUSED_9FFF: /* 0x19f */ 9767 /* File: armv5te/OP_UNUSED_9FFF.S */ 9768 /* File: armv5te/unused.S */ 9769 bl common_abort 9770 9771 9772 /* ------------------------------ */ 9773 .balign 64 9774 .L_OP_UNUSED_A0FF: /* 0x1a0 */ 9775 /* File: armv5te/OP_UNUSED_A0FF.S */ 9776 /* File: armv5te/unused.S */ 9777 bl common_abort 9778 9779 9780 /* ------------------------------ */ 9781 .balign 64 9782 .L_OP_UNUSED_A1FF: /* 0x1a1 */ 9783 /* File: armv5te/OP_UNUSED_A1FF.S */ 9784 /* File: armv5te/unused.S */ 9785 bl common_abort 9786 9787 9788 /* ------------------------------ */ 9789 .balign 64 9790 .L_OP_UNUSED_A2FF: /* 0x1a2 */ 9791 /* File: armv5te/OP_UNUSED_A2FF.S */ 9792 /* File: armv5te/unused.S */ 9793 bl common_abort 9794 9795 9796 /* ------------------------------ */ 9797 .balign 64 9798 .L_OP_UNUSED_A3FF: /* 0x1a3 */ 9799 /* File: armv5te/OP_UNUSED_A3FF.S */ 9800 /* File: armv5te/unused.S */ 9801 bl common_abort 9802 9803 9804 /* ------------------------------ */ 9805 .balign 64 9806 .L_OP_UNUSED_A4FF: /* 0x1a4 */ 9807 /* File: armv5te/OP_UNUSED_A4FF.S */ 9808 /* File: armv5te/unused.S */ 9809 bl common_abort 9810 9811 9812 /* ------------------------------ */ 9813 .balign 64 9814 .L_OP_UNUSED_A5FF: /* 0x1a5 */ 9815 /* File: armv5te/OP_UNUSED_A5FF.S */ 9816 /* File: armv5te/unused.S */ 9817 bl common_abort 9818 9819 9820 /* ------------------------------ */ 9821 .balign 64 9822 .L_OP_UNUSED_A6FF: /* 0x1a6 */ 9823 /* File: armv5te/OP_UNUSED_A6FF.S */ 9824 /* File: armv5te/unused.S */ 9825 bl common_abort 9826 9827 9828 /* ------------------------------ */ 9829 .balign 64 9830 .L_OP_UNUSED_A7FF: /* 0x1a7 */ 9831 /* File: armv5te/OP_UNUSED_A7FF.S */ 9832 /* File: armv5te/unused.S */ 9833 bl common_abort 9834 9835 9836 /* ------------------------------ */ 9837 .balign 64 9838 .L_OP_UNUSED_A8FF: /* 0x1a8 */ 9839 /* File: armv5te/OP_UNUSED_A8FF.S */ 9840 /* File: armv5te/unused.S */ 9841 bl common_abort 9842 9843 9844 /* ------------------------------ */ 9845 .balign 64 9846 .L_OP_UNUSED_A9FF: /* 0x1a9 */ 9847 /* File: armv5te/OP_UNUSED_A9FF.S */ 9848 /* File: armv5te/unused.S */ 9849 bl common_abort 9850 9851 9852 /* ------------------------------ */ 9853 .balign 64 9854 .L_OP_UNUSED_AAFF: /* 0x1aa */ 9855 /* File: armv5te/OP_UNUSED_AAFF.S */ 9856 /* File: armv5te/unused.S */ 9857 bl common_abort 9858 9859 9860 /* ------------------------------ */ 9861 .balign 64 9862 .L_OP_UNUSED_ABFF: /* 0x1ab */ 9863 /* File: armv5te/OP_UNUSED_ABFF.S */ 9864 /* File: armv5te/unused.S */ 9865 bl common_abort 9866 9867 9868 /* ------------------------------ */ 9869 .balign 64 9870 .L_OP_UNUSED_ACFF: /* 0x1ac */ 9871 /* File: armv5te/OP_UNUSED_ACFF.S */ 9872 /* File: armv5te/unused.S */ 9873 bl common_abort 9874 9875 9876 /* ------------------------------ */ 9877 .balign 64 9878 .L_OP_UNUSED_ADFF: /* 0x1ad */ 9879 /* File: armv5te/OP_UNUSED_ADFF.S */ 9880 /* File: armv5te/unused.S */ 9881 bl common_abort 9882 9883 9884 /* ------------------------------ */ 9885 .balign 64 9886 .L_OP_UNUSED_AEFF: /* 0x1ae */ 9887 /* File: armv5te/OP_UNUSED_AEFF.S */ 9888 /* File: armv5te/unused.S */ 9889 bl common_abort 9890 9891 9892 /* ------------------------------ */ 9893 .balign 64 9894 .L_OP_UNUSED_AFFF: /* 0x1af */ 9895 /* File: armv5te/OP_UNUSED_AFFF.S */ 9896 /* File: armv5te/unused.S */ 9897 bl common_abort 9898 9899 9900 /* ------------------------------ */ 9901 .balign 64 9902 .L_OP_UNUSED_B0FF: /* 0x1b0 */ 9903 /* File: armv5te/OP_UNUSED_B0FF.S */ 9904 /* File: armv5te/unused.S */ 9905 bl common_abort 9906 9907 9908 /* ------------------------------ */ 9909 .balign 64 9910 .L_OP_UNUSED_B1FF: /* 0x1b1 */ 9911 /* File: armv5te/OP_UNUSED_B1FF.S */ 9912 /* File: armv5te/unused.S */ 9913 bl common_abort 9914 9915 9916 /* ------------------------------ */ 9917 .balign 64 9918 .L_OP_UNUSED_B2FF: /* 0x1b2 */ 9919 /* File: armv5te/OP_UNUSED_B2FF.S */ 9920 /* File: armv5te/unused.S */ 9921 bl common_abort 9922 9923 9924 /* ------------------------------ */ 9925 .balign 64 9926 .L_OP_UNUSED_B3FF: /* 0x1b3 */ 9927 /* File: armv5te/OP_UNUSED_B3FF.S */ 9928 /* File: armv5te/unused.S */ 9929 bl common_abort 9930 9931 9932 /* ------------------------------ */ 9933 .balign 64 9934 .L_OP_UNUSED_B4FF: /* 0x1b4 */ 9935 /* File: armv5te/OP_UNUSED_B4FF.S */ 9936 /* File: armv5te/unused.S */ 9937 bl common_abort 9938 9939 9940 /* ------------------------------ */ 9941 .balign 64 9942 .L_OP_UNUSED_B5FF: /* 0x1b5 */ 9943 /* File: armv5te/OP_UNUSED_B5FF.S */ 9944 /* File: armv5te/unused.S */ 9945 bl common_abort 9946 9947 9948 /* ------------------------------ */ 9949 .balign 64 9950 .L_OP_UNUSED_B6FF: /* 0x1b6 */ 9951 /* File: armv5te/OP_UNUSED_B6FF.S */ 9952 /* File: armv5te/unused.S */ 9953 bl common_abort 9954 9955 9956 /* ------------------------------ */ 9957 .balign 64 9958 .L_OP_UNUSED_B7FF: /* 0x1b7 */ 9959 /* File: armv5te/OP_UNUSED_B7FF.S */ 9960 /* File: armv5te/unused.S */ 9961 bl common_abort 9962 9963 9964 /* ------------------------------ */ 9965 .balign 64 9966 .L_OP_UNUSED_B8FF: /* 0x1b8 */ 9967 /* File: armv5te/OP_UNUSED_B8FF.S */ 9968 /* File: armv5te/unused.S */ 9969 bl common_abort 9970 9971 9972 /* ------------------------------ */ 9973 .balign 64 9974 .L_OP_UNUSED_B9FF: /* 0x1b9 */ 9975 /* File: armv5te/OP_UNUSED_B9FF.S */ 9976 /* File: armv5te/unused.S */ 9977 bl common_abort 9978 9979 9980 /* ------------------------------ */ 9981 .balign 64 9982 .L_OP_UNUSED_BAFF: /* 0x1ba */ 9983 /* File: armv5te/OP_UNUSED_BAFF.S */ 9984 /* File: armv5te/unused.S */ 9985 bl common_abort 9986 9987 9988 /* ------------------------------ */ 9989 .balign 64 9990 .L_OP_UNUSED_BBFF: /* 0x1bb */ 9991 /* File: armv5te/OP_UNUSED_BBFF.S */ 9992 /* File: armv5te/unused.S */ 9993 bl common_abort 9994 9995 9996 /* ------------------------------ */ 9997 .balign 64 9998 .L_OP_UNUSED_BCFF: /* 0x1bc */ 9999 /* File: armv5te/OP_UNUSED_BCFF.S */ 10000 /* File: armv5te/unused.S */ 10001 bl common_abort 10002 10003 10004 /* ------------------------------ */ 10005 .balign 64 10006 .L_OP_UNUSED_BDFF: /* 0x1bd */ 10007 /* File: armv5te/OP_UNUSED_BDFF.S */ 10008 /* File: armv5te/unused.S */ 10009 bl common_abort 10010 10011 10012 /* ------------------------------ */ 10013 .balign 64 10014 .L_OP_UNUSED_BEFF: /* 0x1be */ 10015 /* File: armv5te/OP_UNUSED_BEFF.S */ 10016 /* File: armv5te/unused.S */ 10017 bl common_abort 10018 10019 10020 /* ------------------------------ */ 10021 .balign 64 10022 .L_OP_UNUSED_BFFF: /* 0x1bf */ 10023 /* File: armv5te/OP_UNUSED_BFFF.S */ 10024 /* File: armv5te/unused.S */ 10025 bl common_abort 10026 10027 10028 /* ------------------------------ */ 10029 .balign 64 10030 .L_OP_UNUSED_C0FF: /* 0x1c0 */ 10031 /* File: armv5te/OP_UNUSED_C0FF.S */ 10032 /* File: armv5te/unused.S */ 10033 bl common_abort 10034 10035 10036 /* ------------------------------ */ 10037 .balign 64 10038 .L_OP_UNUSED_C1FF: /* 0x1c1 */ 10039 /* File: armv5te/OP_UNUSED_C1FF.S */ 10040 /* File: armv5te/unused.S */ 10041 bl common_abort 10042 10043 10044 /* ------------------------------ */ 10045 .balign 64 10046 .L_OP_UNUSED_C2FF: /* 0x1c2 */ 10047 /* File: armv5te/OP_UNUSED_C2FF.S */ 10048 /* File: armv5te/unused.S */ 10049 bl common_abort 10050 10051 10052 /* ------------------------------ */ 10053 .balign 64 10054 .L_OP_UNUSED_C3FF: /* 0x1c3 */ 10055 /* File: armv5te/OP_UNUSED_C3FF.S */ 10056 /* File: armv5te/unused.S */ 10057 bl common_abort 10058 10059 10060 /* ------------------------------ */ 10061 .balign 64 10062 .L_OP_UNUSED_C4FF: /* 0x1c4 */ 10063 /* File: armv5te/OP_UNUSED_C4FF.S */ 10064 /* File: armv5te/unused.S */ 10065 bl common_abort 10066 10067 10068 /* ------------------------------ */ 10069 .balign 64 10070 .L_OP_UNUSED_C5FF: /* 0x1c5 */ 10071 /* File: armv5te/OP_UNUSED_C5FF.S */ 10072 /* File: armv5te/unused.S */ 10073 bl common_abort 10074 10075 10076 /* ------------------------------ */ 10077 .balign 64 10078 .L_OP_UNUSED_C6FF: /* 0x1c6 */ 10079 /* File: armv5te/OP_UNUSED_C6FF.S */ 10080 /* File: armv5te/unused.S */ 10081 bl common_abort 10082 10083 10084 /* ------------------------------ */ 10085 .balign 64 10086 .L_OP_UNUSED_C7FF: /* 0x1c7 */ 10087 /* File: armv5te/OP_UNUSED_C7FF.S */ 10088 /* File: armv5te/unused.S */ 10089 bl common_abort 10090 10091 10092 /* ------------------------------ */ 10093 .balign 64 10094 .L_OP_UNUSED_C8FF: /* 0x1c8 */ 10095 /* File: armv5te/OP_UNUSED_C8FF.S */ 10096 /* File: armv5te/unused.S */ 10097 bl common_abort 10098 10099 10100 /* ------------------------------ */ 10101 .balign 64 10102 .L_OP_UNUSED_C9FF: /* 0x1c9 */ 10103 /* File: armv5te/OP_UNUSED_C9FF.S */ 10104 /* File: armv5te/unused.S */ 10105 bl common_abort 10106 10107 10108 /* ------------------------------ */ 10109 .balign 64 10110 .L_OP_UNUSED_CAFF: /* 0x1ca */ 10111 /* File: armv5te/OP_UNUSED_CAFF.S */ 10112 /* File: armv5te/unused.S */ 10113 bl common_abort 10114 10115 10116 /* ------------------------------ */ 10117 .balign 64 10118 .L_OP_UNUSED_CBFF: /* 0x1cb */ 10119 /* File: armv5te/OP_UNUSED_CBFF.S */ 10120 /* File: armv5te/unused.S */ 10121 bl common_abort 10122 10123 10124 /* ------------------------------ */ 10125 .balign 64 10126 .L_OP_UNUSED_CCFF: /* 0x1cc */ 10127 /* File: armv5te/OP_UNUSED_CCFF.S */ 10128 /* File: armv5te/unused.S */ 10129 bl common_abort 10130 10131 10132 /* ------------------------------ */ 10133 .balign 64 10134 .L_OP_UNUSED_CDFF: /* 0x1cd */ 10135 /* File: armv5te/OP_UNUSED_CDFF.S */ 10136 /* File: armv5te/unused.S */ 10137 bl common_abort 10138 10139 10140 /* ------------------------------ */ 10141 .balign 64 10142 .L_OP_UNUSED_CEFF: /* 0x1ce */ 10143 /* File: armv5te/OP_UNUSED_CEFF.S */ 10144 /* File: armv5te/unused.S */ 10145 bl common_abort 10146 10147 10148 /* ------------------------------ */ 10149 .balign 64 10150 .L_OP_UNUSED_CFFF: /* 0x1cf */ 10151 /* File: armv5te/OP_UNUSED_CFFF.S */ 10152 /* File: armv5te/unused.S */ 10153 bl common_abort 10154 10155 10156 /* ------------------------------ */ 10157 .balign 64 10158 .L_OP_UNUSED_D0FF: /* 0x1d0 */ 10159 /* File: armv5te/OP_UNUSED_D0FF.S */ 10160 /* File: armv5te/unused.S */ 10161 bl common_abort 10162 10163 10164 /* ------------------------------ */ 10165 .balign 64 10166 .L_OP_UNUSED_D1FF: /* 0x1d1 */ 10167 /* File: armv5te/OP_UNUSED_D1FF.S */ 10168 /* File: armv5te/unused.S */ 10169 bl common_abort 10170 10171 10172 /* ------------------------------ */ 10173 .balign 64 10174 .L_OP_UNUSED_D2FF: /* 0x1d2 */ 10175 /* File: armv5te/OP_UNUSED_D2FF.S */ 10176 /* File: armv5te/unused.S */ 10177 bl common_abort 10178 10179 10180 /* ------------------------------ */ 10181 .balign 64 10182 .L_OP_UNUSED_D3FF: /* 0x1d3 */ 10183 /* File: armv5te/OP_UNUSED_D3FF.S */ 10184 /* File: armv5te/unused.S */ 10185 bl common_abort 10186 10187 10188 /* ------------------------------ */ 10189 .balign 64 10190 .L_OP_UNUSED_D4FF: /* 0x1d4 */ 10191 /* File: armv5te/OP_UNUSED_D4FF.S */ 10192 /* File: armv5te/unused.S */ 10193 bl common_abort 10194 10195 10196 /* ------------------------------ */ 10197 .balign 64 10198 .L_OP_UNUSED_D5FF: /* 0x1d5 */ 10199 /* File: armv5te/OP_UNUSED_D5FF.S */ 10200 /* File: armv5te/unused.S */ 10201 bl common_abort 10202 10203 10204 /* ------------------------------ */ 10205 .balign 64 10206 .L_OP_UNUSED_D6FF: /* 0x1d6 */ 10207 /* File: armv5te/OP_UNUSED_D6FF.S */ 10208 /* File: armv5te/unused.S */ 10209 bl common_abort 10210 10211 10212 /* ------------------------------ */ 10213 .balign 64 10214 .L_OP_UNUSED_D7FF: /* 0x1d7 */ 10215 /* File: armv5te/OP_UNUSED_D7FF.S */ 10216 /* File: armv5te/unused.S */ 10217 bl common_abort 10218 10219 10220 /* ------------------------------ */ 10221 .balign 64 10222 .L_OP_UNUSED_D8FF: /* 0x1d8 */ 10223 /* File: armv5te/OP_UNUSED_D8FF.S */ 10224 /* File: armv5te/unused.S */ 10225 bl common_abort 10226 10227 10228 /* ------------------------------ */ 10229 .balign 64 10230 .L_OP_UNUSED_D9FF: /* 0x1d9 */ 10231 /* File: armv5te/OP_UNUSED_D9FF.S */ 10232 /* File: armv5te/unused.S */ 10233 bl common_abort 10234 10235 10236 /* ------------------------------ */ 10237 .balign 64 10238 .L_OP_UNUSED_DAFF: /* 0x1da */ 10239 /* File: armv5te/OP_UNUSED_DAFF.S */ 10240 /* File: armv5te/unused.S */ 10241 bl common_abort 10242 10243 10244 /* ------------------------------ */ 10245 .balign 64 10246 .L_OP_UNUSED_DBFF: /* 0x1db */ 10247 /* File: armv5te/OP_UNUSED_DBFF.S */ 10248 /* File: armv5te/unused.S */ 10249 bl common_abort 10250 10251 10252 /* ------------------------------ */ 10253 .balign 64 10254 .L_OP_UNUSED_DCFF: /* 0x1dc */ 10255 /* File: armv5te/OP_UNUSED_DCFF.S */ 10256 /* File: armv5te/unused.S */ 10257 bl common_abort 10258 10259 10260 /* ------------------------------ */ 10261 .balign 64 10262 .L_OP_UNUSED_DDFF: /* 0x1dd */ 10263 /* File: armv5te/OP_UNUSED_DDFF.S */ 10264 /* File: armv5te/unused.S */ 10265 bl common_abort 10266 10267 10268 /* ------------------------------ */ 10269 .balign 64 10270 .L_OP_UNUSED_DEFF: /* 0x1de */ 10271 /* File: armv5te/OP_UNUSED_DEFF.S */ 10272 /* File: armv5te/unused.S */ 10273 bl common_abort 10274 10275 10276 /* ------------------------------ */ 10277 .balign 64 10278 .L_OP_UNUSED_DFFF: /* 0x1df */ 10279 /* File: armv5te/OP_UNUSED_DFFF.S */ 10280 /* File: armv5te/unused.S */ 10281 bl common_abort 10282 10283 10284 /* ------------------------------ */ 10285 .balign 64 10286 .L_OP_UNUSED_E0FF: /* 0x1e0 */ 10287 /* File: armv5te/OP_UNUSED_E0FF.S */ 10288 /* File: armv5te/unused.S */ 10289 bl common_abort 10290 10291 10292 /* ------------------------------ */ 10293 .balign 64 10294 .L_OP_UNUSED_E1FF: /* 0x1e1 */ 10295 /* File: armv5te/OP_UNUSED_E1FF.S */ 10296 /* File: armv5te/unused.S */ 10297 bl common_abort 10298 10299 10300 /* ------------------------------ */ 10301 .balign 64 10302 .L_OP_UNUSED_E2FF: /* 0x1e2 */ 10303 /* File: armv5te/OP_UNUSED_E2FF.S */ 10304 /* File: armv5te/unused.S */ 10305 bl common_abort 10306 10307 10308 /* ------------------------------ */ 10309 .balign 64 10310 .L_OP_UNUSED_E3FF: /* 0x1e3 */ 10311 /* File: armv5te/OP_UNUSED_E3FF.S */ 10312 /* File: armv5te/unused.S */ 10313 bl common_abort 10314 10315 10316 /* ------------------------------ */ 10317 .balign 64 10318 .L_OP_UNUSED_E4FF: /* 0x1e4 */ 10319 /* File: armv5te/OP_UNUSED_E4FF.S */ 10320 /* File: armv5te/unused.S */ 10321 bl common_abort 10322 10323 10324 /* ------------------------------ */ 10325 .balign 64 10326 .L_OP_UNUSED_E5FF: /* 0x1e5 */ 10327 /* File: armv5te/OP_UNUSED_E5FF.S */ 10328 /* File: armv5te/unused.S */ 10329 bl common_abort 10330 10331 10332 /* ------------------------------ */ 10333 .balign 64 10334 .L_OP_UNUSED_E6FF: /* 0x1e6 */ 10335 /* File: armv5te/OP_UNUSED_E6FF.S */ 10336 /* File: armv5te/unused.S */ 10337 bl common_abort 10338 10339 10340 /* ------------------------------ */ 10341 .balign 64 10342 .L_OP_UNUSED_E7FF: /* 0x1e7 */ 10343 /* File: armv5te/OP_UNUSED_E7FF.S */ 10344 /* File: armv5te/unused.S */ 10345 bl common_abort 10346 10347 10348 /* ------------------------------ */ 10349 .balign 64 10350 .L_OP_UNUSED_E8FF: /* 0x1e8 */ 10351 /* File: armv5te/OP_UNUSED_E8FF.S */ 10352 /* File: armv5te/unused.S */ 10353 bl common_abort 10354 10355 10356 /* ------------------------------ */ 10357 .balign 64 10358 .L_OP_UNUSED_E9FF: /* 0x1e9 */ 10359 /* File: armv5te/OP_UNUSED_E9FF.S */ 10360 /* File: armv5te/unused.S */ 10361 bl common_abort 10362 10363 10364 /* ------------------------------ */ 10365 .balign 64 10366 .L_OP_UNUSED_EAFF: /* 0x1ea */ 10367 /* File: armv5te/OP_UNUSED_EAFF.S */ 10368 /* File: armv5te/unused.S */ 10369 bl common_abort 10370 10371 10372 /* ------------------------------ */ 10373 .balign 64 10374 .L_OP_UNUSED_EBFF: /* 0x1eb */ 10375 /* File: armv5te/OP_UNUSED_EBFF.S */ 10376 /* File: armv5te/unused.S */ 10377 bl common_abort 10378 10379 10380 /* ------------------------------ */ 10381 .balign 64 10382 .L_OP_UNUSED_ECFF: /* 0x1ec */ 10383 /* File: armv5te/OP_UNUSED_ECFF.S */ 10384 /* File: armv5te/unused.S */ 10385 bl common_abort 10386 10387 10388 /* ------------------------------ */ 10389 .balign 64 10390 .L_OP_UNUSED_EDFF: /* 0x1ed */ 10391 /* File: armv5te/OP_UNUSED_EDFF.S */ 10392 /* File: armv5te/unused.S */ 10393 bl common_abort 10394 10395 10396 /* ------------------------------ */ 10397 .balign 64 10398 .L_OP_UNUSED_EEFF: /* 0x1ee */ 10399 /* File: armv5te/OP_UNUSED_EEFF.S */ 10400 /* File: armv5te/unused.S */ 10401 bl common_abort 10402 10403 10404 /* ------------------------------ */ 10405 .balign 64 10406 .L_OP_UNUSED_EFFF: /* 0x1ef */ 10407 /* File: armv5te/OP_UNUSED_EFFF.S */ 10408 /* File: armv5te/unused.S */ 10409 bl common_abort 10410 10411 10412 /* ------------------------------ */ 10413 .balign 64 10414 .L_OP_UNUSED_F0FF: /* 0x1f0 */ 10415 /* File: armv5te/OP_UNUSED_F0FF.S */ 10416 /* File: armv5te/unused.S */ 10417 bl common_abort 10418 10419 10420 /* ------------------------------ */ 10421 .balign 64 10422 .L_OP_UNUSED_F1FF: /* 0x1f1 */ 10423 /* File: armv5te/OP_UNUSED_F1FF.S */ 10424 /* File: armv5te/unused.S */ 10425 bl common_abort 10426 10427 10428 /* ------------------------------ */ 10429 .balign 64 10430 .L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */ 10431 /* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */ 10432 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */ 10433 /* 10434 * Invoke Object.<init> on an object. In practice we know that 10435 * Object's nullary constructor doesn't do anything, so we just 10436 * skip it unless a debugger is active. 10437 */ 10438 FETCH(r1, 4) @ r1<- CCCC 10439 GET_VREG(r0, r1) @ r0<- "this" ptr 10440 cmp r0, #0 @ check for NULL 10441 beq common_errNullObject @ export PC and throw NPE 10442 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz 10443 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags 10444 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable? 10445 bne .LOP_INVOKE_OBJECT_INIT_JUMBO_setFinal @ yes, go 10446 .LOP_INVOKE_OBJECT_INIT_JUMBO_finish: 10447 ldrh r1, [rSELF, #offThread_subMode] 10448 ands r1, #kSubModeDebuggerActive @ debugger active? 10449 bne .LOP_INVOKE_OBJECT_INIT_JUMBO_debugger @ Yes - skip optimization 10450 FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST 10451 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 10452 GOTO_OPCODE(ip) @ execute it 10453 10454 10455 /* ------------------------------ */ 10456 .balign 64 10457 .L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */ 10458 /* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */ 10459 /* File: armv5te/OP_IGET_JUMBO.S */ 10460 /* 10461 * Jumbo 32-bit instance field get. 10462 * 10463 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 10464 * iget-char/jumbo, iget-short/jumbo 10465 */ 10466 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10467 FETCH(r1, 1) @ r1<- aaaa (lo) 10468 FETCH(r2, 2) @ r2<- AAAA (hi) 10469 FETCH(r0, 4) @ r0<- CCCC 10470 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10471 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10472 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10473 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10474 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10475 cmp r0, #0 @ is resolved entry null? 10476 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved 10477 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10478 EXPORT_PC() @ resolve() could throw 10479 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10480 bl dvmResolveInstField @ r0<- resolved InstField ptr 10481 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue 10482 10483 10484 /* ------------------------------ */ 10485 .balign 64 10486 .L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */ 10487 /* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */ 10488 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */ 10489 /* 10490 * Jumbo 64-bit instance field get. 10491 */ 10492 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10493 FETCH(r1, 1) @ r1<- aaaa (lo) 10494 FETCH(r2, 2) @ r2<- AAAA (hi) 10495 FETCH(r0, 4) @ r0<- CCCC 10496 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10497 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10498 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 10499 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10500 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10501 cmp r0, #0 @ is resolved entry null? 10502 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved 10503 ldr r2, [rSELF, #offThread_method] @ r2<- current method 10504 EXPORT_PC() @ resolve() could throw 10505 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10506 bl dvmResolveInstField @ r0<- resolved InstField ptr 10507 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue 10508 10509 10510 /* ------------------------------ */ 10511 .balign 64 10512 .L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */ 10513 /* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */ 10514 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */ 10515 /* File: armv5te/OP_IGET_JUMBO.S */ 10516 /* 10517 * Jumbo 32-bit instance field get. 10518 * 10519 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo, 10520 * iget-char/jumbo, iget-short/jumbo 10521 */ 10522 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10523 FETCH(r1, 1) @ r1<- aaaa (lo) 10524 FETCH(r2, 2) @ r2<- AAAA (hi) 10525 FETCH(r0, 4) @ r0<- CCCC 10526 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10527 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10528 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10529 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10530 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10531 cmp r0, #0 @ is resolved entry null? 10532 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved 10533 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10534 EXPORT_PC() @ resolve() could throw 10535 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10536 bl dvmResolveInstField @ r0<- resolved InstField ptr 10537 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue 10538 10539 10540 10541 /* ------------------------------ */ 10542 .balign 64 10543 .L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */ 10544 /* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */ 10545 /* File: armv5te/OP_IPUT_JUMBO.S */ 10546 /* 10547 * Jumbo 32-bit instance field put. 10548 * 10549 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo, 10550 * iput-short/jumbo 10551 */ 10552 /* exop vBBBB, vCCCC, field@AAAAAAAA */ 10553 FETCH(r1, 1) @ r1<- aaaa (lo) 10554 FETCH(r2, 2) @ r2<- AAAA (hi) 10555 FETCH(r0, 4) @ r0<- CCCC 10556 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10557 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10558 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10559 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10560 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10561 cmp r0, #0 @ is resolved entry null? 10562 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved 10563 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10564 EXPORT_PC() @ resolve() could throw 10565 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10566 bl dvmResolveInstField @ r0<- resolved InstField ptr 10567 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue 10568 10569 10570 /* ------------------------------ */ 10571 .balign 64 10572 .L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */ 10573 /* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */ 10574 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */ 10575 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10576 FETCH(r1, 1) @ r1<- aaaa (lo) 10577 FETCH(r2, 2) @ r2<- AAAA (hi) 10578 FETCH(r0, 4) @ r0<- CCCC 10579 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10580 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10581 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 10582 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 10583 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10584 cmp r0, #0 @ is resolved entry null? 10585 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved 10586 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10587 EXPORT_PC() @ resolve() could throw 10588 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10589 bl dvmResolveInstField @ r0<- resolved InstField ptr 10590 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue 10591 10592 10593 /* ------------------------------ */ 10594 .balign 64 10595 .L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */ 10596 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */ 10597 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */ 10598 /* 10599 * Jumbo 32-bit instance field put. 10600 */ 10601 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */ 10602 FETCH(r1, 1) @ r1<- aaaa (lo) 10603 FETCH(r2, 2) @ r2<- AAAA (hi) 10604 FETCH(r0, 4) @ r0<- CCCC 10605 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex 10606 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10607 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 10608 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer 10609 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 10610 cmp r0, #0 @ is resolved entry null? 10611 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved 10612 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method 10613 EXPORT_PC() @ resolve() could throw 10614 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 10615 bl dvmResolveInstField @ r0<- resolved InstField ptr 10616 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue 10617 10618 10619 /* ------------------------------ */ 10620 .balign 64 10621 .L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */ 10622 /* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */ 10623 /* File: armv5te/OP_SGET_JUMBO.S */ 10624 /* 10625 * Jumbo 32-bit SGET handler. 10626 * 10627 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 10628 * sget-char/jumbo, sget-short/jumbo 10629 */ 10630 /* exop vBBBB, field@AAAAAAAA */ 10631 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10632 FETCH(r0, 1) @ r0<- aaaa (lo) 10633 FETCH(r1, 2) @ r1<- AAAA (hi) 10634 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 10635 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10636 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 10637 cmp r0, #0 @ is resolved entry null? 10638 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve 10639 .LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0 10640 ldr r1, [r0, #offStaticField_value] @ r1<- field value 10641 SMP_DMB @ acquiring load 10642 FETCH(r2, 3) @ r2<- BBBB 10643 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10644 SET_VREG(r1, r2) @ fp[BBBB]<- r1 10645 GET_INST_OPCODE(ip) @ extract opcode from rINST 10646 GOTO_OPCODE(ip) @ jump to next instruction 10647 10648 10649 /* ------------------------------ */ 10650 .balign 64 10651 .L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */ 10652 /* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */ 10653 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */ 10654 /* 10655 * Jumbo 64-bit SGET handler. 10656 */ 10657 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */ 10658 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10659 FETCH(r0, 1) @ r0<- aaaa (lo) 10660 FETCH(r1, 2) @ r1<- AAAA (hi) 10661 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 10662 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10663 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 10664 cmp r0, #0 @ is resolved entry null? 10665 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve 10666 .LOP_SGET_WIDE_VOLATILE_JUMBO_finish: 10667 FETCH(r9, 3) @ r9<- BBBB 10668 .if 1 10669 add r0, r0, #offStaticField_value @ r0<- pointer to data 10670 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 10671 .else 10672 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 10673 .endif 10674 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 10675 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10676 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1 10677 GET_INST_OPCODE(ip) @ extract opcode from rINST 10678 GOTO_OPCODE(ip) @ jump to next instruction 10679 10680 10681 /* ------------------------------ */ 10682 .balign 64 10683 .L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */ 10684 /* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */ 10685 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */ 10686 /* File: armv5te/OP_SGET_JUMBO.S */ 10687 /* 10688 * Jumbo 32-bit SGET handler. 10689 * 10690 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo, 10691 * sget-char/jumbo, sget-short/jumbo 10692 */ 10693 /* exop vBBBB, field@AAAAAAAA */ 10694 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10695 FETCH(r0, 1) @ r0<- aaaa (lo) 10696 FETCH(r1, 2) @ r1<- AAAA (hi) 10697 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 10698 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10699 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 10700 cmp r0, #0 @ is resolved entry null? 10701 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve 10702 .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0 10703 ldr r1, [r0, #offStaticField_value] @ r1<- field value 10704 SMP_DMB @ acquiring load 10705 FETCH(r2, 3) @ r2<- BBBB 10706 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10707 SET_VREG(r1, r2) @ fp[BBBB]<- r1 10708 GET_INST_OPCODE(ip) @ extract opcode from rINST 10709 GOTO_OPCODE(ip) @ jump to next instruction 10710 10711 10712 10713 /* ------------------------------ */ 10714 .balign 64 10715 .L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */ 10716 /* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */ 10717 /* File: armv5te/OP_SPUT_JUMBO.S */ 10718 /* 10719 * Jumbo 32-bit SPUT handler. 10720 * 10721 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo, 10722 * sput-short/jumbo 10723 */ 10724 /* exop vBBBB, field@AAAAAAAA */ 10725 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10726 FETCH(r0, 1) @ r0<- aaaa (lo) 10727 FETCH(r1, 2) @ r1<- AAAA (hi) 10728 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 10729 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10730 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 10731 cmp r0, #0 @ is resolved entry null? 10732 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve 10733 .LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0 10734 FETCH(r2, 3) @ r2<- BBBB 10735 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10736 GET_VREG(r1, r2) @ r1<- fp[BBBB] 10737 GET_INST_OPCODE(ip) @ extract opcode from rINST 10738 SMP_DMB_ST @ releasing store 10739 str r1, [r0, #offStaticField_value] @ field<- vBBBB 10740 SMP_DMB 10741 GOTO_OPCODE(ip) @ jump to next instruction 10742 10743 10744 /* ------------------------------ */ 10745 .balign 64 10746 .L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */ 10747 /* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */ 10748 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */ 10749 /* 10750 * Jumbo 64-bit SPUT handler. 10751 */ 10752 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */ 10753 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex 10754 FETCH(r1, 1) @ r1<- aaaa (lo) 10755 FETCH(r2, 2) @ r2<- AAAA (hi) 10756 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 10757 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa 10758 FETCH(r9, 3) @ r9<- BBBB 10759 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr 10760 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB] 10761 cmp r2, #0 @ is resolved entry null? 10762 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve 10763 .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9 10764 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10765 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1 10766 GET_INST_OPCODE(r10) @ extract opcode from rINST 10767 .if 1 10768 add r2, r2, #offStaticField_value @ r2<- pointer to data 10769 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 10770 .else 10771 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1 10772 .endif 10773 GOTO_OPCODE(r10) @ jump to next instruction 10774 10775 10776 /* ------------------------------ */ 10777 .balign 64 10778 .L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */ 10779 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */ 10780 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */ 10781 /* 10782 * Jumbo 32-bit SPUT handler for objects 10783 */ 10784 /* sput-object/jumbo vBBBB, field@AAAAAAAA */ 10785 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex 10786 FETCH(r0, 1) @ r0<- aaaa (lo) 10787 FETCH(r1, 2) @ r1<- AAAA (hi) 10788 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields 10789 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa 10790 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr 10791 cmp r0, #0 @ is resolved entry null? 10792 beq .LOP_SPUT_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve 10793 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0 10794 FETCH(r2, 3) @ r2<- BBBB 10795 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 10796 GET_VREG(r1, r2) @ r1<- fp[BBBB] 10797 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 10798 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 10799 GET_INST_OPCODE(ip) @ extract opcode from rINST 10800 SMP_DMB_ST @ releasing store 10801 b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end 10802 10803 10804 /* ------------------------------ */ 10805 .balign 64 10806 .L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 10807 /* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */ 10808 /* 10809 * Handle a jumbo throw-verification-error instruction. This throws an 10810 * exception for an error discovered during verification. The 10811 * exception is indicated by BBBB, with some detail provided by AAAAAAAA. 10812 */ 10813 /* exop BBBB, Class@AAAAAAAA */ 10814 FETCH(r1, 1) @ r1<- aaaa (lo) 10815 FETCH(r2, 2) @ r2<- AAAA (hi) 10816 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10817 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa 10818 EXPORT_PC() @ export the PC 10819 FETCH(r1, 3) @ r1<- BBBB 10820 bl dvmThrowVerificationError @ always throws 10821 b common_exceptionThrown @ handle exception 10822 10823 .balign 64 10824 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 10825 .global dvmAsmInstructionEnd 10826 dvmAsmInstructionEnd: 10827 10828 /* 10829 * =========================================================================== 10830 * Sister implementations 10831 * =========================================================================== 10832 */ 10833 .global dvmAsmSisterStart 10834 .type dvmAsmSisterStart, %function 10835 .text 10836 .balign 4 10837 dvmAsmSisterStart: 10838 10839 /* continuation for OP_CONST_STRING */ 10840 10841 /* 10842 * Continuation if the String has not yet been resolved. 10843 * r1: BBBB (String ref) 10844 * r9: target register 10845 */ 10846 .LOP_CONST_STRING_resolve: 10847 EXPORT_PC() 10848 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10849 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10850 bl dvmResolveString @ r0<- String reference 10851 cmp r0, #0 @ failed? 10852 beq common_exceptionThrown @ yup, handle the exception 10853 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10854 GET_INST_OPCODE(ip) @ extract opcode from rINST 10855 SET_VREG(r0, r9) @ vAA<- r0 10856 GOTO_OPCODE(ip) @ jump to next instruction 10857 10858 /* continuation for OP_CONST_STRING_JUMBO */ 10859 10860 /* 10861 * Continuation if the String has not yet been resolved. 10862 * r1: BBBBBBBB (String ref) 10863 * r9: target register 10864 */ 10865 .LOP_CONST_STRING_JUMBO_resolve: 10866 EXPORT_PC() 10867 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10868 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10869 bl dvmResolveString @ r0<- String reference 10870 cmp r0, #0 @ failed? 10871 beq common_exceptionThrown @ yup, handle the exception 10872 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10873 GET_INST_OPCODE(ip) @ extract opcode from rINST 10874 SET_VREG(r0, r9) @ vAA<- r0 10875 GOTO_OPCODE(ip) @ jump to next instruction 10876 10877 /* continuation for OP_CONST_CLASS */ 10878 10879 /* 10880 * Continuation if the Class has not yet been resolved. 10881 * r1: BBBB (Class ref) 10882 * r9: target register 10883 */ 10884 .LOP_CONST_CLASS_resolve: 10885 EXPORT_PC() 10886 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10887 mov r2, #1 @ r2<- true 10888 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10889 bl dvmResolveClass @ r0<- Class reference 10890 cmp r0, #0 @ failed? 10891 beq common_exceptionThrown @ yup, handle the exception 10892 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10893 GET_INST_OPCODE(ip) @ extract opcode from rINST 10894 SET_VREG(r0, r9) @ vAA<- r0 10895 GOTO_OPCODE(ip) @ jump to next instruction 10896 10897 /* continuation for OP_CHECK_CAST */ 10898 10899 /* 10900 * Trivial test failed, need to perform full check. This is common. 10901 * r0 holds obj->clazz 10902 * r1 holds desired class resolved from BBBB 10903 * r9 holds object 10904 */ 10905 .LOP_CHECK_CAST_fullcheck: 10906 mov r10, r1 @ avoid ClassObject getting clobbered 10907 bl dvmInstanceofNonTrivial @ r0<- boolean result 10908 cmp r0, #0 @ failed? 10909 bne .LOP_CHECK_CAST_okay @ no, success 10910 10911 @ A cast has failed. We need to throw a ClassCastException. 10912 EXPORT_PC() @ about to throw 10913 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 10914 mov r1, r10 @ r1<- desired class 10915 bl dvmThrowClassCastException 10916 b common_exceptionThrown 10917 10918 /* 10919 * Resolution required. This is the least-likely path. 10920 * 10921 * r2 holds BBBB 10922 * r9 holds object 10923 */ 10924 .LOP_CHECK_CAST_resolve: 10925 EXPORT_PC() @ resolve() could throw 10926 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 10927 mov r1, r2 @ r1<- BBBB 10928 mov r2, #0 @ r2<- false 10929 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 10930 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10931 cmp r0, #0 @ got null? 10932 beq common_exceptionThrown @ yes, handle exception 10933 mov r1, r0 @ r1<- class resolved from BBB 10934 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 10935 b .LOP_CHECK_CAST_resolved @ pick up where we left off 10936 10937 /* continuation for OP_INSTANCE_OF */ 10938 10939 /* 10940 * Trivial test failed, need to perform full check. This is common. 10941 * r0 holds obj->clazz 10942 * r1 holds class resolved from BBBB 10943 * r9 holds A 10944 */ 10945 .LOP_INSTANCE_OF_fullcheck: 10946 bl dvmInstanceofNonTrivial @ r0<- boolean result 10947 @ fall through to OP_INSTANCE_OF_store 10948 10949 /* 10950 * r0 holds boolean result 10951 * r9 holds A 10952 */ 10953 .LOP_INSTANCE_OF_store: 10954 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10955 SET_VREG(r0, r9) @ vA<- r0 10956 GET_INST_OPCODE(ip) @ extract opcode from rINST 10957 GOTO_OPCODE(ip) @ jump to next instruction 10958 10959 /* 10960 * Trivial test succeeded, save and bail. 10961 * r9 holds A 10962 */ 10963 .LOP_INSTANCE_OF_trivial: 10964 mov r0, #1 @ indicate success 10965 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 10966 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 10967 SET_VREG(r0, r9) @ vA<- r0 10968 GET_INST_OPCODE(ip) @ extract opcode from rINST 10969 GOTO_OPCODE(ip) @ jump to next instruction 10970 10971 /* 10972 * Resolution required. This is the least-likely path. 10973 * 10974 * r3 holds BBBB 10975 * r9 holds A 10976 */ 10977 .LOP_INSTANCE_OF_resolve: 10978 EXPORT_PC() @ resolve() could throw 10979 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 10980 mov r1, r3 @ r1<- BBBB 10981 mov r2, #1 @ r2<- true 10982 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 10983 bl dvmResolveClass @ r0<- resolved ClassObject ptr 10984 cmp r0, #0 @ got null? 10985 beq common_exceptionThrown @ yes, handle exception 10986 mov r1, r0 @ r1<- class resolved from BBB 10987 mov r3, rINST, lsr #12 @ r3<- B 10988 GET_VREG(r0, r3) @ r0<- vB (object) 10989 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 10990 b .LOP_INSTANCE_OF_resolved @ pick up where we left off 10991 10992 /* continuation for OP_NEW_INSTANCE */ 10993 10994 .balign 32 @ minimize cache lines 10995 .LOP_NEW_INSTANCE_finish: @ r0=new object 10996 mov r3, rINST, lsr #8 @ r3<- AA 10997 cmp r0, #0 @ failed? 10998 #if defined(WITH_JIT) 10999 /* 11000 * The JIT needs the class to be fully resolved before it can 11001 * include this instruction in a trace. 11002 */ 11003 ldrh r1, [rSELF, #offThread_subMode] 11004 beq common_exceptionThrown @ yes, handle the exception 11005 ands r1, #kSubModeJitTraceBuild @ under construction? 11006 bne .LOP_NEW_INSTANCE_jitCheck 11007 #else 11008 beq common_exceptionThrown @ yes, handle the exception 11009 #endif 11010 .LOP_NEW_INSTANCE_end: 11011 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11012 GET_INST_OPCODE(ip) @ extract opcode from rINST 11013 SET_VREG(r0, r3) @ vAA<- r0 11014 GOTO_OPCODE(ip) @ jump to next instruction 11015 11016 #if defined(WITH_JIT) 11017 /* 11018 * Check to see if we need to stop the trace building early. 11019 * r0: new object 11020 * r3: vAA 11021 */ 11022 .LOP_NEW_INSTANCE_jitCheck: 11023 ldr r1, [r10] @ reload resolved class 11024 cmp r1, #0 @ okay? 11025 bne .LOP_NEW_INSTANCE_end @ yes, finish 11026 mov r9, r0 @ preserve new object 11027 mov r10, r3 @ preserve vAA 11028 mov r0, rSELF 11029 mov r1, rPC 11030 bl dvmJitEndTraceSelect @ (self, pc) 11031 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11032 GET_INST_OPCODE(ip) @ extract opcode from rINST 11033 SET_VREG(r9, r10) @ vAA<- new object 11034 GOTO_OPCODE(ip) @ jump to next instruction 11035 #endif 11036 11037 /* 11038 * Class initialization required. 11039 * 11040 * r0 holds class object 11041 */ 11042 .LOP_NEW_INSTANCE_needinit: 11043 mov r9, r0 @ save r0 11044 bl dvmInitClass @ initialize class 11045 cmp r0, #0 @ check boolean result 11046 mov r0, r9 @ restore r0 11047 bne .LOP_NEW_INSTANCE_initialized @ success, continue 11048 b common_exceptionThrown @ failed, deal with init exception 11049 11050 /* 11051 * Resolution required. This is the least-likely path. 11052 * 11053 * r1 holds BBBB 11054 */ 11055 .LOP_NEW_INSTANCE_resolve: 11056 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11057 mov r2, #0 @ r2<- false 11058 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11059 bl dvmResolveClass @ r0<- resolved ClassObject ptr 11060 cmp r0, #0 @ got null? 11061 bne .LOP_NEW_INSTANCE_resolved @ no, continue 11062 b common_exceptionThrown @ yes, handle exception 11063 11064 /* continuation for OP_NEW_ARRAY */ 11065 11066 11067 /* 11068 * Resolve class. (This is an uncommon case.) 11069 * 11070 * r1 holds array length 11071 * r2 holds class ref CCCC 11072 */ 11073 .LOP_NEW_ARRAY_resolve: 11074 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 11075 mov r9, r1 @ r9<- length (save) 11076 mov r1, r2 @ r1<- CCCC 11077 mov r2, #0 @ r2<- false 11078 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 11079 bl dvmResolveClass @ r0<- call(clazz, ref) 11080 cmp r0, #0 @ got null? 11081 mov r1, r9 @ r1<- length (restore) 11082 beq common_exceptionThrown @ yes, handle exception 11083 @ fall through to OP_NEW_ARRAY_finish 11084 11085 /* 11086 * Finish allocation. 11087 * 11088 * r0 holds class 11089 * r1 holds array length 11090 */ 11091 .LOP_NEW_ARRAY_finish: 11092 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 11093 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 11094 cmp r0, #0 @ failed? 11095 mov r2, rINST, lsr #8 @ r2<- A+ 11096 beq common_exceptionThrown @ yes, handle the exception 11097 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11098 and r2, r2, #15 @ r2<- A 11099 GET_INST_OPCODE(ip) @ extract opcode from rINST 11100 SET_VREG(r0, r2) @ vA<- r0 11101 GOTO_OPCODE(ip) @ jump to next instruction 11102 11103 /* continuation for OP_FILLED_NEW_ARRAY */ 11104 11105 /* 11106 * On entry: 11107 * r0 holds array class 11108 * r10 holds AA or BA 11109 */ 11110 .LOP_FILLED_NEW_ARRAY_continue: 11111 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11112 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11113 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11114 .if 0 11115 mov r1, r10 @ r1<- AA (length) 11116 .else 11117 mov r1, r10, lsr #4 @ r1<- B (length) 11118 .endif 11119 cmp rINST, #'I' @ array of ints? 11120 cmpne rINST, #'L' @ array of objects? 11121 cmpne rINST, #'[' @ array of arrays? 11122 mov r9, r1 @ save length in r9 11123 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 11124 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11125 cmp r0, #0 @ null return? 11126 beq common_exceptionThrown @ alloc failed, handle exception 11127 11128 FETCH(r1, 2) @ r1<- FEDC or CCCC 11129 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11130 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11131 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11132 subs r9, r9, #1 @ length--, check for neg 11133 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11134 bmi 2f @ was zero, bail 11135 11136 @ copy values from registers into the array 11137 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11138 .if 0 11139 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 11140 1: ldr r3, [r2], #4 @ r3<- *r2++ 11141 subs r9, r9, #1 @ count-- 11142 str r3, [r0], #4 @ *contents++ = vX 11143 bpl 1b 11144 @ continue at 2 11145 .else 11146 cmp r9, #4 @ length was initially 5? 11147 and r2, r10, #15 @ r2<- A 11148 bne 1f @ <= 4 args, branch 11149 GET_VREG(r3, r2) @ r3<- vA 11150 sub r9, r9, #1 @ count-- 11151 str r3, [r0, #16] @ contents[4] = vA 11152 1: and r2, r1, #15 @ r2<- F/E/D/C 11153 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11154 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11155 subs r9, r9, #1 @ count-- 11156 str r3, [r0], #4 @ *contents++ = vX 11157 bpl 1b 11158 @ continue at 2 11159 .endif 11160 11161 2: 11162 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11163 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11164 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11165 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11166 cmp r1, #'I' @ Is int array? 11167 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11168 GOTO_OPCODE(ip) @ execute it 11169 11170 /* 11171 * Throw an exception indicating that we have not implemented this 11172 * mode of filled-new-array. 11173 */ 11174 .LOP_FILLED_NEW_ARRAY_notimpl: 11175 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY 11176 bl dvmThrowInternalError 11177 b common_exceptionThrown 11178 11179 /* 11180 * Ideally we'd only define this once, but depending on layout we can 11181 * exceed the range of the load above. 11182 */ 11183 11184 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY: 11185 .word .LstrFilledNewArrayNotImpl 11186 11187 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 11188 11189 /* 11190 * On entry: 11191 * r0 holds array class 11192 * r10 holds AA or BA 11193 */ 11194 .LOP_FILLED_NEW_ARRAY_RANGE_continue: 11195 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 11196 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 11197 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 11198 .if 1 11199 mov r1, r10 @ r1<- AA (length) 11200 .else 11201 mov r1, r10, lsr #4 @ r1<- B (length) 11202 .endif 11203 cmp rINST, #'I' @ array of ints? 11204 cmpne rINST, #'L' @ array of objects? 11205 cmpne rINST, #'[' @ array of arrays? 11206 mov r9, r1 @ save length in r9 11207 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 11208 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 11209 cmp r0, #0 @ null return? 11210 beq common_exceptionThrown @ alloc failed, handle exception 11211 11212 FETCH(r1, 2) @ r1<- FEDC or CCCC 11213 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 11214 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 11215 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 11216 subs r9, r9, #1 @ length--, check for neg 11217 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 11218 bmi 2f @ was zero, bail 11219 11220 @ copy values from registers into the array 11221 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 11222 .if 1 11223 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 11224 1: ldr r3, [r2], #4 @ r3<- *r2++ 11225 subs r9, r9, #1 @ count-- 11226 str r3, [r0], #4 @ *contents++ = vX 11227 bpl 1b 11228 @ continue at 2 11229 .else 11230 cmp r9, #4 @ length was initially 5? 11231 and r2, r10, #15 @ r2<- A 11232 bne 1f @ <= 4 args, branch 11233 GET_VREG(r3, r2) @ r3<- vA 11234 sub r9, r9, #1 @ count-- 11235 str r3, [r0, #16] @ contents[4] = vA 11236 1: and r2, r1, #15 @ r2<- F/E/D/C 11237 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 11238 mov r1, r1, lsr #4 @ r1<- next reg in low 4 11239 subs r9, r9, #1 @ count-- 11240 str r3, [r0], #4 @ *contents++ = vX 11241 bpl 1b 11242 @ continue at 2 11243 .endif 11244 11245 2: 11246 ldr r0, [rSELF, #offThread_retval] @ r0<- object 11247 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 11248 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11249 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 11250 cmp r1, #'I' @ Is int array? 11251 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 11252 GOTO_OPCODE(ip) @ execute it 11253 11254 /* 11255 * Throw an exception indicating that we have not implemented this 11256 * mode of filled-new-array. 11257 */ 11258 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 11259 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_RANGE 11260 bl dvmThrowInternalError 11261 b common_exceptionThrown 11262 11263 /* 11264 * Ideally we'd only define this once, but depending on layout we can 11265 * exceed the range of the load above. 11266 */ 11267 11268 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_RANGE: 11269 .word .LstrFilledNewArrayNotImpl 11270 11271 /* continuation for OP_CMPL_FLOAT */ 11272 .LOP_CMPL_FLOAT_finish: 11273 SET_VREG(r0, r9) @ vAA<- r0 11274 GOTO_OPCODE(ip) @ jump to next instruction 11275 11276 /* continuation for OP_CMPG_FLOAT */ 11277 .LOP_CMPG_FLOAT_finish: 11278 SET_VREG(r0, r9) @ vAA<- r0 11279 GOTO_OPCODE(ip) @ jump to next instruction 11280 11281 /* continuation for OP_CMPL_DOUBLE */ 11282 .LOP_CMPL_DOUBLE_finish: 11283 SET_VREG(r0, r9) @ vAA<- r0 11284 GOTO_OPCODE(ip) @ jump to next instruction 11285 11286 /* continuation for OP_CMPG_DOUBLE */ 11287 .LOP_CMPG_DOUBLE_finish: 11288 SET_VREG(r0, r9) @ vAA<- r0 11289 GOTO_OPCODE(ip) @ jump to next instruction 11290 11291 /* continuation for OP_CMP_LONG */ 11292 11293 .LOP_CMP_LONG_less: 11294 mvn r1, #0 @ r1<- -1 11295 @ Want to cond code the next mov so we can avoid branch, but don't see it; 11296 @ instead, we just replicate the tail end. 11297 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11298 SET_VREG(r1, r9) @ vAA<- r1 11299 GET_INST_OPCODE(ip) @ extract opcode from rINST 11300 GOTO_OPCODE(ip) @ jump to next instruction 11301 11302 .LOP_CMP_LONG_greater: 11303 mov r1, #1 @ r1<- 1 11304 @ fall through to _finish 11305 11306 .LOP_CMP_LONG_finish: 11307 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11308 SET_VREG(r1, r9) @ vAA<- r1 11309 GET_INST_OPCODE(ip) @ extract opcode from rINST 11310 GOTO_OPCODE(ip) @ jump to next instruction 11311 11312 /* continuation for OP_AGET_WIDE */ 11313 11314 .LOP_AGET_WIDE_finish: 11315 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11316 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11317 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 11318 GET_INST_OPCODE(ip) @ extract opcode from rINST 11319 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 11320 GOTO_OPCODE(ip) @ jump to next instruction 11321 11322 /* continuation for OP_APUT_WIDE */ 11323 11324 .LOP_APUT_WIDE_finish: 11325 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11326 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 11327 GET_INST_OPCODE(ip) @ extract opcode from rINST 11328 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 11329 GOTO_OPCODE(ip) @ jump to next instruction 11330 11331 /* continuation for OP_APUT_OBJECT */ 11332 /* 11333 * On entry: 11334 * rINST = vBB (arrayObj) 11335 * r9 = vAA (obj) 11336 * r10 = offset into array (vBB + vCC * width) 11337 */ 11338 .LOP_APUT_OBJECT_finish: 11339 cmp r9, #0 @ storing null reference? 11340 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 11341 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 11342 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 11343 bl dvmCanPutArrayElement @ test object type vs. array type 11344 cmp r0, #0 @ okay? 11345 beq .LOP_APUT_OBJECT_throw @ no 11346 mov r1, rINST @ r1<- arrayObj 11347 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11348 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base 11349 add r10, #offArrayObject_contents @ r0<- pointer to slot 11350 GET_INST_OPCODE(ip) @ extract opcode from rINST 11351 str r9, [r10] @ vBB[vCC]<- vAA 11352 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 11353 GOTO_OPCODE(ip) @ jump to next instruction 11354 .LOP_APUT_OBJECT_skip_check: 11355 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11356 GET_INST_OPCODE(ip) @ extract opcode from rINST 11357 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 11358 GOTO_OPCODE(ip) @ jump to next instruction 11359 .LOP_APUT_OBJECT_throw: 11360 @ The types don't match. We need to throw an ArrayStoreException. 11361 ldr r0, [r9, #offObject_clazz] 11362 ldr r1, [rINST, #offObject_clazz] 11363 EXPORT_PC() 11364 bl dvmThrowArrayStoreExceptionIncompatibleElement 11365 b common_exceptionThrown 11366 11367 /* continuation for OP_IGET */ 11368 11369 /* 11370 * Currently: 11371 * r0 holds resolved field 11372 * r9 holds object 11373 */ 11374 .LOP_IGET_finish: 11375 @bl common_squeak0 11376 cmp r9, #0 @ check object for null 11377 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11378 beq common_errNullObject @ object was null 11379 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11380 @ no-op @ acquiring load 11381 mov r2, rINST, lsr #8 @ r2<- A+ 11382 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11383 and r2, r2, #15 @ r2<- A 11384 GET_INST_OPCODE(ip) @ extract opcode from rINST 11385 SET_VREG(r0, r2) @ fp[A]<- r0 11386 GOTO_OPCODE(ip) @ jump to next instruction 11387 11388 /* continuation for OP_IGET_WIDE */ 11389 11390 /* 11391 * Currently: 11392 * r0 holds resolved field 11393 * r9 holds object 11394 */ 11395 .LOP_IGET_WIDE_finish: 11396 cmp r9, #0 @ check object for null 11397 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11398 beq common_errNullObject @ object was null 11399 .if 0 11400 add r0, r9, r3 @ r0<- address of field 11401 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 11402 .else 11403 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 11404 .endif 11405 mov r2, rINST, lsr #8 @ r2<- A+ 11406 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11407 and r2, r2, #15 @ r2<- A 11408 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 11409 GET_INST_OPCODE(ip) @ extract opcode from rINST 11410 stmia r3, {r0-r1} @ fp[A]<- r0/r1 11411 GOTO_OPCODE(ip) @ jump to next instruction 11412 11413 /* continuation for OP_IGET_OBJECT */ 11414 11415 /* 11416 * Currently: 11417 * r0 holds resolved field 11418 * r9 holds object 11419 */ 11420 .LOP_IGET_OBJECT_finish: 11421 @bl common_squeak0 11422 cmp r9, #0 @ check object for null 11423 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11424 beq common_errNullObject @ object was null 11425 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11426 @ no-op @ acquiring load 11427 mov r2, rINST, lsr #8 @ r2<- A+ 11428 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11429 and r2, r2, #15 @ r2<- A 11430 GET_INST_OPCODE(ip) @ extract opcode from rINST 11431 SET_VREG(r0, r2) @ fp[A]<- r0 11432 GOTO_OPCODE(ip) @ jump to next instruction 11433 11434 /* continuation for OP_IGET_BOOLEAN */ 11435 11436 /* 11437 * Currently: 11438 * r0 holds resolved field 11439 * r9 holds object 11440 */ 11441 .LOP_IGET_BOOLEAN_finish: 11442 @bl common_squeak1 11443 cmp r9, #0 @ check object for null 11444 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11445 beq common_errNullObject @ object was null 11446 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11447 @ no-op @ acquiring load 11448 mov r2, rINST, lsr #8 @ r2<- A+ 11449 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11450 and r2, r2, #15 @ r2<- A 11451 GET_INST_OPCODE(ip) @ extract opcode from rINST 11452 SET_VREG(r0, r2) @ fp[A]<- r0 11453 GOTO_OPCODE(ip) @ jump to next instruction 11454 11455 /* continuation for OP_IGET_BYTE */ 11456 11457 /* 11458 * Currently: 11459 * r0 holds resolved field 11460 * r9 holds object 11461 */ 11462 .LOP_IGET_BYTE_finish: 11463 @bl common_squeak2 11464 cmp r9, #0 @ check object for null 11465 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11466 beq common_errNullObject @ object was null 11467 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11468 @ no-op @ acquiring load 11469 mov r2, rINST, lsr #8 @ r2<- A+ 11470 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11471 and r2, r2, #15 @ r2<- A 11472 GET_INST_OPCODE(ip) @ extract opcode from rINST 11473 SET_VREG(r0, r2) @ fp[A]<- r0 11474 GOTO_OPCODE(ip) @ jump to next instruction 11475 11476 /* continuation for OP_IGET_CHAR */ 11477 11478 /* 11479 * Currently: 11480 * r0 holds resolved field 11481 * r9 holds object 11482 */ 11483 .LOP_IGET_CHAR_finish: 11484 @bl common_squeak3 11485 cmp r9, #0 @ check object for null 11486 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11487 beq common_errNullObject @ object was null 11488 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11489 @ no-op @ acquiring load 11490 mov r2, rINST, lsr #8 @ r2<- A+ 11491 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11492 and r2, r2, #15 @ r2<- A 11493 GET_INST_OPCODE(ip) @ extract opcode from rINST 11494 SET_VREG(r0, r2) @ fp[A]<- r0 11495 GOTO_OPCODE(ip) @ jump to next instruction 11496 11497 /* continuation for OP_IGET_SHORT */ 11498 11499 /* 11500 * Currently: 11501 * r0 holds resolved field 11502 * r9 holds object 11503 */ 11504 .LOP_IGET_SHORT_finish: 11505 @bl common_squeak4 11506 cmp r9, #0 @ check object for null 11507 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11508 beq common_errNullObject @ object was null 11509 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 11510 @ no-op @ acquiring load 11511 mov r2, rINST, lsr #8 @ r2<- A+ 11512 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11513 and r2, r2, #15 @ r2<- A 11514 GET_INST_OPCODE(ip) @ extract opcode from rINST 11515 SET_VREG(r0, r2) @ fp[A]<- r0 11516 GOTO_OPCODE(ip) @ jump to next instruction 11517 11518 /* continuation for OP_IPUT */ 11519 11520 /* 11521 * Currently: 11522 * r0 holds resolved field 11523 * r9 holds object 11524 */ 11525 .LOP_IPUT_finish: 11526 @bl common_squeak0 11527 mov r1, rINST, lsr #8 @ r1<- A+ 11528 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11529 and r1, r1, #15 @ r1<- A 11530 cmp r9, #0 @ check object for null 11531 GET_VREG(r0, r1) @ r0<- fp[A] 11532 beq common_errNullObject @ object was null 11533 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11534 GET_INST_OPCODE(ip) @ extract opcode from rINST 11535 @ no-op @ releasing store 11536 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11537 @ no-op 11538 GOTO_OPCODE(ip) @ jump to next instruction 11539 11540 /* continuation for OP_IPUT_WIDE */ 11541 11542 /* 11543 * Currently: 11544 * r0 holds resolved field 11545 * r9 holds object 11546 */ 11547 .LOP_IPUT_WIDE_finish: 11548 mov r2, rINST, lsr #8 @ r2<- A+ 11549 cmp r9, #0 @ check object for null 11550 and r2, r2, #15 @ r2<- A 11551 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11552 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 11553 beq common_errNullObject @ object was null 11554 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11555 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 11556 GET_INST_OPCODE(r10) @ extract opcode from rINST 11557 .if 0 11558 add r2, r9, r3 @ r2<- target address 11559 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 11560 .else 11561 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 11562 .endif 11563 GOTO_OPCODE(r10) @ jump to next instruction 11564 11565 /* continuation for OP_IPUT_OBJECT */ 11566 11567 /* 11568 * Currently: 11569 * r0 holds resolved field 11570 * r9 holds object 11571 */ 11572 .LOP_IPUT_OBJECT_finish: 11573 @bl common_squeak0 11574 mov r1, rINST, lsr #8 @ r1<- A+ 11575 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11576 and r1, r1, #15 @ r1<- A 11577 cmp r9, #0 @ check object for null 11578 GET_VREG(r0, r1) @ r0<- fp[A] 11579 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 11580 beq common_errNullObject @ object was null 11581 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11582 GET_INST_OPCODE(ip) @ extract opcode from rINST 11583 @ no-op @ releasing store 11584 str r0, [r9, r3] @ obj.field (32 bits)<- r0 11585 @ no-op 11586 cmp r0, #0 @ stored a null reference? 11587 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 11588 GOTO_OPCODE(ip) @ jump to next instruction 11589 11590 /* continuation for OP_IPUT_BOOLEAN */ 11591 11592 /* 11593 * Currently: 11594 * r0 holds resolved field 11595 * r9 holds object 11596 */ 11597 .LOP_IPUT_BOOLEAN_finish: 11598 @bl common_squeak1 11599 mov r1, rINST, lsr #8 @ r1<- A+ 11600 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11601 and r1, r1, #15 @ r1<- A 11602 cmp r9, #0 @ check object for null 11603 GET_VREG(r0, r1) @ r0<- fp[A] 11604 beq common_errNullObject @ object was null 11605 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11606 GET_INST_OPCODE(ip) @ extract opcode from rINST 11607 @ no-op @ releasing store 11608 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11609 @ no-op 11610 GOTO_OPCODE(ip) @ jump to next instruction 11611 11612 /* continuation for OP_IPUT_BYTE */ 11613 11614 /* 11615 * Currently: 11616 * r0 holds resolved field 11617 * r9 holds object 11618 */ 11619 .LOP_IPUT_BYTE_finish: 11620 @bl common_squeak2 11621 mov r1, rINST, lsr #8 @ r1<- A+ 11622 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11623 and r1, r1, #15 @ r1<- A 11624 cmp r9, #0 @ check object for null 11625 GET_VREG(r0, r1) @ r0<- fp[A] 11626 beq common_errNullObject @ object was null 11627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11628 GET_INST_OPCODE(ip) @ extract opcode from rINST 11629 @ no-op @ releasing store 11630 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11631 @ no-op 11632 GOTO_OPCODE(ip) @ jump to next instruction 11633 11634 /* continuation for OP_IPUT_CHAR */ 11635 11636 /* 11637 * Currently: 11638 * r0 holds resolved field 11639 * r9 holds object 11640 */ 11641 .LOP_IPUT_CHAR_finish: 11642 @bl common_squeak3 11643 mov r1, rINST, lsr #8 @ r1<- A+ 11644 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11645 and r1, r1, #15 @ r1<- A 11646 cmp r9, #0 @ check object for null 11647 GET_VREG(r0, r1) @ r0<- fp[A] 11648 beq common_errNullObject @ object was null 11649 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11650 GET_INST_OPCODE(ip) @ extract opcode from rINST 11651 @ no-op @ releasing store 11652 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11653 @ no-op 11654 GOTO_OPCODE(ip) @ jump to next instruction 11655 11656 /* continuation for OP_IPUT_SHORT */ 11657 11658 /* 11659 * Currently: 11660 * r0 holds resolved field 11661 * r9 holds object 11662 */ 11663 .LOP_IPUT_SHORT_finish: 11664 @bl common_squeak4 11665 mov r1, rINST, lsr #8 @ r1<- A+ 11666 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 11667 and r1, r1, #15 @ r1<- A 11668 cmp r9, #0 @ check object for null 11669 GET_VREG(r0, r1) @ r0<- fp[A] 11670 beq common_errNullObject @ object was null 11671 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 11672 GET_INST_OPCODE(ip) @ extract opcode from rINST 11673 @ no-op @ releasing store 11674 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 11675 @ no-op 11676 GOTO_OPCODE(ip) @ jump to next instruction 11677 11678 /* continuation for OP_SGET */ 11679 11680 /* 11681 * Continuation if the field has not yet been resolved. 11682 * r1: BBBB field ref 11683 * r10: dvmDex->pResFields 11684 */ 11685 .LOP_SGET_resolve: 11686 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11687 #if defined(WITH_JIT) 11688 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11689 #endif 11690 EXPORT_PC() @ resolve() could throw, so export now 11691 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11692 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11693 cmp r0, #0 @ success? 11694 beq common_exceptionThrown @ no, handle exception 11695 #if defined(WITH_JIT) 11696 /* 11697 * If the JIT is actively building a trace we need to make sure 11698 * that the field is fully resolved before including this instruction. 11699 */ 11700 bl common_verifyField 11701 #endif 11702 b .LOP_SGET_finish 11703 11704 /* continuation for OP_SGET_WIDE */ 11705 11706 /* 11707 * Continuation if the field has not yet been resolved. 11708 * r1: BBBB field ref 11709 * r10: dvmDex->pResFields 11710 * 11711 * Returns StaticField pointer in r0. 11712 */ 11713 .LOP_SGET_WIDE_resolve: 11714 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11715 #if defined(WITH_JIT) 11716 add r10, r10, r1, lsl #2 @ r1<- &dvmDex->pResFields[field] 11717 #endif 11718 EXPORT_PC() @ resolve() could throw, so export now 11719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11720 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11721 cmp r0, #0 @ success? 11722 beq common_exceptionThrown @ no, handle exception 11723 #if defined(WITH_JIT) 11724 /* 11725 * If the JIT is actively building a trace we need to make sure 11726 * that the field is fully resolved before including this instruction. 11727 */ 11728 bl common_verifyField 11729 #endif 11730 b .LOP_SGET_WIDE_finish @ resume 11731 11732 /* continuation for OP_SGET_OBJECT */ 11733 11734 /* 11735 * Continuation if the field has not yet been resolved. 11736 * r1: BBBB field ref 11737 * r10: dvmDex->pResFields 11738 */ 11739 .LOP_SGET_OBJECT_resolve: 11740 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11741 #if defined(WITH_JIT) 11742 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11743 #endif 11744 EXPORT_PC() @ resolve() could throw, so export now 11745 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11746 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11747 cmp r0, #0 @ success? 11748 beq common_exceptionThrown @ no, handle exception 11749 #if defined(WITH_JIT) 11750 /* 11751 * If the JIT is actively building a trace we need to make sure 11752 * that the field is fully resolved before including this instruction. 11753 */ 11754 bl common_verifyField 11755 #endif 11756 b .LOP_SGET_OBJECT_finish 11757 11758 /* continuation for OP_SGET_BOOLEAN */ 11759 11760 /* 11761 * Continuation if the field has not yet been resolved. 11762 * r1: BBBB field ref 11763 * r10: dvmDex->pResFields 11764 */ 11765 .LOP_SGET_BOOLEAN_resolve: 11766 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11767 #if defined(WITH_JIT) 11768 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11769 #endif 11770 EXPORT_PC() @ resolve() could throw, so export now 11771 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11772 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11773 cmp r0, #0 @ success? 11774 beq common_exceptionThrown @ no, handle exception 11775 #if defined(WITH_JIT) 11776 /* 11777 * If the JIT is actively building a trace we need to make sure 11778 * that the field is fully resolved before including this instruction. 11779 */ 11780 bl common_verifyField 11781 #endif 11782 b .LOP_SGET_BOOLEAN_finish 11783 11784 /* continuation for OP_SGET_BYTE */ 11785 11786 /* 11787 * Continuation if the field has not yet been resolved. 11788 * r1: BBBB field ref 11789 * r10: dvmDex->pResFields 11790 */ 11791 .LOP_SGET_BYTE_resolve: 11792 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11793 #if defined(WITH_JIT) 11794 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11795 #endif 11796 EXPORT_PC() @ resolve() could throw, so export now 11797 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11798 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11799 cmp r0, #0 @ success? 11800 beq common_exceptionThrown @ no, handle exception 11801 #if defined(WITH_JIT) 11802 /* 11803 * If the JIT is actively building a trace we need to make sure 11804 * that the field is fully resolved before including this instruction. 11805 */ 11806 bl common_verifyField 11807 #endif 11808 b .LOP_SGET_BYTE_finish 11809 11810 /* continuation for OP_SGET_CHAR */ 11811 11812 /* 11813 * Continuation if the field has not yet been resolved. 11814 * r1: BBBB field ref 11815 * r10: dvmDex->pResFields 11816 */ 11817 .LOP_SGET_CHAR_resolve: 11818 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11819 #if defined(WITH_JIT) 11820 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11821 #endif 11822 EXPORT_PC() @ resolve() could throw, so export now 11823 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11824 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11825 cmp r0, #0 @ success? 11826 beq common_exceptionThrown @ no, handle exception 11827 #if defined(WITH_JIT) 11828 /* 11829 * If the JIT is actively building a trace we need to make sure 11830 * that the field is fully resolved before including this instruction. 11831 */ 11832 bl common_verifyField 11833 #endif 11834 b .LOP_SGET_CHAR_finish 11835 11836 /* continuation for OP_SGET_SHORT */ 11837 11838 /* 11839 * Continuation if the field has not yet been resolved. 11840 * r1: BBBB field ref 11841 * r10: dvmDex->pResFields 11842 */ 11843 .LOP_SGET_SHORT_resolve: 11844 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11845 #if defined(WITH_JIT) 11846 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11847 #endif 11848 EXPORT_PC() @ resolve() could throw, so export now 11849 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11850 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11851 cmp r0, #0 @ success? 11852 beq common_exceptionThrown @ no, handle exception 11853 #if defined(WITH_JIT) 11854 /* 11855 * If the JIT is actively building a trace we need to make sure 11856 * that the field is fully resolved before including this instruction. 11857 */ 11858 bl common_verifyField 11859 #endif 11860 b .LOP_SGET_SHORT_finish 11861 11862 /* continuation for OP_SPUT */ 11863 11864 /* 11865 * Continuation if the field has not yet been resolved. 11866 * r1: BBBB field ref 11867 * r10: dvmDex->pResFields 11868 */ 11869 .LOP_SPUT_resolve: 11870 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11871 #if defined(WITH_JIT) 11872 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11873 #endif 11874 EXPORT_PC() @ resolve() could throw, so export now 11875 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11876 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11877 cmp r0, #0 @ success? 11878 beq common_exceptionThrown @ no, handle exception 11879 #if defined(WITH_JIT) 11880 /* 11881 * If the JIT is actively building a trace we need to make sure 11882 * that the field is fully resolved before including this instruction. 11883 */ 11884 bl common_verifyField 11885 #endif 11886 b .LOP_SPUT_finish @ resume 11887 11888 /* continuation for OP_SPUT_WIDE */ 11889 11890 /* 11891 * Continuation if the field has not yet been resolved. 11892 * r1: BBBB field ref 11893 * r9: &fp[AA] 11894 * r10: dvmDex->pResFields 11895 * 11896 * Returns StaticField pointer in r2. 11897 */ 11898 .LOP_SPUT_WIDE_resolve: 11899 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11900 #if defined(WITH_JIT) 11901 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11902 #endif 11903 EXPORT_PC() @ resolve() could throw, so export now 11904 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11905 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11906 cmp r0, #0 @ success? 11907 mov r2, r0 @ copy to r2 11908 beq common_exceptionThrown @ no, handle exception 11909 #if defined(WITH_JIT) 11910 /* 11911 * If the JIT is actively building a trace we need to make sure 11912 * that the field is fully resolved before including this instruction. 11913 */ 11914 bl common_verifyField 11915 #endif 11916 b .LOP_SPUT_WIDE_finish @ resume 11917 11918 /* continuation for OP_SPUT_OBJECT */ 11919 11920 11921 .LOP_SPUT_OBJECT_end: 11922 str r1, [r0, #offStaticField_value] @ field<- vAA 11923 @ no-op 11924 cmp r1, #0 @ stored a null object? 11925 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 11926 GOTO_OPCODE(ip) @ jump to next instruction 11927 11928 /* Continuation if the field has not yet been resolved. 11929 * r1: BBBB field ref 11930 * r10: dvmDex->pResFields 11931 */ 11932 .LOP_SPUT_OBJECT_resolve: 11933 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11934 #if defined(WITH_JIT) 11935 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11936 #endif 11937 EXPORT_PC() @ resolve() could throw, so export now 11938 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11939 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11940 cmp r0, #0 @ success? 11941 beq common_exceptionThrown @ no, handle exception 11942 #if defined(WITH_JIT) 11943 /* 11944 * If the JIT is actively building a trace we need to make sure 11945 * that the field is fully resolved before including this instruction. 11946 */ 11947 bl common_verifyField 11948 #endif 11949 b .LOP_SPUT_OBJECT_finish @ resume 11950 11951 11952 /* continuation for OP_SPUT_BOOLEAN */ 11953 11954 /* 11955 * Continuation if the field has not yet been resolved. 11956 * r1: BBBB field ref 11957 * r10: dvmDex->pResFields 11958 */ 11959 .LOP_SPUT_BOOLEAN_resolve: 11960 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11961 #if defined(WITH_JIT) 11962 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11963 #endif 11964 EXPORT_PC() @ resolve() could throw, so export now 11965 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11966 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11967 cmp r0, #0 @ success? 11968 beq common_exceptionThrown @ no, handle exception 11969 #if defined(WITH_JIT) 11970 /* 11971 * If the JIT is actively building a trace we need to make sure 11972 * that the field is fully resolved before including this instruction. 11973 */ 11974 bl common_verifyField 11975 #endif 11976 b .LOP_SPUT_BOOLEAN_finish @ resume 11977 11978 /* continuation for OP_SPUT_BYTE */ 11979 11980 /* 11981 * Continuation if the field has not yet been resolved. 11982 * r1: BBBB field ref 11983 * r10: dvmDex->pResFields 11984 */ 11985 .LOP_SPUT_BYTE_resolve: 11986 ldr r2, [rSELF, #offThread_method] @ r2<- current method 11987 #if defined(WITH_JIT) 11988 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 11989 #endif 11990 EXPORT_PC() @ resolve() could throw, so export now 11991 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 11992 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 11993 cmp r0, #0 @ success? 11994 beq common_exceptionThrown @ no, handle exception 11995 #if defined(WITH_JIT) 11996 /* 11997 * If the JIT is actively building a trace we need to make sure 11998 * that the field is fully resolved before including this instruction. 11999 */ 12000 bl common_verifyField 12001 #endif 12002 b .LOP_SPUT_BYTE_finish @ resume 12003 12004 /* continuation for OP_SPUT_CHAR */ 12005 12006 /* 12007 * Continuation if the field has not yet been resolved. 12008 * r1: BBBB field ref 12009 * r10: dvmDex->pResFields 12010 */ 12011 .LOP_SPUT_CHAR_resolve: 12012 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12013 #if defined(WITH_JIT) 12014 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12015 #endif 12016 EXPORT_PC() @ resolve() could throw, so export now 12017 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12018 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12019 cmp r0, #0 @ success? 12020 beq common_exceptionThrown @ no, handle exception 12021 #if defined(WITH_JIT) 12022 /* 12023 * If the JIT is actively building a trace we need to make sure 12024 * that the field is fully resolved before including this instruction. 12025 */ 12026 bl common_verifyField 12027 #endif 12028 b .LOP_SPUT_CHAR_finish @ resume 12029 12030 /* continuation for OP_SPUT_SHORT */ 12031 12032 /* 12033 * Continuation if the field has not yet been resolved. 12034 * r1: BBBB field ref 12035 * r10: dvmDex->pResFields 12036 */ 12037 .LOP_SPUT_SHORT_resolve: 12038 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12039 #if defined(WITH_JIT) 12040 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12041 #endif 12042 EXPORT_PC() @ resolve() could throw, so export now 12043 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12044 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12045 cmp r0, #0 @ success? 12046 beq common_exceptionThrown @ no, handle exception 12047 #if defined(WITH_JIT) 12048 /* 12049 * If the JIT is actively building a trace we need to make sure 12050 * that the field is fully resolved before including this instruction. 12051 */ 12052 bl common_verifyField 12053 #endif 12054 b .LOP_SPUT_SHORT_finish @ resume 12055 12056 /* continuation for OP_INVOKE_VIRTUAL */ 12057 12058 /* 12059 * At this point: 12060 * r0 = resolved base method 12061 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 12062 */ 12063 .LOP_INVOKE_VIRTUAL_continue: 12064 GET_VREG(r9, r10) @ r9<- "this" ptr 12065 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12066 cmp r9, #0 @ is "this" null? 12067 beq common_errNullObject @ null "this", throw exception 12068 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz 12069 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 12070 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 12071 bl common_invokeMethodNoRange @ (r0=method, r9="this") 12072 12073 /* continuation for OP_INVOKE_SUPER */ 12074 12075 /* 12076 * At this point: 12077 * r0 = resolved base method 12078 * r10 = method->clazz 12079 */ 12080 .LOP_INVOKE_SUPER_continue: 12081 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super 12082 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12083 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 12084 EXPORT_PC() @ must export for invoke 12085 cmp r2, r3 @ compare (methodIndex, vtableCount) 12086 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 12087 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 12088 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 12089 bl common_invokeMethodNoRange @ continue on 12090 12091 .LOP_INVOKE_SUPER_resolve: 12092 mov r0, r10 @ r0<- method->clazz 12093 mov r2, #METHOD_VIRTUAL @ resolver method type 12094 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12095 cmp r0, #0 @ got null? 12096 bne .LOP_INVOKE_SUPER_continue @ no, continue 12097 b common_exceptionThrown @ yes, handle exception 12098 12099 /* 12100 * Throw a NoSuchMethodError with the method name as the message. 12101 * r0 = resolved base method 12102 */ 12103 .LOP_INVOKE_SUPER_nsm: 12104 ldr r1, [r0, #offMethod_name] @ r1<- method name 12105 b common_errNoSuchMethod 12106 12107 /* continuation for OP_INVOKE_DIRECT */ 12108 12109 /* 12110 * On entry: 12111 * r1 = reference (BBBB or CCCC) 12112 * r10 = "this" register 12113 */ 12114 .LOP_INVOKE_DIRECT_resolve: 12115 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12116 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12117 mov r2, #METHOD_DIRECT @ resolver method type 12118 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12119 cmp r0, #0 @ got null? 12120 bne .LOP_INVOKE_DIRECT_finish @ no, continue 12121 b common_exceptionThrown @ yes, handle exception 12122 12123 /* continuation for OP_INVOKE_STATIC */ 12124 12125 12126 .LOP_INVOKE_STATIC_resolve: 12127 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12128 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12129 mov r2, #METHOD_STATIC @ resolver method type 12130 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12131 cmp r0, #0 @ got null? 12132 #if defined(WITH_JIT) 12133 /* 12134 * Check to see if we're actively building a trace. If so, 12135 * we need to keep this instruction out of it. 12136 * r10: &resolved_methodToCall 12137 */ 12138 ldrh r2, [rSELF, #offThread_subMode] 12139 beq common_exceptionThrown @ null, handle exception 12140 ands r2, #kSubModeJitTraceBuild @ trace under construction? 12141 beq common_invokeMethodNoRange @ no (r0=method, r9="this") 12142 ldr r1, [r10] @ reload resolved method 12143 cmp r1, #0 @ finished resolving? 12144 bne common_invokeMethodNoRange @ yes (r0=method, r9="this") 12145 mov r10, r0 @ preserve method 12146 mov r0, rSELF 12147 mov r1, rPC 12148 bl dvmJitEndTraceSelect @ (self, pc) 12149 mov r0, r10 12150 b common_invokeMethodNoRange @ whew, finally! 12151 #else 12152 bne common_invokeMethodNoRange @ (r0=method, r9="this") 12153 b common_exceptionThrown @ yes, handle exception 12154 #endif 12155 12156 /* continuation for OP_INVOKE_VIRTUAL_RANGE */ 12157 12158 /* 12159 * At this point: 12160 * r0 = resolved base method 12161 * r10 = C or CCCC (index of first arg, which is the "this" ptr) 12162 */ 12163 .LOP_INVOKE_VIRTUAL_RANGE_continue: 12164 GET_VREG(r9, r10) @ r9<- "this" ptr 12165 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12166 cmp r9, #0 @ is "this" null? 12167 beq common_errNullObject @ null "this", throw exception 12168 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz 12169 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 12170 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 12171 bl common_invokeMethodRange @ (r0=method, r9="this") 12172 12173 /* continuation for OP_INVOKE_SUPER_RANGE */ 12174 12175 /* 12176 * At this point: 12177 * r0 = resolved base method 12178 * r10 = method->clazz 12179 */ 12180 .LOP_INVOKE_SUPER_RANGE_continue: 12181 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super 12182 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 12183 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 12184 EXPORT_PC() @ must export for invoke 12185 cmp r2, r3 @ compare (methodIndex, vtableCount) 12186 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 12187 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 12188 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 12189 bl common_invokeMethodRange @ continue on 12190 12191 .LOP_INVOKE_SUPER_RANGE_resolve: 12192 mov r0, r10 @ r0<- method->clazz 12193 mov r2, #METHOD_VIRTUAL @ resolver method type 12194 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12195 cmp r0, #0 @ got null? 12196 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 12197 b common_exceptionThrown @ yes, handle exception 12198 12199 /* 12200 * Throw a NoSuchMethodError with the method name as the message. 12201 * r0 = resolved base method 12202 */ 12203 .LOP_INVOKE_SUPER_RANGE_nsm: 12204 ldr r1, [r0, #offMethod_name] @ r1<- method name 12205 b common_errNoSuchMethod 12206 12207 /* continuation for OP_INVOKE_DIRECT_RANGE */ 12208 12209 /* 12210 * On entry: 12211 * r1 = reference (BBBB or CCCC) 12212 * r10 = "this" register 12213 */ 12214 .LOP_INVOKE_DIRECT_RANGE_resolve: 12215 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12216 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12217 mov r2, #METHOD_DIRECT @ resolver method type 12218 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12219 cmp r0, #0 @ got null? 12220 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 12221 b common_exceptionThrown @ yes, handle exception 12222 12223 /* continuation for OP_INVOKE_STATIC_RANGE */ 12224 12225 12226 .LOP_INVOKE_STATIC_RANGE_resolve: 12227 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12228 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12229 mov r2, #METHOD_STATIC @ resolver method type 12230 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 12231 cmp r0, #0 @ got null? 12232 #if defined(WITH_JIT) 12233 /* 12234 * Check to see if we're actively building a trace. If so, 12235 * we need to keep this instruction out of it. 12236 * r10: &resolved_methodToCall 12237 */ 12238 ldrh r2, [rSELF, #offThread_subMode] 12239 beq common_exceptionThrown @ null, handle exception 12240 ands r2, #kSubModeJitTraceBuild @ trace under construction? 12241 beq common_invokeMethodRange @ no (r0=method, r9="this") 12242 ldr r1, [r10] @ reload resolved method 12243 cmp r1, #0 @ finished resolving? 12244 bne common_invokeMethodRange @ yes (r0=method, r9="this") 12245 mov r10, r0 @ preserve method 12246 mov r0, rSELF 12247 mov r1, rPC 12248 bl dvmJitEndTraceSelect @ (self, pc) 12249 mov r0, r10 12250 b common_invokeMethodRange @ whew, finally! 12251 #else 12252 bne common_invokeMethodRange @ (r0=method, r9="this") 12253 b common_exceptionThrown @ yes, handle exception 12254 #endif 12255 12256 /* continuation for OP_FLOAT_TO_LONG */ 12257 /* 12258 * Convert the float in r0 to a long in r0/r1. 12259 * 12260 * We have to clip values to long min/max per the specification. The 12261 * expected common case is a "reasonable" value that converts directly 12262 * to modest integer. The EABI convert function isn't doing this for us. 12263 */ 12264 f2l_doconv: 12265 stmfd sp!, {r4, lr} 12266 mov r1, #0x5f000000 @ (float)maxlong 12267 mov r4, r0 12268 bl __aeabi_fcmpge @ is arg >= maxlong? 12269 cmp r0, #0 @ nonzero == yes 12270 mvnne r0, #0 @ return maxlong (7fffffff) 12271 mvnne r1, #0x80000000 12272 ldmnefd sp!, {r4, pc} 12273 12274 mov r0, r4 @ recover arg 12275 mov r1, #0xdf000000 @ (float)minlong 12276 bl __aeabi_fcmple @ is arg <= minlong? 12277 cmp r0, #0 @ nonzero == yes 12278 movne r0, #0 @ return minlong (80000000) 12279 movne r1, #0x80000000 12280 ldmnefd sp!, {r4, pc} 12281 12282 mov r0, r4 @ recover arg 12283 mov r1, r4 12284 bl __aeabi_fcmpeq @ is arg == self? 12285 cmp r0, #0 @ zero == no 12286 moveq r1, #0 @ return zero for NaN 12287 ldmeqfd sp!, {r4, pc} 12288 12289 mov r0, r4 @ recover arg 12290 bl __aeabi_f2lz @ convert float to long 12291 ldmfd sp!, {r4, pc} 12292 12293 /* continuation for OP_DOUBLE_TO_LONG */ 12294 /* 12295 * Convert the double in r0/r1 to a long in r0/r1. 12296 * 12297 * We have to clip values to long min/max per the specification. The 12298 * expected common case is a "reasonable" value that converts directly 12299 * to modest integer. The EABI convert function isn't doing this for us. 12300 */ 12301 d2l_doconv: 12302 stmfd sp!, {r4, r5, lr} @ save regs 12303 mov r3, #0x43000000 @ maxlong, as a double (high word) 12304 add r3, #0x00e00000 @ 0x43e00000 12305 mov r2, #0 @ maxlong, as a double (low word) 12306 sub sp, sp, #4 @ align for EABI 12307 mov r4, r0 @ save a copy of r0 12308 mov r5, r1 @ and r1 12309 bl __aeabi_dcmpge @ is arg >= maxlong? 12310 cmp r0, #0 @ nonzero == yes 12311 mvnne r0, #0 @ return maxlong (7fffffffffffffff) 12312 mvnne r1, #0x80000000 12313 bne 1f 12314 12315 mov r0, r4 @ recover arg 12316 mov r1, r5 12317 mov r3, #0xc3000000 @ minlong, as a double (high word) 12318 add r3, #0x00e00000 @ 0xc3e00000 12319 mov r2, #0 @ minlong, as a double (low word) 12320 bl __aeabi_dcmple @ is arg <= minlong? 12321 cmp r0, #0 @ nonzero == yes 12322 movne r0, #0 @ return minlong (8000000000000000) 12323 movne r1, #0x80000000 12324 bne 1f 12325 12326 mov r0, r4 @ recover arg 12327 mov r1, r5 12328 mov r2, r4 @ compare against self 12329 mov r3, r5 12330 bl __aeabi_dcmpeq @ is arg == self? 12331 cmp r0, #0 @ zero == no 12332 moveq r1, #0 @ return zero for NaN 12333 beq 1f 12334 12335 mov r0, r4 @ recover arg 12336 mov r1, r5 12337 bl __aeabi_d2lz @ convert double to long 12338 12339 1: 12340 add sp, sp, #4 12341 ldmfd sp!, {r4, r5, pc} 12342 12343 /* continuation for OP_MUL_LONG */ 12344 12345 .LOP_MUL_LONG_finish: 12346 GET_INST_OPCODE(ip) @ extract opcode from rINST 12347 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 12348 GOTO_OPCODE(ip) @ jump to next instruction 12349 12350 /* continuation for OP_SHL_LONG */ 12351 12352 .LOP_SHL_LONG_finish: 12353 mov r0, r0, asl r2 @ r0<- r0 << r2 12354 GET_INST_OPCODE(ip) @ extract opcode from rINST 12355 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12356 GOTO_OPCODE(ip) @ jump to next instruction 12357 12358 /* continuation for OP_SHR_LONG */ 12359 12360 .LOP_SHR_LONG_finish: 12361 mov r1, r1, asr r2 @ r1<- r1 >> r2 12362 GET_INST_OPCODE(ip) @ extract opcode from rINST 12363 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12364 GOTO_OPCODE(ip) @ jump to next instruction 12365 12366 /* continuation for OP_USHR_LONG */ 12367 12368 .LOP_USHR_LONG_finish: 12369 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 12370 GET_INST_OPCODE(ip) @ extract opcode from rINST 12371 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12372 GOTO_OPCODE(ip) @ jump to next instruction 12373 12374 /* continuation for OP_SHL_LONG_2ADDR */ 12375 12376 .LOP_SHL_LONG_2ADDR_finish: 12377 GET_INST_OPCODE(ip) @ extract opcode from rINST 12378 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12379 GOTO_OPCODE(ip) @ jump to next instruction 12380 12381 /* continuation for OP_SHR_LONG_2ADDR */ 12382 12383 .LOP_SHR_LONG_2ADDR_finish: 12384 GET_INST_OPCODE(ip) @ extract opcode from rINST 12385 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12386 GOTO_OPCODE(ip) @ jump to next instruction 12387 12388 /* continuation for OP_USHR_LONG_2ADDR */ 12389 12390 .LOP_USHR_LONG_2ADDR_finish: 12391 GET_INST_OPCODE(ip) @ extract opcode from rINST 12392 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 12393 GOTO_OPCODE(ip) @ jump to next instruction 12394 12395 /* continuation for OP_IGET_VOLATILE */ 12396 12397 /* 12398 * Currently: 12399 * r0 holds resolved field 12400 * r9 holds object 12401 */ 12402 .LOP_IGET_VOLATILE_finish: 12403 @bl common_squeak0 12404 cmp r9, #0 @ check object for null 12405 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12406 beq common_errNullObject @ object was null 12407 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12408 SMP_DMB @ acquiring load 12409 mov r2, rINST, lsr #8 @ r2<- A+ 12410 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12411 and r2, r2, #15 @ r2<- A 12412 GET_INST_OPCODE(ip) @ extract opcode from rINST 12413 SET_VREG(r0, r2) @ fp[A]<- r0 12414 GOTO_OPCODE(ip) @ jump to next instruction 12415 12416 /* continuation for OP_IPUT_VOLATILE */ 12417 12418 /* 12419 * Currently: 12420 * r0 holds resolved field 12421 * r9 holds object 12422 */ 12423 .LOP_IPUT_VOLATILE_finish: 12424 @bl common_squeak0 12425 mov r1, rINST, lsr #8 @ r1<- A+ 12426 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12427 and r1, r1, #15 @ r1<- A 12428 cmp r9, #0 @ check object for null 12429 GET_VREG(r0, r1) @ r0<- fp[A] 12430 beq common_errNullObject @ object was null 12431 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12432 GET_INST_OPCODE(ip) @ extract opcode from rINST 12433 SMP_DMB_ST @ releasing store 12434 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 12435 SMP_DMB 12436 GOTO_OPCODE(ip) @ jump to next instruction 12437 12438 /* continuation for OP_SGET_VOLATILE */ 12439 12440 /* 12441 * Continuation if the field has not yet been resolved. 12442 * r1: BBBB field ref 12443 * r10: dvmDex->pResFields 12444 */ 12445 .LOP_SGET_VOLATILE_resolve: 12446 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12447 #if defined(WITH_JIT) 12448 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12449 #endif 12450 EXPORT_PC() @ resolve() could throw, so export now 12451 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12452 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12453 cmp r0, #0 @ success? 12454 beq common_exceptionThrown @ no, handle exception 12455 #if defined(WITH_JIT) 12456 /* 12457 * If the JIT is actively building a trace we need to make sure 12458 * that the field is fully resolved before including this instruction. 12459 */ 12460 bl common_verifyField 12461 #endif 12462 b .LOP_SGET_VOLATILE_finish 12463 12464 /* continuation for OP_SPUT_VOLATILE */ 12465 12466 /* 12467 * Continuation if the field has not yet been resolved. 12468 * r1: BBBB field ref 12469 * r10: dvmDex->pResFields 12470 */ 12471 .LOP_SPUT_VOLATILE_resolve: 12472 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12473 #if defined(WITH_JIT) 12474 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12475 #endif 12476 EXPORT_PC() @ resolve() could throw, so export now 12477 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12478 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12479 cmp r0, #0 @ success? 12480 beq common_exceptionThrown @ no, handle exception 12481 #if defined(WITH_JIT) 12482 /* 12483 * If the JIT is actively building a trace we need to make sure 12484 * that the field is fully resolved before including this instruction. 12485 */ 12486 bl common_verifyField 12487 #endif 12488 b .LOP_SPUT_VOLATILE_finish @ resume 12489 12490 /* continuation for OP_IGET_OBJECT_VOLATILE */ 12491 12492 /* 12493 * Currently: 12494 * r0 holds resolved field 12495 * r9 holds object 12496 */ 12497 .LOP_IGET_OBJECT_VOLATILE_finish: 12498 @bl common_squeak0 12499 cmp r9, #0 @ check object for null 12500 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12501 beq common_errNullObject @ object was null 12502 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 12503 SMP_DMB @ acquiring load 12504 mov r2, rINST, lsr #8 @ r2<- A+ 12505 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12506 and r2, r2, #15 @ r2<- A 12507 GET_INST_OPCODE(ip) @ extract opcode from rINST 12508 SET_VREG(r0, r2) @ fp[A]<- r0 12509 GOTO_OPCODE(ip) @ jump to next instruction 12510 12511 /* continuation for OP_IGET_WIDE_VOLATILE */ 12512 12513 /* 12514 * Currently: 12515 * r0 holds resolved field 12516 * r9 holds object 12517 */ 12518 .LOP_IGET_WIDE_VOLATILE_finish: 12519 cmp r9, #0 @ check object for null 12520 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12521 beq common_errNullObject @ object was null 12522 .if 1 12523 add r0, r9, r3 @ r0<- address of field 12524 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 12525 .else 12526 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 12527 .endif 12528 mov r2, rINST, lsr #8 @ r2<- A+ 12529 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12530 and r2, r2, #15 @ r2<- A 12531 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 12532 GET_INST_OPCODE(ip) @ extract opcode from rINST 12533 stmia r3, {r0-r1} @ fp[A]<- r0/r1 12534 GOTO_OPCODE(ip) @ jump to next instruction 12535 12536 /* continuation for OP_IPUT_WIDE_VOLATILE */ 12537 12538 /* 12539 * Currently: 12540 * r0 holds resolved field 12541 * r9 holds object 12542 */ 12543 .LOP_IPUT_WIDE_VOLATILE_finish: 12544 mov r2, rINST, lsr #8 @ r2<- A+ 12545 cmp r9, #0 @ check object for null 12546 and r2, r2, #15 @ r2<- A 12547 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12548 add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 12549 beq common_errNullObject @ object was null 12550 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12551 ldmia r2, {r0-r1} @ r0/r1<- fp[A] 12552 GET_INST_OPCODE(r10) @ extract opcode from rINST 12553 .if 1 12554 add r2, r9, r3 @ r2<- target address 12555 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 12556 .else 12557 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 12558 .endif 12559 GOTO_OPCODE(r10) @ jump to next instruction 12560 12561 /* continuation for OP_SGET_WIDE_VOLATILE */ 12562 12563 /* 12564 * Continuation if the field has not yet been resolved. 12565 * r1: BBBB field ref 12566 * r10: dvmDex->pResFields 12567 * 12568 * Returns StaticField pointer in r0. 12569 */ 12570 .LOP_SGET_WIDE_VOLATILE_resolve: 12571 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12572 #if defined(WITH_JIT) 12573 add r10, r10, r1, lsl #2 @ r1<- &dvmDex->pResFields[field] 12574 #endif 12575 EXPORT_PC() @ resolve() could throw, so export now 12576 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12577 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12578 cmp r0, #0 @ success? 12579 beq common_exceptionThrown @ no, handle exception 12580 #if defined(WITH_JIT) 12581 /* 12582 * If the JIT is actively building a trace we need to make sure 12583 * that the field is fully resolved before including this instruction. 12584 */ 12585 bl common_verifyField 12586 #endif 12587 b .LOP_SGET_WIDE_VOLATILE_finish @ resume 12588 12589 /* continuation for OP_SPUT_WIDE_VOLATILE */ 12590 12591 /* 12592 * Continuation if the field has not yet been resolved. 12593 * r1: BBBB field ref 12594 * r9: &fp[AA] 12595 * r10: dvmDex->pResFields 12596 * 12597 * Returns StaticField pointer in r2. 12598 */ 12599 .LOP_SPUT_WIDE_VOLATILE_resolve: 12600 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12601 #if defined(WITH_JIT) 12602 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12603 #endif 12604 EXPORT_PC() @ resolve() could throw, so export now 12605 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12606 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12607 cmp r0, #0 @ success? 12608 mov r2, r0 @ copy to r2 12609 beq common_exceptionThrown @ no, handle exception 12610 #if defined(WITH_JIT) 12611 /* 12612 * If the JIT is actively building a trace we need to make sure 12613 * that the field is fully resolved before including this instruction. 12614 */ 12615 bl common_verifyField 12616 #endif 12617 b .LOP_SPUT_WIDE_VOLATILE_finish @ resume 12618 12619 /* continuation for OP_EXECUTE_INLINE */ 12620 12621 /* 12622 * Extract args, call function. 12623 * r0 = #of args (0-4) 12624 * r10 = call index 12625 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12626 * 12627 * Other ideas: 12628 * - Use a jump table from the main piece to jump directly into the 12629 * AND/LDR pairs. Costs a data load, saves a branch. 12630 * - Have five separate pieces that do the loading, so we can work the 12631 * interleave a little better. Increases code size. 12632 */ 12633 .LOP_EXECUTE_INLINE_continue: 12634 rsb r0, r0, #4 @ r0<- 4-r0 12635 FETCH(rINST, 2) @ rINST<- FEDC 12636 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12637 bl common_abort @ (skipped due to ARM prefetch) 12638 4: and ip, rINST, #0xf000 @ isolate F 12639 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 12640 3: and ip, rINST, #0x0f00 @ isolate E 12641 ldr r2, [rFP, ip, lsr #6] @ r2<- vE 12642 2: and ip, rINST, #0x00f0 @ isolate D 12643 ldr r1, [rFP, ip, lsr #2] @ r1<- vD 12644 1: and ip, rINST, #0x000f @ isolate C 12645 ldr r0, [rFP, ip, lsl #2] @ r0<- vC 12646 0: 12647 ldr rINST, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 12648 ldr pc, [rINST, r10, lsl #4] @ sizeof=16, "func" is first entry 12649 @ (not reached) 12650 12651 /* 12652 * We're debugging or profiling. 12653 * r10: opIndex 12654 */ 12655 .LOP_EXECUTE_INLINE_debugmode: 12656 mov r0, r10 12657 bl dvmResolveInlineNative 12658 cmp r0, #0 @ did it resolve? 12659 beq .LOP_EXECUTE_INLINE_resume @ no, just move on 12660 mov r9, r0 @ remember method 12661 mov r1, rSELF 12662 bl dvmFastMethodTraceEnter @ (method, self) 12663 add r1, rSELF, #offThread_retval@ r1<- &self->retval 12664 sub sp, sp, #8 @ make room for arg, +64 bit align 12665 mov r0, rINST, lsr #12 @ r0<- B 12666 str r1, [sp] @ push &self->retval 12667 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 12668 mov rINST, r0 @ save result of inline 12669 add sp, sp, #8 @ pop stack 12670 mov r0, r9 @ r0<- method 12671 mov r1, rSELF 12672 bl dvmFastNativeMethodTraceExit @ (method, self) 12673 cmp rINST, #0 @ test boolean result of inline 12674 beq common_exceptionThrown @ returned false, handle exception 12675 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 12676 GET_INST_OPCODE(ip) @ extract opcode from rINST 12677 GOTO_OPCODE(ip) @ jump to next instruction 12678 12679 12680 12681 12682 .LOP_EXECUTE_INLINE_table: 12683 .word gDvmInlineOpsTable 12684 12685 /* continuation for OP_EXECUTE_INLINE_RANGE */ 12686 12687 /* 12688 * Extract args, call function. 12689 * r0 = #of args (0-4) 12690 * r10 = call index 12691 * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 12692 */ 12693 .LOP_EXECUTE_INLINE_RANGE_continue: 12694 rsb r0, r0, #4 @ r0<- 4-r0 12695 FETCH(r9, 2) @ r9<- CCCC 12696 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 12697 bl common_abort @ (skipped due to ARM prefetch) 12698 4: add ip, r9, #3 @ base+3 12699 GET_VREG(r3, ip) @ r3<- vBase[3] 12700 3: add ip, r9, #2 @ base+2 12701 GET_VREG(r2, ip) @ r2<- vBase[2] 12702 2: add ip, r9, #1 @ base+1 12703 GET_VREG(r1, ip) @ r1<- vBase[1] 12704 1: add ip, r9, #0 @ (nop) 12705 GET_VREG(r0, ip) @ r0<- vBase[0] 12706 0: 12707 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 12708 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry 12709 @ (not reached) 12710 12711 12712 /* 12713 * We're debugging or profiling. 12714 * r10: opIndex 12715 */ 12716 .LOP_EXECUTE_INLINE_RANGE_debugmode: 12717 mov r0, r10 12718 bl dvmResolveInlineNative 12719 cmp r0, #0 @ did it resolve? 12720 beq .LOP_EXECUTE_INLINE_RANGE_resume @ no, just move on 12721 mov r9, r0 @ remember method 12722 mov r1, rSELF 12723 bl dvmFastMethodTraceEnter @ (method, self) 12724 add r1, rSELF, #offThread_retval@ r1<- &self->retval 12725 sub sp, sp, #8 @ make room for arg, +64 bit align 12726 mov r0, rINST, lsr #8 @ r0<- B 12727 mov rINST, r9 @ rINST<- method 12728 str r1, [sp] @ push &self->retval 12729 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 12730 mov r9, r0 @ save result of inline 12731 add sp, sp, #8 @ pop stack 12732 mov r0, rINST @ r0<- method 12733 mov r1, rSELF 12734 bl dvmFastNativeMethodTraceExit @ (method, self) 12735 cmp r9, #0 @ test boolean result of inline 12736 beq common_exceptionThrown @ returned false, handle exception 12737 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 12738 GET_INST_OPCODE(ip) @ extract opcode from rINST 12739 GOTO_OPCODE(ip) @ jump to next instruction 12740 12741 12742 12743 12744 .LOP_EXECUTE_INLINE_RANGE_table: 12745 .word gDvmInlineOpsTable 12746 12747 12748 /* continuation for OP_INVOKE_OBJECT_INIT_RANGE */ 12749 12750 .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal: 12751 EXPORT_PC() @ can throw 12752 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 12753 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception 12754 cmp r0, #0 @ exception pending? 12755 bne common_exceptionThrown @ yes, handle it 12756 b .LOP_INVOKE_OBJECT_INIT_RANGE_finish 12757 12758 /* 12759 * A debugger is attached, so we need to go ahead and do 12760 * this. For simplicity, we'll just jump directly to the 12761 * corresponding handler. Note that we can't use 12762 * rIBASE here because it may be in single-step mode. 12763 * Load the primary table base directly. 12764 */ 12765 .LOP_INVOKE_OBJECT_INIT_RANGE_debugger: 12766 ldr r1, [rSELF, #offThread_mainHandlerTable] 12767 .if 0 12768 mov ip, #OP_INVOKE_DIRECT_JUMBO 12769 .else 12770 mov ip, #OP_INVOKE_DIRECT_RANGE 12771 .endif 12772 GOTO_OPCODE_BASE(r1,ip) @ execute it 12773 12774 /* continuation for OP_IPUT_OBJECT_VOLATILE */ 12775 12776 /* 12777 * Currently: 12778 * r0 holds resolved field 12779 * r9 holds object 12780 */ 12781 .LOP_IPUT_OBJECT_VOLATILE_finish: 12782 @bl common_squeak0 12783 mov r1, rINST, lsr #8 @ r1<- A+ 12784 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 12785 and r1, r1, #15 @ r1<- A 12786 cmp r9, #0 @ check object for null 12787 GET_VREG(r0, r1) @ r0<- fp[A] 12788 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 12789 beq common_errNullObject @ object was null 12790 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 12791 GET_INST_OPCODE(ip) @ extract opcode from rINST 12792 SMP_DMB_ST @ releasing store 12793 str r0, [r9, r3] @ obj.field (32 bits)<- r0 12794 SMP_DMB 12795 cmp r0, #0 @ stored a null reference? 12796 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 12797 GOTO_OPCODE(ip) @ jump to next instruction 12798 12799 /* continuation for OP_SGET_OBJECT_VOLATILE */ 12800 12801 /* 12802 * Continuation if the field has not yet been resolved. 12803 * r1: BBBB field ref 12804 * r10: dvmDex->pResFields 12805 */ 12806 .LOP_SGET_OBJECT_VOLATILE_resolve: 12807 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12808 #if defined(WITH_JIT) 12809 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12810 #endif 12811 EXPORT_PC() @ resolve() could throw, so export now 12812 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12813 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12814 cmp r0, #0 @ success? 12815 beq common_exceptionThrown @ no, handle exception 12816 #if defined(WITH_JIT) 12817 /* 12818 * If the JIT is actively building a trace we need to make sure 12819 * that the field is fully resolved before including this instruction. 12820 */ 12821 bl common_verifyField 12822 #endif 12823 b .LOP_SGET_OBJECT_VOLATILE_finish 12824 12825 /* continuation for OP_SPUT_OBJECT_VOLATILE */ 12826 12827 12828 .LOP_SPUT_OBJECT_VOLATILE_end: 12829 str r1, [r0, #offStaticField_value] @ field<- vAA 12830 SMP_DMB 12831 cmp r1, #0 @ stored a null object? 12832 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 12833 GOTO_OPCODE(ip) @ jump to next instruction 12834 12835 /* Continuation if the field has not yet been resolved. 12836 * r1: BBBB field ref 12837 * r10: dvmDex->pResFields 12838 */ 12839 .LOP_SPUT_OBJECT_VOLATILE_resolve: 12840 ldr r2, [rSELF, #offThread_method] @ r2<- current method 12841 #if defined(WITH_JIT) 12842 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 12843 #endif 12844 EXPORT_PC() @ resolve() could throw, so export now 12845 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 12846 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 12847 cmp r0, #0 @ success? 12848 beq common_exceptionThrown @ no, handle exception 12849 #if defined(WITH_JIT) 12850 /* 12851 * If the JIT is actively building a trace we need to make sure 12852 * that the field is fully resolved before including this instruction. 12853 */ 12854 bl common_verifyField 12855 #endif 12856 b .LOP_SPUT_OBJECT_VOLATILE_finish @ resume 12857 12858 12859 /* continuation for OP_CONST_CLASS_JUMBO */ 12860 12861 /* 12862 * Continuation if the Class has not yet been resolved. 12863 * r1: AAAAAAAA (Class ref) 12864 * r9: target register 12865 */ 12866 .LOP_CONST_CLASS_JUMBO_resolve: 12867 EXPORT_PC() 12868 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12869 mov r2, #1 @ r2<- true 12870 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12871 bl dvmResolveClass @ r0<- Class reference 12872 cmp r0, #0 @ failed? 12873 beq common_exceptionThrown @ yup, handle the exception 12874 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12875 GET_INST_OPCODE(ip) @ extract opcode from rINST 12876 SET_VREG(r0, r9) @ vBBBB<- r0 12877 GOTO_OPCODE(ip) @ jump to next instruction 12878 12879 /* continuation for OP_CHECK_CAST_JUMBO */ 12880 12881 /* 12882 * Trivial test failed, need to perform full check. This is common. 12883 * r0 holds obj->clazz 12884 * r1 holds desired class resolved from AAAAAAAA 12885 * r9 holds object 12886 */ 12887 .LOP_CHECK_CAST_JUMBO_fullcheck: 12888 mov r10, r1 @ avoid ClassObject getting clobbered 12889 bl dvmInstanceofNonTrivial @ r0<- boolean result 12890 cmp r0, #0 @ failed? 12891 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success 12892 12893 @ A cast has failed. We need to throw a ClassCastException. 12894 EXPORT_PC() @ about to throw 12895 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class) 12896 mov r1, r10 @ r1<- desired class 12897 bl dvmThrowClassCastException 12898 b common_exceptionThrown 12899 12900 /* 12901 * Advance PC and get the next opcode. 12902 */ 12903 .LOP_CHECK_CAST_JUMBO_okay: 12904 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 12905 GET_INST_OPCODE(ip) @ extract opcode from rINST 12906 GOTO_OPCODE(ip) @ jump to next instruction 12907 12908 /* 12909 * Resolution required. This is the least-likely path. 12910 * 12911 * r2 holds AAAAAAAA 12912 * r9 holds object 12913 */ 12914 .LOP_CHECK_CAST_JUMBO_resolve: 12915 EXPORT_PC() @ resolve() could throw 12916 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 12917 mov r1, r2 @ r1<- AAAAAAAA 12918 mov r2, #0 @ r2<- false 12919 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 12920 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12921 cmp r0, #0 @ got null? 12922 beq common_exceptionThrown @ yes, handle exception 12923 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12924 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 12925 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off 12926 12927 /* continuation for OP_INSTANCE_OF_JUMBO */ 12928 12929 /* 12930 * Class resolved, determine type of check necessary. This is common. 12931 * r0 holds obj->clazz 12932 * r1 holds class resolved from AAAAAAAA 12933 * r9 holds BBBB 12934 */ 12935 .LOP_INSTANCE_OF_JUMBO_resolved: 12936 cmp r0, r1 @ same class (trivial success)? 12937 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish 12938 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck 12939 12940 /* 12941 * Trivial test failed, need to perform full check. This is common. 12942 * r0 holds obj->clazz 12943 * r1 holds class resolved from AAAAAAAA 12944 * r9 holds BBBB 12945 */ 12946 .LOP_INSTANCE_OF_JUMBO_fullcheck: 12947 bl dvmInstanceofNonTrivial @ r0<- boolean result 12948 @ fall through to OP_INSTANCE_OF_JUMBO_store 12949 12950 /* 12951 * r0 holds boolean result 12952 * r9 holds BBBB 12953 */ 12954 .LOP_INSTANCE_OF_JUMBO_store: 12955 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12956 SET_VREG(r0, r9) @ vBBBB<- r0 12957 GET_INST_OPCODE(ip) @ extract opcode from rINST 12958 GOTO_OPCODE(ip) @ jump to next instruction 12959 12960 /* 12961 * Trivial test succeeded, save and bail. 12962 * r9 holds BBBB 12963 */ 12964 .LOP_INSTANCE_OF_JUMBO_trivial: 12965 mov r0, #1 @ indicate success 12966 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper 12967 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 12968 SET_VREG(r0, r9) @ vBBBB<- r0 12969 GET_INST_OPCODE(ip) @ extract opcode from rINST 12970 GOTO_OPCODE(ip) @ jump to next instruction 12971 12972 /* 12973 * Resolution required. This is the least-likely path. 12974 * 12975 * r3 holds AAAAAAAA 12976 * r9 holds BBBB 12977 */ 12978 12979 .LOP_INSTANCE_OF_JUMBO_resolve: 12980 EXPORT_PC() @ resolve() could throw 12981 ldr r0, [rSELF, #offThread_method] @ r0<- self->method 12982 mov r1, r3 @ r1<- AAAAAAAA 12983 mov r2, #1 @ r2<- true 12984 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 12985 bl dvmResolveClass @ r0<- resolved ClassObject ptr 12986 cmp r0, #0 @ got null? 12987 beq common_exceptionThrown @ yes, handle exception 12988 FETCH(r3, 4) @ r3<- vCCCC 12989 mov r1, r0 @ r1<- class resolved from AAAAAAAA 12990 GET_VREG(r0, r3) @ r0<- vCCCC (object) 12991 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 12992 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off 12993 12994 /* continuation for OP_NEW_INSTANCE_JUMBO */ 12995 12996 .balign 32 @ minimize cache lines 12997 .LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object 12998 FETCH(r3, 3) @ r3<- BBBB 12999 cmp r0, #0 @ failed? 13000 #if defined(WITH_JIT) 13001 /* 13002 * The JIT needs the class to be fully resolved before it can 13003 * include this instruction in a trace. 13004 */ 13005 ldrh r1, [rSELF, #offThread_subMode] 13006 beq common_exceptionThrown @ yes, handle the exception 13007 ands r1, #kSubModeJitTraceBuild @ under construction? 13008 bne .LOP_NEW_INSTANCE_JUMBO_jitCheck 13009 #else 13010 beq common_exceptionThrown @ yes, handle the exception 13011 #endif 13012 .LOP_NEW_INSTANCE_JUMBO_end: 13013 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST 13014 GET_INST_OPCODE(ip) @ extract opcode from rINST 13015 SET_VREG(r0, r3) @ vBBBB<- r0 13016 GOTO_OPCODE(ip) @ jump to next instruction 13017 13018 #if defined(WITH_JIT) 13019 /* 13020 * Check to see if we need to stop the trace building early. 13021 * r0: new object 13022 * r3: vAA 13023 */ 13024 .LOP_NEW_INSTANCE_JUMBO_jitCheck: 13025 ldr r1, [r10] @ reload resolved class 13026 cmp r1, #0 @ okay? 13027 bne .LOP_NEW_INSTANCE_JUMBO_end @ yes, finish 13028 mov r9, r0 @ preserve new object 13029 mov r10, r3 @ preserve vAA 13030 mov r0, rSELF 13031 mov r1, rPC 13032 bl dvmJitEndTraceSelect @ (self, pc) 13033 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 13034 GET_INST_OPCODE(ip) @ extract opcode from rINST 13035 SET_VREG(r9, r10) @ vAA<- new object 13036 GOTO_OPCODE(ip) @ jump to next instruction 13037 #endif 13038 13039 /* 13040 * Class initialization required. 13041 * 13042 * r0 holds class object 13043 */ 13044 .LOP_NEW_INSTANCE_JUMBO_needinit: 13045 mov r9, r0 @ save r0 13046 bl dvmInitClass @ initialize class 13047 cmp r0, #0 @ check boolean result 13048 mov r0, r9 @ restore r0 13049 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue 13050 b common_exceptionThrown @ failed, deal with init exception 13051 13052 /* 13053 * Resolution required. This is the least-likely path. 13054 * 13055 * r1 holds AAAAAAAA 13056 */ 13057 .LOP_NEW_INSTANCE_JUMBO_resolve: 13058 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13059 mov r2, #0 @ r2<- false 13060 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13061 bl dvmResolveClass @ r0<- resolved ClassObject ptr 13062 cmp r0, #0 @ got null? 13063 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue 13064 b common_exceptionThrown @ yes, handle exception 13065 13066 /* continuation for OP_NEW_ARRAY_JUMBO */ 13067 13068 13069 /* 13070 * Resolve class. (This is an uncommon case.) 13071 * 13072 * r1 holds array length 13073 * r2 holds class ref AAAAAAAA 13074 */ 13075 .LOP_NEW_ARRAY_JUMBO_resolve: 13076 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 13077 mov r9, r1 @ r9<- length (save) 13078 mov r1, r2 @ r1<- AAAAAAAA 13079 mov r2, #0 @ r2<- false 13080 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 13081 bl dvmResolveClass @ r0<- call(clazz, ref) 13082 cmp r0, #0 @ got null? 13083 mov r1, r9 @ r1<- length (restore) 13084 beq common_exceptionThrown @ yes, handle exception 13085 @ fall through to OP_NEW_ARRAY_JUMBO_finish 13086 13087 /* 13088 * Finish allocation. 13089 * 13090 * r0 holds class 13091 * r1 holds array length 13092 */ 13093 .LOP_NEW_ARRAY_JUMBO_finish: 13094 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 13095 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 13096 cmp r0, #0 @ failed? 13097 FETCH(r2, 3) @ r2<- vBBBB 13098 beq common_exceptionThrown @ yes, handle the exception 13099 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13100 GET_INST_OPCODE(ip) @ extract opcode from rINST 13101 SET_VREG(r0, r2) @ vBBBB<- r0 13102 GOTO_OPCODE(ip) @ jump to next instruction 13103 13104 /* continuation for OP_FILLED_NEW_ARRAY_JUMBO */ 13105 13106 /* 13107 * On entry: 13108 * r0 holds array class 13109 */ 13110 .LOP_FILLED_NEW_ARRAY_JUMBO_continue: 13111 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 13112 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 13113 ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 13114 FETCH(r1, 3) @ r1<- BBBB (length) 13115 cmp rINST, #'I' @ array of ints? 13116 cmpne rINST, #'L' @ array of objects? 13117 cmpne rINST, #'[' @ array of arrays? 13118 mov r9, r1 @ save length in r9 13119 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet 13120 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 13121 cmp r0, #0 @ null return? 13122 beq common_exceptionThrown @ alloc failed, handle exception 13123 13124 FETCH(r1, 4) @ r1<- CCCC 13125 str r0, [rSELF, #offThread_retval] @ retval.l <- new array 13126 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type 13127 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 13128 subs r9, r9, #1 @ length--, check for neg 13129 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST 13130 bmi 2f @ was zero, bail 13131 13132 @ copy values from registers into the array 13133 @ r0=array, r1=CCCC, r9=BBBB (length) 13134 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 13135 1: ldr r3, [r2], #4 @ r3<- *r2++ 13136 subs r9, r9, #1 @ count-- 13137 str r3, [r0], #4 @ *contents++ = vX 13138 bpl 1b 13139 13140 2: ldr r0, [rSELF, #offThread_retval] @ r0<- object 13141 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type 13142 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13143 GET_INST_OPCODE(ip) @ ip<- opcode from rINST 13144 cmp r1, #'I' @ Is int array? 13145 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 13146 GOTO_OPCODE(ip) @ execute it 13147 13148 /* 13149 * Throw an exception indicating that we have not implemented this 13150 * mode of filled-new-array. 13151 */ 13152 .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl: 13153 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_JUMBO 13154 bl dvmThrowInternalError 13155 b common_exceptionThrown 13156 13157 /* 13158 * Ideally we'd only define this once, but depending on layout we can 13159 * exceed the range of the load above. 13160 */ 13161 13162 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_JUMBO: 13163 .word .LstrFilledNewArrayNotImpl 13164 13165 /* continuation for OP_IGET_JUMBO */ 13166 13167 /* 13168 * Currently: 13169 * r0 holds resolved field 13170 * r9 holds object 13171 */ 13172 .LOP_IGET_JUMBO_resolved: 13173 cmp r0, #0 @ resolution unsuccessful? 13174 beq common_exceptionThrown @ yes, throw exception 13175 @ fall through to OP_IGET_JUMBO_finish 13176 13177 /* 13178 * Currently: 13179 * r0 holds resolved field 13180 * r9 holds object 13181 */ 13182 .LOP_IGET_JUMBO_finish: 13183 @bl common_squeak0 13184 cmp r9, #0 @ check object for null 13185 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13186 beq common_errNullObject @ object was null 13187 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13188 @ no-op @ acquiring load 13189 FETCH(r2, 3) @ r2<- BBBB 13190 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13191 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13192 GET_INST_OPCODE(ip) @ extract opcode from rINST 13193 GOTO_OPCODE(ip) @ jump to next instruction 13194 13195 /* continuation for OP_IGET_WIDE_JUMBO */ 13196 13197 /* 13198 * Currently: 13199 * r0 holds resolved field 13200 * r9 holds object 13201 */ 13202 .LOP_IGET_WIDE_JUMBO_resolved: 13203 cmp r0, #0 @ resolution unsuccessful? 13204 beq common_exceptionThrown @ yes, throw exception 13205 @ fall through to OP_IGET_WIDE_JUMBO_finish 13206 13207 /* 13208 * Currently: 13209 * r0 holds resolved field 13210 * r9 holds object 13211 */ 13212 .LOP_IGET_WIDE_JUMBO_finish: 13213 cmp r9, #0 @ check object for null 13214 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13215 beq common_errNullObject @ object was null 13216 .if 0 13217 add r0, r9, r3 @ r0<- address of field 13218 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 13219 .else 13220 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 13221 .endif 13222 FETCH(r2, 3) @ r2<- BBBB 13223 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13224 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13225 GET_INST_OPCODE(ip) @ extract opcode from rINST 13226 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 13227 GOTO_OPCODE(ip) @ jump to next instruction 13228 13229 /* continuation for OP_IGET_OBJECT_JUMBO */ 13230 13231 /* 13232 * Currently: 13233 * r0 holds resolved field 13234 * r9 holds object 13235 */ 13236 .LOP_IGET_OBJECT_JUMBO_resolved: 13237 cmp r0, #0 @ resolution unsuccessful? 13238 beq common_exceptionThrown @ yes, throw exception 13239 @ fall through to OP_IGET_OBJECT_JUMBO_finish 13240 13241 /* 13242 * Currently: 13243 * r0 holds resolved field 13244 * r9 holds object 13245 */ 13246 .LOP_IGET_OBJECT_JUMBO_finish: 13247 @bl common_squeak0 13248 cmp r9, #0 @ check object for null 13249 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13250 beq common_errNullObject @ object was null 13251 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13252 @ no-op @ acquiring load 13253 FETCH(r2, 3) @ r2<- BBBB 13254 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13255 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13256 GET_INST_OPCODE(ip) @ extract opcode from rINST 13257 GOTO_OPCODE(ip) @ jump to next instruction 13258 13259 /* continuation for OP_IGET_BOOLEAN_JUMBO */ 13260 13261 /* 13262 * Currently: 13263 * r0 holds resolved field 13264 * r9 holds object 13265 */ 13266 .LOP_IGET_BOOLEAN_JUMBO_resolved: 13267 cmp r0, #0 @ resolution unsuccessful? 13268 beq common_exceptionThrown @ yes, throw exception 13269 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish 13270 13271 /* 13272 * Currently: 13273 * r0 holds resolved field 13274 * r9 holds object 13275 */ 13276 .LOP_IGET_BOOLEAN_JUMBO_finish: 13277 @bl common_squeak1 13278 cmp r9, #0 @ check object for null 13279 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13280 beq common_errNullObject @ object was null 13281 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13282 @ no-op @ acquiring load 13283 FETCH(r2, 3) @ r2<- BBBB 13284 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13285 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13286 GET_INST_OPCODE(ip) @ extract opcode from rINST 13287 GOTO_OPCODE(ip) @ jump to next instruction 13288 13289 /* continuation for OP_IGET_BYTE_JUMBO */ 13290 13291 /* 13292 * Currently: 13293 * r0 holds resolved field 13294 * r9 holds object 13295 */ 13296 .LOP_IGET_BYTE_JUMBO_resolved: 13297 cmp r0, #0 @ resolution unsuccessful? 13298 beq common_exceptionThrown @ yes, throw exception 13299 @ fall through to OP_IGET_BYTE_JUMBO_finish 13300 13301 /* 13302 * Currently: 13303 * r0 holds resolved field 13304 * r9 holds object 13305 */ 13306 .LOP_IGET_BYTE_JUMBO_finish: 13307 @bl common_squeak2 13308 cmp r9, #0 @ check object for null 13309 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13310 beq common_errNullObject @ object was null 13311 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13312 @ no-op @ acquiring load 13313 FETCH(r2, 3) @ r2<- BBBB 13314 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13315 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13316 GET_INST_OPCODE(ip) @ extract opcode from rINST 13317 GOTO_OPCODE(ip) @ jump to next instruction 13318 13319 /* continuation for OP_IGET_CHAR_JUMBO */ 13320 13321 /* 13322 * Currently: 13323 * r0 holds resolved field 13324 * r9 holds object 13325 */ 13326 .LOP_IGET_CHAR_JUMBO_resolved: 13327 cmp r0, #0 @ resolution unsuccessful? 13328 beq common_exceptionThrown @ yes, throw exception 13329 @ fall through to OP_IGET_CHAR_JUMBO_finish 13330 13331 /* 13332 * Currently: 13333 * r0 holds resolved field 13334 * r9 holds object 13335 */ 13336 .LOP_IGET_CHAR_JUMBO_finish: 13337 @bl common_squeak3 13338 cmp r9, #0 @ check object for null 13339 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13340 beq common_errNullObject @ object was null 13341 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13342 @ no-op @ acquiring load 13343 FETCH(r2, 3) @ r2<- BBBB 13344 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13345 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13346 GET_INST_OPCODE(ip) @ extract opcode from rINST 13347 GOTO_OPCODE(ip) @ jump to next instruction 13348 13349 /* continuation for OP_IGET_SHORT_JUMBO */ 13350 13351 /* 13352 * Currently: 13353 * r0 holds resolved field 13354 * r9 holds object 13355 */ 13356 .LOP_IGET_SHORT_JUMBO_resolved: 13357 cmp r0, #0 @ resolution unsuccessful? 13358 beq common_exceptionThrown @ yes, throw exception 13359 @ fall through to OP_IGET_SHORT_JUMBO_finish 13360 13361 /* 13362 * Currently: 13363 * r0 holds resolved field 13364 * r9 holds object 13365 */ 13366 .LOP_IGET_SHORT_JUMBO_finish: 13367 @bl common_squeak4 13368 cmp r9, #0 @ check object for null 13369 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13370 beq common_errNullObject @ object was null 13371 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 13372 @ no-op @ acquiring load 13373 FETCH(r2, 3) @ r2<- BBBB 13374 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13375 SET_VREG(r0, r2) @ fp[BBBB]<- r0 13376 GET_INST_OPCODE(ip) @ extract opcode from rINST 13377 GOTO_OPCODE(ip) @ jump to next instruction 13378 13379 /* continuation for OP_IPUT_JUMBO */ 13380 13381 /* 13382 * Currently: 13383 * r0 holds resolved field 13384 * r9 holds object 13385 */ 13386 .LOP_IPUT_JUMBO_resolved: 13387 cmp r0, #0 @ resolution unsuccessful? 13388 beq common_exceptionThrown @ yes, throw exception 13389 @ fall through to OP_IPUT_JUMBO_finish 13390 13391 /* 13392 * Currently: 13393 * r0 holds resolved field 13394 * r9 holds object 13395 */ 13396 .LOP_IPUT_JUMBO_finish: 13397 @bl common_squeak0 13398 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13399 FETCH(r1, 3) @ r1<- BBBB 13400 cmp r9, #0 @ check object for null 13401 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13402 beq common_errNullObject @ object was null 13403 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13404 GET_INST_OPCODE(ip) @ extract opcode from rINST 13405 @ no-op @ releasing store 13406 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13407 @ no-op 13408 GOTO_OPCODE(ip) @ jump to next instruction 13409 13410 /* continuation for OP_IPUT_WIDE_JUMBO */ 13411 13412 /* 13413 * Currently: 13414 * r0 holds resolved field 13415 * r9 holds object 13416 */ 13417 .LOP_IPUT_WIDE_JUMBO_resolved: 13418 cmp r0, #0 @ resolution unsuccessful? 13419 beq common_exceptionThrown @ yes, throw exception 13420 @ fall through to OP_IPUT_WIDE_JUMBO_finish 13421 13422 /* 13423 * Currently: 13424 * r0 holds resolved field 13425 * r9 holds object 13426 */ 13427 .LOP_IPUT_WIDE_JUMBO_finish: 13428 cmp r9, #0 @ check object for null 13429 FETCH(r2, 3) @ r1<- BBBB 13430 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13431 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 13432 beq common_errNullObject @ object was null 13433 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13434 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 13435 GET_INST_OPCODE(r10) @ extract opcode from rINST 13436 .if 0 13437 add r2, r9, r3 @ r2<- target address 13438 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 13439 .else 13440 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 13441 .endif 13442 GOTO_OPCODE(r10) @ jump to next instruction 13443 13444 /* continuation for OP_IPUT_OBJECT_JUMBO */ 13445 13446 /* 13447 * Currently: 13448 * r0 holds resolved field 13449 * r9 holds object 13450 */ 13451 .LOP_IPUT_OBJECT_JUMBO_resolved: 13452 cmp r0, #0 @ resolution unsuccessful? 13453 beq common_exceptionThrown @ yes, throw exception 13454 @ fall through to OP_IPUT_OBJECT_JUMBO_finish 13455 13456 /* 13457 * Currently: 13458 * r0 holds resolved field 13459 * r9 holds object 13460 */ 13461 .LOP_IPUT_OBJECT_JUMBO_finish: 13462 @bl common_squeak0 13463 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13464 FETCH(r1, 3) @ r1<- BBBB 13465 cmp r9, #0 @ check object for null 13466 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13467 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 13468 beq common_errNullObject @ object was null 13469 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13470 GET_INST_OPCODE(ip) @ extract opcode from rINST 13471 @ no-op @ releasing store 13472 str r0, [r9, r3] @ obj.field (32 bits)<- r0 13473 @ no-op 13474 cmp r0, #0 @ stored a null reference? 13475 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 13476 GOTO_OPCODE(ip) @ jump to next instruction 13477 13478 /* continuation for OP_IPUT_BOOLEAN_JUMBO */ 13479 13480 /* 13481 * Currently: 13482 * r0 holds resolved field 13483 * r9 holds object 13484 */ 13485 .LOP_IPUT_BOOLEAN_JUMBO_resolved: 13486 cmp r0, #0 @ resolution unsuccessful? 13487 beq common_exceptionThrown @ yes, throw exception 13488 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish 13489 13490 /* 13491 * Currently: 13492 * r0 holds resolved field 13493 * r9 holds object 13494 */ 13495 .LOP_IPUT_BOOLEAN_JUMBO_finish: 13496 @bl common_squeak1 13497 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13498 FETCH(r1, 3) @ r1<- BBBB 13499 cmp r9, #0 @ check object for null 13500 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13501 beq common_errNullObject @ object was null 13502 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13503 GET_INST_OPCODE(ip) @ extract opcode from rINST 13504 @ no-op @ releasing store 13505 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13506 @ no-op 13507 GOTO_OPCODE(ip) @ jump to next instruction 13508 13509 /* continuation for OP_IPUT_BYTE_JUMBO */ 13510 13511 /* 13512 * Currently: 13513 * r0 holds resolved field 13514 * r9 holds object 13515 */ 13516 .LOP_IPUT_BYTE_JUMBO_resolved: 13517 cmp r0, #0 @ resolution unsuccessful? 13518 beq common_exceptionThrown @ yes, throw exception 13519 @ fall through to OP_IPUT_BYTE_JUMBO_finish 13520 13521 /* 13522 * Currently: 13523 * r0 holds resolved field 13524 * r9 holds object 13525 */ 13526 .LOP_IPUT_BYTE_JUMBO_finish: 13527 @bl common_squeak2 13528 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13529 FETCH(r1, 3) @ r1<- BBBB 13530 cmp r9, #0 @ check object for null 13531 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13532 beq common_errNullObject @ object was null 13533 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13534 GET_INST_OPCODE(ip) @ extract opcode from rINST 13535 @ no-op @ releasing store 13536 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13537 @ no-op 13538 GOTO_OPCODE(ip) @ jump to next instruction 13539 13540 /* continuation for OP_IPUT_CHAR_JUMBO */ 13541 13542 /* 13543 * Currently: 13544 * r0 holds resolved field 13545 * r9 holds object 13546 */ 13547 .LOP_IPUT_CHAR_JUMBO_resolved: 13548 cmp r0, #0 @ resolution unsuccessful? 13549 beq common_exceptionThrown @ yes, throw exception 13550 @ fall through to OP_IPUT_CHAR_JUMBO_finish 13551 13552 /* 13553 * Currently: 13554 * r0 holds resolved field 13555 * r9 holds object 13556 */ 13557 .LOP_IPUT_CHAR_JUMBO_finish: 13558 @bl common_squeak3 13559 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13560 FETCH(r1, 3) @ r1<- BBBB 13561 cmp r9, #0 @ check object for null 13562 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13563 beq common_errNullObject @ object was null 13564 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13565 GET_INST_OPCODE(ip) @ extract opcode from rINST 13566 @ no-op @ releasing store 13567 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13568 @ no-op 13569 GOTO_OPCODE(ip) @ jump to next instruction 13570 13571 /* continuation for OP_IPUT_SHORT_JUMBO */ 13572 13573 /* 13574 * Currently: 13575 * r0 holds resolved field 13576 * r9 holds object 13577 */ 13578 .LOP_IPUT_SHORT_JUMBO_resolved: 13579 cmp r0, #0 @ resolution unsuccessful? 13580 beq common_exceptionThrown @ yes, throw exception 13581 @ fall through to OP_IPUT_SHORT_JUMBO_finish 13582 13583 /* 13584 * Currently: 13585 * r0 holds resolved field 13586 * r9 holds object 13587 */ 13588 .LOP_IPUT_SHORT_JUMBO_finish: 13589 @bl common_squeak4 13590 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 13591 FETCH(r1, 3) @ r1<- BBBB 13592 cmp r9, #0 @ check object for null 13593 GET_VREG(r0, r1) @ r0<- fp[BBBB] 13594 beq common_errNullObject @ object was null 13595 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 13596 GET_INST_OPCODE(ip) @ extract opcode from rINST 13597 @ no-op @ releasing store 13598 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 13599 @ no-op 13600 GOTO_OPCODE(ip) @ jump to next instruction 13601 13602 /* continuation for OP_SGET_JUMBO */ 13603 13604 /* 13605 * Continuation if the field has not yet been resolved. 13606 * r1: AAAAAAAA field ref 13607 * r10: dvmDex->pResFields 13608 */ 13609 .LOP_SGET_JUMBO_resolve: 13610 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13611 #if defined(WITH_JIT) 13612 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13613 #endif 13614 EXPORT_PC() @ resolve() could throw, so export now 13615 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13616 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13617 cmp r0, #0 @ success? 13618 beq common_exceptionThrown @ no, handle exception 13619 #if defined(WITH_JIT) 13620 /* 13621 * If the JIT is actively building a trace we need to make sure 13622 * that the field is fully resolved before including this instruction. 13623 */ 13624 bl common_verifyField 13625 #endif 13626 b .LOP_SGET_JUMBO_finish @ resume 13627 13628 /* continuation for OP_SGET_WIDE_JUMBO */ 13629 13630 /* 13631 * Continuation if the field has not yet been resolved. 13632 * r1: AAAAAAAA field ref 13633 * 13634 * Returns StaticField pointer in r0. 13635 */ 13636 .LOP_SGET_WIDE_JUMBO_resolve: 13637 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13638 EXPORT_PC() @ resolve() could throw, so export now 13639 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13640 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13641 cmp r0, #0 @ success? 13642 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish 13643 b common_exceptionThrown @ no, handle exception 13644 13645 /* continuation for OP_SGET_OBJECT_JUMBO */ 13646 13647 /* 13648 * Continuation if the field has not yet been resolved. 13649 * r1: AAAAAAAA field ref 13650 * r10: dvmDex->pResFields 13651 */ 13652 .LOP_SGET_OBJECT_JUMBO_resolve: 13653 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13654 #if defined(WITH_JIT) 13655 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13656 #endif 13657 EXPORT_PC() @ resolve() could throw, so export now 13658 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13659 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13660 cmp r0, #0 @ success? 13661 beq common_exceptionThrown @ no, handle exception 13662 #if defined(WITH_JIT) 13663 /* 13664 * If the JIT is actively building a trace we need to make sure 13665 * that the field is fully resolved before including this instruction. 13666 */ 13667 bl common_verifyField 13668 #endif 13669 b .LOP_SGET_OBJECT_JUMBO_finish @ resume 13670 13671 /* continuation for OP_SGET_BOOLEAN_JUMBO */ 13672 13673 /* 13674 * Continuation if the field has not yet been resolved. 13675 * r1: AAAAAAAA field ref 13676 * r10: dvmDex->pResFields 13677 */ 13678 .LOP_SGET_BOOLEAN_JUMBO_resolve: 13679 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13680 #if defined(WITH_JIT) 13681 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13682 #endif 13683 EXPORT_PC() @ resolve() could throw, so export now 13684 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13685 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13686 cmp r0, #0 @ success? 13687 beq common_exceptionThrown @ no, handle exception 13688 #if defined(WITH_JIT) 13689 /* 13690 * If the JIT is actively building a trace we need to make sure 13691 * that the field is fully resolved before including this instruction. 13692 */ 13693 bl common_verifyField 13694 #endif 13695 b .LOP_SGET_BOOLEAN_JUMBO_finish @ resume 13696 13697 /* continuation for OP_SGET_BYTE_JUMBO */ 13698 13699 /* 13700 * Continuation if the field has not yet been resolved. 13701 * r1: AAAAAAAA field ref 13702 * r10: dvmDex->pResFields 13703 */ 13704 .LOP_SGET_BYTE_JUMBO_resolve: 13705 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13706 #if defined(WITH_JIT) 13707 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13708 #endif 13709 EXPORT_PC() @ resolve() could throw, so export now 13710 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13711 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13712 cmp r0, #0 @ success? 13713 beq common_exceptionThrown @ no, handle exception 13714 #if defined(WITH_JIT) 13715 /* 13716 * If the JIT is actively building a trace we need to make sure 13717 * that the field is fully resolved before including this instruction. 13718 */ 13719 bl common_verifyField 13720 #endif 13721 b .LOP_SGET_BYTE_JUMBO_finish @ resume 13722 13723 /* continuation for OP_SGET_CHAR_JUMBO */ 13724 13725 /* 13726 * Continuation if the field has not yet been resolved. 13727 * r1: AAAAAAAA field ref 13728 * r10: dvmDex->pResFields 13729 */ 13730 .LOP_SGET_CHAR_JUMBO_resolve: 13731 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13732 #if defined(WITH_JIT) 13733 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13734 #endif 13735 EXPORT_PC() @ resolve() could throw, so export now 13736 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13737 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13738 cmp r0, #0 @ success? 13739 beq common_exceptionThrown @ no, handle exception 13740 #if defined(WITH_JIT) 13741 /* 13742 * If the JIT is actively building a trace we need to make sure 13743 * that the field is fully resolved before including this instruction. 13744 */ 13745 bl common_verifyField 13746 #endif 13747 b .LOP_SGET_CHAR_JUMBO_finish @ resume 13748 13749 /* continuation for OP_SGET_SHORT_JUMBO */ 13750 13751 /* 13752 * Continuation if the field has not yet been resolved. 13753 * r1: AAAAAAAA field ref 13754 * r10: dvmDex->pResFields 13755 */ 13756 .LOP_SGET_SHORT_JUMBO_resolve: 13757 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13758 #if defined(WITH_JIT) 13759 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13760 #endif 13761 EXPORT_PC() @ resolve() could throw, so export now 13762 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13763 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13764 cmp r0, #0 @ success? 13765 beq common_exceptionThrown @ no, handle exception 13766 #if defined(WITH_JIT) 13767 /* 13768 * If the JIT is actively building a trace we need to make sure 13769 * that the field is fully resolved before including this instruction. 13770 */ 13771 bl common_verifyField 13772 #endif 13773 b .LOP_SGET_SHORT_JUMBO_finish @ resume 13774 13775 /* continuation for OP_SPUT_JUMBO */ 13776 13777 /* 13778 * Continuation if the field has not yet been resolved. 13779 * r1: AAAAAAAA field ref 13780 * r10: dvmDex->pResFields 13781 */ 13782 .LOP_SPUT_JUMBO_resolve: 13783 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13784 #if defined(WITH_JIT) 13785 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13786 #endif 13787 EXPORT_PC() @ resolve() could throw, so export now 13788 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13789 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13790 cmp r0, #0 @ success? 13791 beq common_exceptionThrown @ no, handle exception 13792 #if defined(WITH_JIT) 13793 /* 13794 * If the JIT is actively building a trace we need to make sure 13795 * that the field is fully resolved before including this instruction. 13796 */ 13797 bl common_verifyField 13798 #endif 13799 b .LOP_SPUT_JUMBO_finish @ resume 13800 13801 /* continuation for OP_SPUT_WIDE_JUMBO */ 13802 13803 /* 13804 * Continuation if the field has not yet been resolved. 13805 * r1: AAAAAAAA field ref 13806 * r9: &fp[BBBB] 13807 * r10: dvmDex->pResFields 13808 * 13809 * Returns StaticField pointer in r2. 13810 */ 13811 .LOP_SPUT_WIDE_JUMBO_resolve: 13812 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13813 #if defined(WITH_JIT) 13814 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13815 #endif 13816 EXPORT_PC() @ resolve() could throw, so export now 13817 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13818 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13819 cmp r0, #0 @ success? 13820 mov r2, r0 @ copy to r2 13821 beq common_exceptionThrown @ no, handle exception 13822 #if defined(WITH_JIT) 13823 /* 13824 * If the JIT is actively building a trace we need to make sure 13825 * that the field is fully resolved before including this instruction. 13826 */ 13827 bl common_verifyField 13828 #endif 13829 b .LOP_SPUT_WIDE_JUMBO_finish @ resume 13830 13831 /* continuation for OP_SPUT_OBJECT_JUMBO */ 13832 13833 13834 .LOP_SPUT_OBJECT_JUMBO_end: 13835 str r1, [r0, #offStaticField_value] @ field<- vBBBB 13836 @ no-op 13837 cmp r1, #0 @ stored a null object? 13838 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 13839 GOTO_OPCODE(ip) @ jump to next instruction 13840 13841 /* Continuation if the field has not yet been resolved. 13842 * r1: AAAAaaaa field ref 13843 * r10: dvmDex->pResFields 13844 */ 13845 .LOP_SPUT_OBJECT_JUMBO_resolve: 13846 ldr r2, [rSELF, #offThread_method] @ r9<- current method 13847 #if defined(WITH_JIT) 13848 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13849 #endif 13850 EXPORT_PC() @ resolve() could throw, so export now 13851 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13852 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13853 cmp r0, #0 @ success? 13854 beq common_exceptionThrown @ no, handle exception 13855 #if defined(WITH_JIT) 13856 /* 13857 * If the JIT is actively building a trace we need to make sure 13858 * that the field is fully resolved before including this instruction. 13859 */ 13860 bl common_verifyField 13861 #endif 13862 b .LOP_SPUT_OBJECT_JUMBO_finish @ resume 13863 13864 13865 /* continuation for OP_SPUT_BOOLEAN_JUMBO */ 13866 13867 /* 13868 * Continuation if the field has not yet been resolved. 13869 * r1: AAAAAAAA field ref 13870 * r10: dvmDex->pResFields 13871 */ 13872 .LOP_SPUT_BOOLEAN_JUMBO_resolve: 13873 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13874 #if defined(WITH_JIT) 13875 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13876 #endif 13877 EXPORT_PC() @ resolve() could throw, so export now 13878 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13879 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13880 cmp r0, #0 @ success? 13881 beq common_exceptionThrown @ no, handle exception 13882 #if defined(WITH_JIT) 13883 /* 13884 * If the JIT is actively building a trace we need to make sure 13885 * that the field is fully resolved before including this instruction. 13886 */ 13887 bl common_verifyField 13888 #endif 13889 b .LOP_SPUT_BOOLEAN_JUMBO_finish @ resume 13890 13891 /* continuation for OP_SPUT_BYTE_JUMBO */ 13892 13893 /* 13894 * Continuation if the field has not yet been resolved. 13895 * r1: AAAAAAAA field ref 13896 * r10: dvmDex->pResFields 13897 */ 13898 .LOP_SPUT_BYTE_JUMBO_resolve: 13899 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13900 #if defined(WITH_JIT) 13901 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13902 #endif 13903 EXPORT_PC() @ resolve() could throw, so export now 13904 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13905 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13906 cmp r0, #0 @ success? 13907 beq common_exceptionThrown @ no, handle exception 13908 #if defined(WITH_JIT) 13909 /* 13910 * If the JIT is actively building a trace we need to make sure 13911 * that the field is fully resolved before including this instruction. 13912 */ 13913 bl common_verifyField 13914 #endif 13915 b .LOP_SPUT_BYTE_JUMBO_finish @ resume 13916 13917 /* continuation for OP_SPUT_CHAR_JUMBO */ 13918 13919 /* 13920 * Continuation if the field has not yet been resolved. 13921 * r1: AAAAAAAA field ref 13922 * r10: dvmDex->pResFields 13923 */ 13924 .LOP_SPUT_CHAR_JUMBO_resolve: 13925 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13926 #if defined(WITH_JIT) 13927 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13928 #endif 13929 EXPORT_PC() @ resolve() could throw, so export now 13930 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13931 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13932 cmp r0, #0 @ success? 13933 beq common_exceptionThrown @ no, handle exception 13934 #if defined(WITH_JIT) 13935 /* 13936 * If the JIT is actively building a trace we need to make sure 13937 * that the field is fully resolved before including this instruction. 13938 */ 13939 bl common_verifyField 13940 #endif 13941 b .LOP_SPUT_CHAR_JUMBO_finish @ resume 13942 13943 /* continuation for OP_SPUT_SHORT_JUMBO */ 13944 13945 /* 13946 * Continuation if the field has not yet been resolved. 13947 * r1: AAAAAAAA field ref 13948 * r10: dvmDex->pResFields 13949 */ 13950 .LOP_SPUT_SHORT_JUMBO_resolve: 13951 ldr r2, [rSELF, #offThread_method] @ r2<- current method 13952 #if defined(WITH_JIT) 13953 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 13954 #endif 13955 EXPORT_PC() @ resolve() could throw, so export now 13956 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 13957 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 13958 cmp r0, #0 @ success? 13959 beq common_exceptionThrown @ no, handle exception 13960 #if defined(WITH_JIT) 13961 /* 13962 * If the JIT is actively building a trace we need to make sure 13963 * that the field is fully resolved before including this instruction. 13964 */ 13965 bl common_verifyField 13966 #endif 13967 b .LOP_SPUT_SHORT_JUMBO_finish @ resume 13968 13969 /* continuation for OP_INVOKE_VIRTUAL_JUMBO */ 13970 13971 /* 13972 * At this point: 13973 * r0 = resolved base method 13974 */ 13975 .LOP_INVOKE_VIRTUAL_JUMBO_continue: 13976 FETCH(r10, 4) @ r10<- CCCC 13977 GET_VREG(r9, r10) @ r9<- "this" ptr 13978 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13979 cmp r9, #0 @ is "this" null? 13980 beq common_errNullObject @ null "this", throw exception 13981 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz 13982 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 13983 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 13984 bl common_invokeMethodJumbo @ (r0=method, r9="this") 13985 13986 /* continuation for OP_INVOKE_SUPER_JUMBO */ 13987 13988 /* 13989 * At this point: 13990 * r0 = resolved base method 13991 * r10 = method->clazz 13992 */ 13993 .LOP_INVOKE_SUPER_JUMBO_continue: 13994 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super 13995 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 13996 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 13997 EXPORT_PC() @ must export for invoke 13998 cmp r2, r3 @ compare (methodIndex, vtableCount) 13999 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass 14000 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 14001 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 14002 bl common_invokeMethodJumbo @ (r0=method, r9="this") 14003 14004 .LOP_INVOKE_SUPER_JUMBO_resolve: 14005 mov r0, r10 @ r0<- method->clazz 14006 mov r2, #METHOD_VIRTUAL @ resolver method type 14007 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 14008 cmp r0, #0 @ got null? 14009 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue 14010 b common_exceptionThrown @ yes, handle exception 14011 14012 /* 14013 * Throw a NoSuchMethodError with the method name as the message. 14014 * r0 = resolved base method 14015 */ 14016 .LOP_INVOKE_SUPER_JUMBO_nsm: 14017 ldr r1, [r0, #offMethod_name] @ r1<- method name 14018 b common_errNoSuchMethod 14019 14020 /* continuation for OP_INVOKE_DIRECT_JUMBO */ 14021 14022 /* 14023 * On entry: 14024 * r1 = reference (CCCC) 14025 * r10 = "this" register 14026 */ 14027 .LOP_INVOKE_DIRECT_JUMBO_resolve: 14028 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 14029 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 14030 mov r2, #METHOD_DIRECT @ resolver method type 14031 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 14032 cmp r0, #0 @ got null? 14033 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue 14034 b common_exceptionThrown @ yes, handle exception 14035 14036 /* continuation for OP_INVOKE_STATIC_JUMBO */ 14037 14038 14039 .LOP_INVOKE_STATIC_JUMBO_resolve: 14040 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 14041 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 14042 mov r2, #METHOD_STATIC @ resolver method type 14043 bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 14044 cmp r0, #0 @ got null? 14045 #if defined(WITH_JIT) 14046 /* 14047 * Check to see if we're actively building a trace. If so, 14048 * we need to keep this instruction out of it. 14049 * r10: &resolved_methodToCall 14050 */ 14051 ldrh r2, [rSELF, #offThread_subMode] 14052 beq common_exceptionThrown @ null, handle exception 14053 ands r2, #kSubModeJitTraceBuild @ trace under construction? 14054 beq common_invokeMethodJumboNoThis @ no (r0=method, r9="this") 14055 ldr r1, [r10] @ reload resolved method 14056 cmp r1, #0 @ finished resolving? 14057 bne common_invokeMethodJumboNoThis @ yes (r0=method, r9="this") 14058 mov r10, r0 @ preserve method 14059 mov r0, rSELF 14060 mov r1, rPC 14061 bl dvmJitEndTraceSelect @ (self, pc) 14062 mov r0, r10 14063 b common_invokeMethodJumboNoThis @ whew, finally! 14064 #else 14065 bne common_invokeMethodJumboNoThis @ (r0=method, r9="this") 14066 b common_exceptionThrown @ yes, handle exception 14067 #endif 14068 14069 /* continuation for OP_INVOKE_OBJECT_INIT_JUMBO */ 14070 14071 .LOP_INVOKE_OBJECT_INIT_JUMBO_setFinal: 14072 EXPORT_PC() @ can throw 14073 bl dvmSetFinalizable @ call dvmSetFinalizable(obj) 14074 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception 14075 cmp r0, #0 @ exception pending? 14076 bne common_exceptionThrown @ yes, handle it 14077 b .LOP_INVOKE_OBJECT_INIT_JUMBO_finish 14078 14079 /* 14080 * A debugger is attached, so we need to go ahead and do 14081 * this. For simplicity, we'll just jump directly to the 14082 * corresponding handler. Note that we can't use 14083 * rIBASE here because it may be in single-step mode. 14084 * Load the primary table base directly. 14085 */ 14086 .LOP_INVOKE_OBJECT_INIT_JUMBO_debugger: 14087 ldr r1, [rSELF, #offThread_mainHandlerTable] 14088 .if 1 14089 mov ip, #OP_INVOKE_DIRECT_JUMBO 14090 .else 14091 mov ip, #OP_INVOKE_DIRECT_RANGE 14092 .endif 14093 GOTO_OPCODE_BASE(r1,ip) @ execute it 14094 14095 /* continuation for OP_IGET_VOLATILE_JUMBO */ 14096 14097 /* 14098 * Currently: 14099 * r0 holds resolved field 14100 * r9 holds object 14101 */ 14102 .LOP_IGET_VOLATILE_JUMBO_resolved: 14103 cmp r0, #0 @ resolution unsuccessful? 14104 beq common_exceptionThrown @ yes, throw exception 14105 @ fall through to OP_IGET_VOLATILE_JUMBO_finish 14106 14107 /* 14108 * Currently: 14109 * r0 holds resolved field 14110 * r9 holds object 14111 */ 14112 .LOP_IGET_VOLATILE_JUMBO_finish: 14113 @bl common_squeak0 14114 cmp r9, #0 @ check object for null 14115 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 14116 beq common_errNullObject @ object was null 14117 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 14118 SMP_DMB @ acquiring load 14119 FETCH(r2, 3) @ r2<- BBBB 14120 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 14121 SET_VREG(r0, r2) @ fp[BBBB]<- r0 14122 GET_INST_OPCODE(ip) @ extract opcode from rINST 14123 GOTO_OPCODE(ip) @ jump to next instruction 14124 14125 /* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */ 14126 14127 /* 14128 * Currently: 14129 * r0 holds resolved field 14130 * r9 holds object 14131 */ 14132 .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved: 14133 cmp r0, #0 @ resolution unsuccessful? 14134 beq common_exceptionThrown @ yes, throw exception 14135 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish 14136 14137 /* 14138 * Currently: 14139 * r0 holds resolved field 14140 * r9 holds object 14141 */ 14142 .LOP_IGET_WIDE_VOLATILE_JUMBO_finish: 14143 cmp r9, #0 @ check object for null 14144 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 14145 beq common_errNullObject @ object was null 14146 .if 1 14147 add r0, r9, r3 @ r0<- address of field 14148 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 14149 .else 14150 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 14151 .endif 14152 FETCH(r2, 3) @ r2<- BBBB 14153 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 14154 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 14155 GET_INST_OPCODE(ip) @ extract opcode from rINST 14156 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1 14157 GOTO_OPCODE(ip) @ jump to next instruction 14158 14159 /* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */ 14160 14161 /* 14162 * Currently: 14163 * r0 holds resolved field 14164 * r9 holds object 14165 */ 14166 .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved: 14167 cmp r0, #0 @ resolution unsuccessful? 14168 beq common_exceptionThrown @ yes, throw exception 14169 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish 14170 14171 /* 14172 * Currently: 14173 * r0 holds resolved field 14174 * r9 holds object 14175 */ 14176 .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish: 14177 @bl common_squeak0 14178 cmp r9, #0 @ check object for null 14179 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 14180 beq common_errNullObject @ object was null 14181 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 14182 SMP_DMB @ acquiring load 14183 FETCH(r2, 3) @ r2<- BBBB 14184 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 14185 SET_VREG(r0, r2) @ fp[BBBB]<- r0 14186 GET_INST_OPCODE(ip) @ extract opcode from rINST 14187 GOTO_OPCODE(ip) @ jump to next instruction 14188 14189 /* continuation for OP_IPUT_VOLATILE_JUMBO */ 14190 14191 /* 14192 * Currently: 14193 * r0 holds resolved field 14194 * r9 holds object 14195 */ 14196 .LOP_IPUT_VOLATILE_JUMBO_resolved: 14197 cmp r0, #0 @ resolution unsuccessful? 14198 beq common_exceptionThrown @ yes, throw exception 14199 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish 14200 14201 /* 14202 * Currently: 14203 * r0 holds resolved field 14204 * r9 holds object 14205 */ 14206 .LOP_IPUT_VOLATILE_JUMBO_finish: 14207 @bl common_squeak0 14208 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 14209 FETCH(r1, 3) @ r1<- BBBB 14210 cmp r9, #0 @ check object for null 14211 GET_VREG(r0, r1) @ r0<- fp[BBBB] 14212 beq common_errNullObject @ object was null 14213 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 14214 GET_INST_OPCODE(ip) @ extract opcode from rINST 14215 SMP_DMB_ST @ releasing store 14216 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 14217 SMP_DMB 14218 GOTO_OPCODE(ip) @ jump to next instruction 14219 14220 /* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */ 14221 14222 /* 14223 * Currently: 14224 * r0 holds resolved field 14225 * r9 holds object 14226 */ 14227 .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved: 14228 cmp r0, #0 @ resolution unsuccessful? 14229 beq common_exceptionThrown @ yes, throw exception 14230 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish 14231 14232 /* 14233 * Currently: 14234 * r0 holds resolved field 14235 * r9 holds object 14236 */ 14237 .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish: 14238 cmp r9, #0 @ check object for null 14239 FETCH(r2, 3) @ r1<- BBBB 14240 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 14241 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB] 14242 beq common_errNullObject @ object was null 14243 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 14244 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB] 14245 GET_INST_OPCODE(r10) @ extract opcode from rINST 14246 .if 1 14247 add r2, r9, r3 @ r2<- target address 14248 bl dvmQuasiAtomicSwap64Sync @ stores r0/r1 into addr r2 14249 .else 14250 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 14251 .endif 14252 GOTO_OPCODE(r10) @ jump to next instruction 14253 14254 /* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */ 14255 14256 /* 14257 * Currently: 14258 * r0 holds resolved field 14259 * r9 holds object 14260 */ 14261 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved: 14262 cmp r0, #0 @ resolution unsuccessful? 14263 beq common_exceptionThrown @ yes, throw exception 14264 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish 14265 14266 /* 14267 * Currently: 14268 * r0 holds resolved field 14269 * r9 holds object 14270 */ 14271 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish: 14272 @bl common_squeak0 14273 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 14274 FETCH(r1, 3) @ r1<- BBBB 14275 cmp r9, #0 @ check object for null 14276 GET_VREG(r0, r1) @ r0<- fp[BBBB] 14277 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base 14278 beq common_errNullObject @ object was null 14279 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 14280 GET_INST_OPCODE(ip) @ extract opcode from rINST 14281 SMP_DMB_ST @ releasing store 14282 str r0, [r9, r3] @ obj.field (32 bits)<- r0 14283 SMP_DMB 14284 cmp r0, #0 @ stored a null reference? 14285 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 14286 GOTO_OPCODE(ip) @ jump to next instruction 14287 14288 /* continuation for OP_SGET_VOLATILE_JUMBO */ 14289 14290 /* 14291 * Continuation if the field has not yet been resolved. 14292 * r1: AAAAAAAA field ref 14293 * r10: dvmDex->pResFields 14294 */ 14295 .LOP_SGET_VOLATILE_JUMBO_resolve: 14296 ldr r2, [rSELF, #offThread_method] @ r2<- current method 14297 #if defined(WITH_JIT) 14298 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 14299 #endif 14300 EXPORT_PC() @ resolve() could throw, so export now 14301 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 14302 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 14303 cmp r0, #0 @ success? 14304 beq common_exceptionThrown @ no, handle exception 14305 #if defined(WITH_JIT) 14306 /* 14307 * If the JIT is actively building a trace we need to make sure 14308 * that the field is fully resolved before including this instruction. 14309 */ 14310 bl common_verifyField 14311 #endif 14312 b .LOP_SGET_VOLATILE_JUMBO_finish @ resume 14313 14314 /* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */ 14315 14316 /* 14317 * Continuation if the field has not yet been resolved. 14318 * r1: AAAAAAAA field ref 14319 * 14320 * Returns StaticField pointer in r0. 14321 */ 14322 .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve: 14323 ldr r2, [rSELF, #offThread_method] @ r2<- current method 14324 EXPORT_PC() @ resolve() could throw, so export now 14325 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 14326 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 14327 cmp r0, #0 @ success? 14328 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish 14329 b common_exceptionThrown @ no, handle exception 14330 14331 /* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */ 14332 14333 /* 14334 * Continuation if the field has not yet been resolved. 14335 * r1: AAAAAAAA field ref 14336 * r10: dvmDex->pResFields 14337 */ 14338 .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve: 14339 ldr r2, [rSELF, #offThread_method] @ r2<- current method 14340 #if defined(WITH_JIT) 14341 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 14342 #endif 14343 EXPORT_PC() @ resolve() could throw, so export now 14344 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 14345 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 14346 cmp r0, #0 @ success? 14347 beq common_exceptionThrown @ no, handle exception 14348 #if defined(WITH_JIT) 14349 /* 14350 * If the JIT is actively building a trace we need to make sure 14351 * that the field is fully resolved before including this instruction. 14352 */ 14353 bl common_verifyField 14354 #endif 14355 b .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ resume 14356 14357 /* continuation for OP_SPUT_VOLATILE_JUMBO */ 14358 14359 /* 14360 * Continuation if the field has not yet been resolved. 14361 * r1: AAAAAAAA field ref 14362 * r10: dvmDex->pResFields 14363 */ 14364 .LOP_SPUT_VOLATILE_JUMBO_resolve: 14365 ldr r2, [rSELF, #offThread_method] @ r2<- current method 14366 #if defined(WITH_JIT) 14367 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 14368 #endif 14369 EXPORT_PC() @ resolve() could throw, so export now 14370 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 14371 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 14372 cmp r0, #0 @ success? 14373 beq common_exceptionThrown @ no, handle exception 14374 #if defined(WITH_JIT) 14375 /* 14376 * If the JIT is actively building a trace we need to make sure 14377 * that the field is fully resolved before including this instruction. 14378 */ 14379 bl common_verifyField 14380 #endif 14381 b .LOP_SPUT_VOLATILE_JUMBO_finish @ resume 14382 14383 /* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */ 14384 14385 /* 14386 * Continuation if the field has not yet been resolved. 14387 * r1: AAAAAAAA field ref 14388 * r9: &fp[BBBB] 14389 * r10: dvmDex->pResFields 14390 * 14391 * Returns StaticField pointer in r2. 14392 */ 14393 .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve: 14394 ldr r2, [rSELF, #offThread_method] @ r2<- current method 14395 #if defined(WITH_JIT) 14396 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 14397 #endif 14398 EXPORT_PC() @ resolve() could throw, so export now 14399 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 14400 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 14401 cmp r0, #0 @ success? 14402 mov r2, r0 @ copy to r2 14403 beq common_exceptionThrown @ no, handle exception 14404 #if defined(WITH_JIT) 14405 /* 14406 * If the JIT is actively building a trace we need to make sure 14407 * that the field is fully resolved before including this instruction. 14408 */ 14409 bl common_verifyField 14410 #endif 14411 b .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ resume 14412 14413 /* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */ 14414 14415 14416 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end: 14417 str r1, [r0, #offStaticField_value] @ field<- vBBBB 14418 SMP_DMB 14419 cmp r1, #0 @ stored a null object? 14420 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 14421 GOTO_OPCODE(ip) @ jump to next instruction 14422 14423 /* Continuation if the field has not yet been resolved. 14424 * r1: AAAAaaaa field ref 14425 * r10: dvmDex->pResFields 14426 */ 14427 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_resolve: 14428 ldr r2, [rSELF, #offThread_method] @ r9<- current method 14429 #if defined(WITH_JIT) 14430 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field] 14431 #endif 14432 EXPORT_PC() @ resolve() could throw, so export now 14433 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 14434 bl dvmResolveStaticField @ r0<- resolved StaticField ptr 14435 cmp r0, #0 @ success? 14436 beq common_exceptionThrown @ no, handle exception 14437 #if defined(WITH_JIT) 14438 /* 14439 * If the JIT is actively building a trace we need to make sure 14440 * that the field is fully resolved before including this instruction. 14441 */ 14442 bl common_verifyField 14443 #endif 14444 b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ resume 14445 14446 14447 .size dvmAsmSisterStart, .-dvmAsmSisterStart 14448 .global dvmAsmSisterEnd 14449 dvmAsmSisterEnd: 14450 14451 14452 .global dvmAsmAltInstructionStart 14453 .type dvmAsmAltInstructionStart, %function 14454 .text 14455 14456 dvmAsmAltInstructionStart = .L_ALT_OP_NOP 14457 /* ------------------------------ */ 14458 .balign 64 14459 .L_ALT_OP_NOP: /* 0x00 */ 14460 /* File: armv5te/alt_stub.S */ 14461 /* 14462 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14463 * any interesting requests and then jump to the real instruction 14464 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14465 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14466 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14467 * bail to the real handler if breakFlags==0. 14468 */ 14469 ldrb r3, [rSELF, #offThread_breakFlags] 14470 adrl lr, dvmAsmInstructionStart + (0 * 64) 14471 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14472 cmp r3, #0 14473 bxeq lr @ nothing to do - jump to real handler 14474 EXPORT_PC() 14475 mov r0, rPC @ arg0 14476 mov r1, rFP @ arg1 14477 mov r2, rSELF @ arg2 14478 b dvmCheckBefore @ (dPC,dFP,self) tail call 14479 14480 /* ------------------------------ */ 14481 .balign 64 14482 .L_ALT_OP_MOVE: /* 0x01 */ 14483 /* File: armv5te/alt_stub.S */ 14484 /* 14485 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14486 * any interesting requests and then jump to the real instruction 14487 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14488 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14489 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14490 * bail to the real handler if breakFlags==0. 14491 */ 14492 ldrb r3, [rSELF, #offThread_breakFlags] 14493 adrl lr, dvmAsmInstructionStart + (1 * 64) 14494 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14495 cmp r3, #0 14496 bxeq lr @ nothing to do - jump to real handler 14497 EXPORT_PC() 14498 mov r0, rPC @ arg0 14499 mov r1, rFP @ arg1 14500 mov r2, rSELF @ arg2 14501 b dvmCheckBefore @ (dPC,dFP,self) tail call 14502 14503 /* ------------------------------ */ 14504 .balign 64 14505 .L_ALT_OP_MOVE_FROM16: /* 0x02 */ 14506 /* File: armv5te/alt_stub.S */ 14507 /* 14508 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14509 * any interesting requests and then jump to the real instruction 14510 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14511 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14512 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14513 * bail to the real handler if breakFlags==0. 14514 */ 14515 ldrb r3, [rSELF, #offThread_breakFlags] 14516 adrl lr, dvmAsmInstructionStart + (2 * 64) 14517 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14518 cmp r3, #0 14519 bxeq lr @ nothing to do - jump to real handler 14520 EXPORT_PC() 14521 mov r0, rPC @ arg0 14522 mov r1, rFP @ arg1 14523 mov r2, rSELF @ arg2 14524 b dvmCheckBefore @ (dPC,dFP,self) tail call 14525 14526 /* ------------------------------ */ 14527 .balign 64 14528 .L_ALT_OP_MOVE_16: /* 0x03 */ 14529 /* File: armv5te/alt_stub.S */ 14530 /* 14531 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14532 * any interesting requests and then jump to the real instruction 14533 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14534 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14535 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14536 * bail to the real handler if breakFlags==0. 14537 */ 14538 ldrb r3, [rSELF, #offThread_breakFlags] 14539 adrl lr, dvmAsmInstructionStart + (3 * 64) 14540 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14541 cmp r3, #0 14542 bxeq lr @ nothing to do - jump to real handler 14543 EXPORT_PC() 14544 mov r0, rPC @ arg0 14545 mov r1, rFP @ arg1 14546 mov r2, rSELF @ arg2 14547 b dvmCheckBefore @ (dPC,dFP,self) tail call 14548 14549 /* ------------------------------ */ 14550 .balign 64 14551 .L_ALT_OP_MOVE_WIDE: /* 0x04 */ 14552 /* File: armv5te/alt_stub.S */ 14553 /* 14554 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14555 * any interesting requests and then jump to the real instruction 14556 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14557 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14558 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14559 * bail to the real handler if breakFlags==0. 14560 */ 14561 ldrb r3, [rSELF, #offThread_breakFlags] 14562 adrl lr, dvmAsmInstructionStart + (4 * 64) 14563 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14564 cmp r3, #0 14565 bxeq lr @ nothing to do - jump to real handler 14566 EXPORT_PC() 14567 mov r0, rPC @ arg0 14568 mov r1, rFP @ arg1 14569 mov r2, rSELF @ arg2 14570 b dvmCheckBefore @ (dPC,dFP,self) tail call 14571 14572 /* ------------------------------ */ 14573 .balign 64 14574 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */ 14575 /* File: armv5te/alt_stub.S */ 14576 /* 14577 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14578 * any interesting requests and then jump to the real instruction 14579 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14580 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14581 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14582 * bail to the real handler if breakFlags==0. 14583 */ 14584 ldrb r3, [rSELF, #offThread_breakFlags] 14585 adrl lr, dvmAsmInstructionStart + (5 * 64) 14586 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14587 cmp r3, #0 14588 bxeq lr @ nothing to do - jump to real handler 14589 EXPORT_PC() 14590 mov r0, rPC @ arg0 14591 mov r1, rFP @ arg1 14592 mov r2, rSELF @ arg2 14593 b dvmCheckBefore @ (dPC,dFP,self) tail call 14594 14595 /* ------------------------------ */ 14596 .balign 64 14597 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */ 14598 /* File: armv5te/alt_stub.S */ 14599 /* 14600 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14601 * any interesting requests and then jump to the real instruction 14602 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14603 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14604 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14605 * bail to the real handler if breakFlags==0. 14606 */ 14607 ldrb r3, [rSELF, #offThread_breakFlags] 14608 adrl lr, dvmAsmInstructionStart + (6 * 64) 14609 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14610 cmp r3, #0 14611 bxeq lr @ nothing to do - jump to real handler 14612 EXPORT_PC() 14613 mov r0, rPC @ arg0 14614 mov r1, rFP @ arg1 14615 mov r2, rSELF @ arg2 14616 b dvmCheckBefore @ (dPC,dFP,self) tail call 14617 14618 /* ------------------------------ */ 14619 .balign 64 14620 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */ 14621 /* File: armv5te/alt_stub.S */ 14622 /* 14623 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14624 * any interesting requests and then jump to the real instruction 14625 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14626 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14627 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14628 * bail to the real handler if breakFlags==0. 14629 */ 14630 ldrb r3, [rSELF, #offThread_breakFlags] 14631 adrl lr, dvmAsmInstructionStart + (7 * 64) 14632 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14633 cmp r3, #0 14634 bxeq lr @ nothing to do - jump to real handler 14635 EXPORT_PC() 14636 mov r0, rPC @ arg0 14637 mov r1, rFP @ arg1 14638 mov r2, rSELF @ arg2 14639 b dvmCheckBefore @ (dPC,dFP,self) tail call 14640 14641 /* ------------------------------ */ 14642 .balign 64 14643 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 14644 /* File: armv5te/alt_stub.S */ 14645 /* 14646 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14647 * any interesting requests and then jump to the real instruction 14648 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14649 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14650 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14651 * bail to the real handler if breakFlags==0. 14652 */ 14653 ldrb r3, [rSELF, #offThread_breakFlags] 14654 adrl lr, dvmAsmInstructionStart + (8 * 64) 14655 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14656 cmp r3, #0 14657 bxeq lr @ nothing to do - jump to real handler 14658 EXPORT_PC() 14659 mov r0, rPC @ arg0 14660 mov r1, rFP @ arg1 14661 mov r2, rSELF @ arg2 14662 b dvmCheckBefore @ (dPC,dFP,self) tail call 14663 14664 /* ------------------------------ */ 14665 .balign 64 14666 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */ 14667 /* File: armv5te/alt_stub.S */ 14668 /* 14669 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14670 * any interesting requests and then jump to the real instruction 14671 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14672 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14673 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14674 * bail to the real handler if breakFlags==0. 14675 */ 14676 ldrb r3, [rSELF, #offThread_breakFlags] 14677 adrl lr, dvmAsmInstructionStart + (9 * 64) 14678 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14679 cmp r3, #0 14680 bxeq lr @ nothing to do - jump to real handler 14681 EXPORT_PC() 14682 mov r0, rPC @ arg0 14683 mov r1, rFP @ arg1 14684 mov r2, rSELF @ arg2 14685 b dvmCheckBefore @ (dPC,dFP,self) tail call 14686 14687 /* ------------------------------ */ 14688 .balign 64 14689 .L_ALT_OP_MOVE_RESULT: /* 0x0a */ 14690 /* File: armv5te/alt_stub.S */ 14691 /* 14692 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14693 * any interesting requests and then jump to the real instruction 14694 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14695 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14696 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14697 * bail to the real handler if breakFlags==0. 14698 */ 14699 ldrb r3, [rSELF, #offThread_breakFlags] 14700 adrl lr, dvmAsmInstructionStart + (10 * 64) 14701 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14702 cmp r3, #0 14703 bxeq lr @ nothing to do - jump to real handler 14704 EXPORT_PC() 14705 mov r0, rPC @ arg0 14706 mov r1, rFP @ arg1 14707 mov r2, rSELF @ arg2 14708 b dvmCheckBefore @ (dPC,dFP,self) tail call 14709 14710 /* ------------------------------ */ 14711 .balign 64 14712 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */ 14713 /* File: armv5te/alt_stub.S */ 14714 /* 14715 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14716 * any interesting requests and then jump to the real instruction 14717 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14718 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14719 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14720 * bail to the real handler if breakFlags==0. 14721 */ 14722 ldrb r3, [rSELF, #offThread_breakFlags] 14723 adrl lr, dvmAsmInstructionStart + (11 * 64) 14724 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14725 cmp r3, #0 14726 bxeq lr @ nothing to do - jump to real handler 14727 EXPORT_PC() 14728 mov r0, rPC @ arg0 14729 mov r1, rFP @ arg1 14730 mov r2, rSELF @ arg2 14731 b dvmCheckBefore @ (dPC,dFP,self) tail call 14732 14733 /* ------------------------------ */ 14734 .balign 64 14735 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 14736 /* File: armv5te/alt_stub.S */ 14737 /* 14738 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14739 * any interesting requests and then jump to the real instruction 14740 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14741 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14742 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14743 * bail to the real handler if breakFlags==0. 14744 */ 14745 ldrb r3, [rSELF, #offThread_breakFlags] 14746 adrl lr, dvmAsmInstructionStart + (12 * 64) 14747 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14748 cmp r3, #0 14749 bxeq lr @ nothing to do - jump to real handler 14750 EXPORT_PC() 14751 mov r0, rPC @ arg0 14752 mov r1, rFP @ arg1 14753 mov r2, rSELF @ arg2 14754 b dvmCheckBefore @ (dPC,dFP,self) tail call 14755 14756 /* ------------------------------ */ 14757 .balign 64 14758 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */ 14759 /* File: armv5te/alt_stub.S */ 14760 /* 14761 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14762 * any interesting requests and then jump to the real instruction 14763 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14764 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14765 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14766 * bail to the real handler if breakFlags==0. 14767 */ 14768 ldrb r3, [rSELF, #offThread_breakFlags] 14769 adrl lr, dvmAsmInstructionStart + (13 * 64) 14770 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14771 cmp r3, #0 14772 bxeq lr @ nothing to do - jump to real handler 14773 EXPORT_PC() 14774 mov r0, rPC @ arg0 14775 mov r1, rFP @ arg1 14776 mov r2, rSELF @ arg2 14777 b dvmCheckBefore @ (dPC,dFP,self) tail call 14778 14779 /* ------------------------------ */ 14780 .balign 64 14781 .L_ALT_OP_RETURN_VOID: /* 0x0e */ 14782 /* File: armv5te/alt_stub.S */ 14783 /* 14784 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14785 * any interesting requests and then jump to the real instruction 14786 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14787 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14788 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14789 * bail to the real handler if breakFlags==0. 14790 */ 14791 ldrb r3, [rSELF, #offThread_breakFlags] 14792 adrl lr, dvmAsmInstructionStart + (14 * 64) 14793 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14794 cmp r3, #0 14795 bxeq lr @ nothing to do - jump to real handler 14796 EXPORT_PC() 14797 mov r0, rPC @ arg0 14798 mov r1, rFP @ arg1 14799 mov r2, rSELF @ arg2 14800 b dvmCheckBefore @ (dPC,dFP,self) tail call 14801 14802 /* ------------------------------ */ 14803 .balign 64 14804 .L_ALT_OP_RETURN: /* 0x0f */ 14805 /* File: armv5te/alt_stub.S */ 14806 /* 14807 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14808 * any interesting requests and then jump to the real instruction 14809 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14810 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14811 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14812 * bail to the real handler if breakFlags==0. 14813 */ 14814 ldrb r3, [rSELF, #offThread_breakFlags] 14815 adrl lr, dvmAsmInstructionStart + (15 * 64) 14816 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14817 cmp r3, #0 14818 bxeq lr @ nothing to do - jump to real handler 14819 EXPORT_PC() 14820 mov r0, rPC @ arg0 14821 mov r1, rFP @ arg1 14822 mov r2, rSELF @ arg2 14823 b dvmCheckBefore @ (dPC,dFP,self) tail call 14824 14825 /* ------------------------------ */ 14826 .balign 64 14827 .L_ALT_OP_RETURN_WIDE: /* 0x10 */ 14828 /* File: armv5te/alt_stub.S */ 14829 /* 14830 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14831 * any interesting requests and then jump to the real instruction 14832 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14833 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14834 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14835 * bail to the real handler if breakFlags==0. 14836 */ 14837 ldrb r3, [rSELF, #offThread_breakFlags] 14838 adrl lr, dvmAsmInstructionStart + (16 * 64) 14839 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14840 cmp r3, #0 14841 bxeq lr @ nothing to do - jump to real handler 14842 EXPORT_PC() 14843 mov r0, rPC @ arg0 14844 mov r1, rFP @ arg1 14845 mov r2, rSELF @ arg2 14846 b dvmCheckBefore @ (dPC,dFP,self) tail call 14847 14848 /* ------------------------------ */ 14849 .balign 64 14850 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */ 14851 /* File: armv5te/alt_stub.S */ 14852 /* 14853 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14854 * any interesting requests and then jump to the real instruction 14855 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14856 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14857 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14858 * bail to the real handler if breakFlags==0. 14859 */ 14860 ldrb r3, [rSELF, #offThread_breakFlags] 14861 adrl lr, dvmAsmInstructionStart + (17 * 64) 14862 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14863 cmp r3, #0 14864 bxeq lr @ nothing to do - jump to real handler 14865 EXPORT_PC() 14866 mov r0, rPC @ arg0 14867 mov r1, rFP @ arg1 14868 mov r2, rSELF @ arg2 14869 b dvmCheckBefore @ (dPC,dFP,self) tail call 14870 14871 /* ------------------------------ */ 14872 .balign 64 14873 .L_ALT_OP_CONST_4: /* 0x12 */ 14874 /* File: armv5te/alt_stub.S */ 14875 /* 14876 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14877 * any interesting requests and then jump to the real instruction 14878 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14879 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14880 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14881 * bail to the real handler if breakFlags==0. 14882 */ 14883 ldrb r3, [rSELF, #offThread_breakFlags] 14884 adrl lr, dvmAsmInstructionStart + (18 * 64) 14885 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14886 cmp r3, #0 14887 bxeq lr @ nothing to do - jump to real handler 14888 EXPORT_PC() 14889 mov r0, rPC @ arg0 14890 mov r1, rFP @ arg1 14891 mov r2, rSELF @ arg2 14892 b dvmCheckBefore @ (dPC,dFP,self) tail call 14893 14894 /* ------------------------------ */ 14895 .balign 64 14896 .L_ALT_OP_CONST_16: /* 0x13 */ 14897 /* File: armv5te/alt_stub.S */ 14898 /* 14899 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14900 * any interesting requests and then jump to the real instruction 14901 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14902 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14903 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14904 * bail to the real handler if breakFlags==0. 14905 */ 14906 ldrb r3, [rSELF, #offThread_breakFlags] 14907 adrl lr, dvmAsmInstructionStart + (19 * 64) 14908 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14909 cmp r3, #0 14910 bxeq lr @ nothing to do - jump to real handler 14911 EXPORT_PC() 14912 mov r0, rPC @ arg0 14913 mov r1, rFP @ arg1 14914 mov r2, rSELF @ arg2 14915 b dvmCheckBefore @ (dPC,dFP,self) tail call 14916 14917 /* ------------------------------ */ 14918 .balign 64 14919 .L_ALT_OP_CONST: /* 0x14 */ 14920 /* File: armv5te/alt_stub.S */ 14921 /* 14922 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14923 * any interesting requests and then jump to the real instruction 14924 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14925 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14926 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14927 * bail to the real handler if breakFlags==0. 14928 */ 14929 ldrb r3, [rSELF, #offThread_breakFlags] 14930 adrl lr, dvmAsmInstructionStart + (20 * 64) 14931 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14932 cmp r3, #0 14933 bxeq lr @ nothing to do - jump to real handler 14934 EXPORT_PC() 14935 mov r0, rPC @ arg0 14936 mov r1, rFP @ arg1 14937 mov r2, rSELF @ arg2 14938 b dvmCheckBefore @ (dPC,dFP,self) tail call 14939 14940 /* ------------------------------ */ 14941 .balign 64 14942 .L_ALT_OP_CONST_HIGH16: /* 0x15 */ 14943 /* File: armv5te/alt_stub.S */ 14944 /* 14945 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14946 * any interesting requests and then jump to the real instruction 14947 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14948 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14949 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14950 * bail to the real handler if breakFlags==0. 14951 */ 14952 ldrb r3, [rSELF, #offThread_breakFlags] 14953 adrl lr, dvmAsmInstructionStart + (21 * 64) 14954 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14955 cmp r3, #0 14956 bxeq lr @ nothing to do - jump to real handler 14957 EXPORT_PC() 14958 mov r0, rPC @ arg0 14959 mov r1, rFP @ arg1 14960 mov r2, rSELF @ arg2 14961 b dvmCheckBefore @ (dPC,dFP,self) tail call 14962 14963 /* ------------------------------ */ 14964 .balign 64 14965 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */ 14966 /* File: armv5te/alt_stub.S */ 14967 /* 14968 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14969 * any interesting requests and then jump to the real instruction 14970 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14971 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14972 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14973 * bail to the real handler if breakFlags==0. 14974 */ 14975 ldrb r3, [rSELF, #offThread_breakFlags] 14976 adrl lr, dvmAsmInstructionStart + (22 * 64) 14977 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 14978 cmp r3, #0 14979 bxeq lr @ nothing to do - jump to real handler 14980 EXPORT_PC() 14981 mov r0, rPC @ arg0 14982 mov r1, rFP @ arg1 14983 mov r2, rSELF @ arg2 14984 b dvmCheckBefore @ (dPC,dFP,self) tail call 14985 14986 /* ------------------------------ */ 14987 .balign 64 14988 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */ 14989 /* File: armv5te/alt_stub.S */ 14990 /* 14991 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 14992 * any interesting requests and then jump to the real instruction 14993 * handler. Note that the call to dvmCheckBefore is done as a tail call. 14994 * rIBASE updates won't be seen until a refresh, and we can tell we have a 14995 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 14996 * bail to the real handler if breakFlags==0. 14997 */ 14998 ldrb r3, [rSELF, #offThread_breakFlags] 14999 adrl lr, dvmAsmInstructionStart + (23 * 64) 15000 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15001 cmp r3, #0 15002 bxeq lr @ nothing to do - jump to real handler 15003 EXPORT_PC() 15004 mov r0, rPC @ arg0 15005 mov r1, rFP @ arg1 15006 mov r2, rSELF @ arg2 15007 b dvmCheckBefore @ (dPC,dFP,self) tail call 15008 15009 /* ------------------------------ */ 15010 .balign 64 15011 .L_ALT_OP_CONST_WIDE: /* 0x18 */ 15012 /* File: armv5te/alt_stub.S */ 15013 /* 15014 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15015 * any interesting requests and then jump to the real instruction 15016 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15017 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15018 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15019 * bail to the real handler if breakFlags==0. 15020 */ 15021 ldrb r3, [rSELF, #offThread_breakFlags] 15022 adrl lr, dvmAsmInstructionStart + (24 * 64) 15023 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15024 cmp r3, #0 15025 bxeq lr @ nothing to do - jump to real handler 15026 EXPORT_PC() 15027 mov r0, rPC @ arg0 15028 mov r1, rFP @ arg1 15029 mov r2, rSELF @ arg2 15030 b dvmCheckBefore @ (dPC,dFP,self) tail call 15031 15032 /* ------------------------------ */ 15033 .balign 64 15034 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */ 15035 /* File: armv5te/alt_stub.S */ 15036 /* 15037 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15038 * any interesting requests and then jump to the real instruction 15039 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15040 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15041 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15042 * bail to the real handler if breakFlags==0. 15043 */ 15044 ldrb r3, [rSELF, #offThread_breakFlags] 15045 adrl lr, dvmAsmInstructionStart + (25 * 64) 15046 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15047 cmp r3, #0 15048 bxeq lr @ nothing to do - jump to real handler 15049 EXPORT_PC() 15050 mov r0, rPC @ arg0 15051 mov r1, rFP @ arg1 15052 mov r2, rSELF @ arg2 15053 b dvmCheckBefore @ (dPC,dFP,self) tail call 15054 15055 /* ------------------------------ */ 15056 .balign 64 15057 .L_ALT_OP_CONST_STRING: /* 0x1a */ 15058 /* File: armv5te/alt_stub.S */ 15059 /* 15060 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15061 * any interesting requests and then jump to the real instruction 15062 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15063 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15064 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15065 * bail to the real handler if breakFlags==0. 15066 */ 15067 ldrb r3, [rSELF, #offThread_breakFlags] 15068 adrl lr, dvmAsmInstructionStart + (26 * 64) 15069 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15070 cmp r3, #0 15071 bxeq lr @ nothing to do - jump to real handler 15072 EXPORT_PC() 15073 mov r0, rPC @ arg0 15074 mov r1, rFP @ arg1 15075 mov r2, rSELF @ arg2 15076 b dvmCheckBefore @ (dPC,dFP,self) tail call 15077 15078 /* ------------------------------ */ 15079 .balign 64 15080 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */ 15081 /* File: armv5te/alt_stub.S */ 15082 /* 15083 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15084 * any interesting requests and then jump to the real instruction 15085 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15086 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15087 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15088 * bail to the real handler if breakFlags==0. 15089 */ 15090 ldrb r3, [rSELF, #offThread_breakFlags] 15091 adrl lr, dvmAsmInstructionStart + (27 * 64) 15092 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15093 cmp r3, #0 15094 bxeq lr @ nothing to do - jump to real handler 15095 EXPORT_PC() 15096 mov r0, rPC @ arg0 15097 mov r1, rFP @ arg1 15098 mov r2, rSELF @ arg2 15099 b dvmCheckBefore @ (dPC,dFP,self) tail call 15100 15101 /* ------------------------------ */ 15102 .balign 64 15103 .L_ALT_OP_CONST_CLASS: /* 0x1c */ 15104 /* File: armv5te/alt_stub.S */ 15105 /* 15106 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15107 * any interesting requests and then jump to the real instruction 15108 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15109 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15110 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15111 * bail to the real handler if breakFlags==0. 15112 */ 15113 ldrb r3, [rSELF, #offThread_breakFlags] 15114 adrl lr, dvmAsmInstructionStart + (28 * 64) 15115 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15116 cmp r3, #0 15117 bxeq lr @ nothing to do - jump to real handler 15118 EXPORT_PC() 15119 mov r0, rPC @ arg0 15120 mov r1, rFP @ arg1 15121 mov r2, rSELF @ arg2 15122 b dvmCheckBefore @ (dPC,dFP,self) tail call 15123 15124 /* ------------------------------ */ 15125 .balign 64 15126 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */ 15127 /* File: armv5te/alt_stub.S */ 15128 /* 15129 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15130 * any interesting requests and then jump to the real instruction 15131 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15132 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15133 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15134 * bail to the real handler if breakFlags==0. 15135 */ 15136 ldrb r3, [rSELF, #offThread_breakFlags] 15137 adrl lr, dvmAsmInstructionStart + (29 * 64) 15138 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15139 cmp r3, #0 15140 bxeq lr @ nothing to do - jump to real handler 15141 EXPORT_PC() 15142 mov r0, rPC @ arg0 15143 mov r1, rFP @ arg1 15144 mov r2, rSELF @ arg2 15145 b dvmCheckBefore @ (dPC,dFP,self) tail call 15146 15147 /* ------------------------------ */ 15148 .balign 64 15149 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */ 15150 /* File: armv5te/alt_stub.S */ 15151 /* 15152 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15153 * any interesting requests and then jump to the real instruction 15154 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15155 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15156 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15157 * bail to the real handler if breakFlags==0. 15158 */ 15159 ldrb r3, [rSELF, #offThread_breakFlags] 15160 adrl lr, dvmAsmInstructionStart + (30 * 64) 15161 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15162 cmp r3, #0 15163 bxeq lr @ nothing to do - jump to real handler 15164 EXPORT_PC() 15165 mov r0, rPC @ arg0 15166 mov r1, rFP @ arg1 15167 mov r2, rSELF @ arg2 15168 b dvmCheckBefore @ (dPC,dFP,self) tail call 15169 15170 /* ------------------------------ */ 15171 .balign 64 15172 .L_ALT_OP_CHECK_CAST: /* 0x1f */ 15173 /* File: armv5te/alt_stub.S */ 15174 /* 15175 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15176 * any interesting requests and then jump to the real instruction 15177 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15178 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15179 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15180 * bail to the real handler if breakFlags==0. 15181 */ 15182 ldrb r3, [rSELF, #offThread_breakFlags] 15183 adrl lr, dvmAsmInstructionStart + (31 * 64) 15184 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15185 cmp r3, #0 15186 bxeq lr @ nothing to do - jump to real handler 15187 EXPORT_PC() 15188 mov r0, rPC @ arg0 15189 mov r1, rFP @ arg1 15190 mov r2, rSELF @ arg2 15191 b dvmCheckBefore @ (dPC,dFP,self) tail call 15192 15193 /* ------------------------------ */ 15194 .balign 64 15195 .L_ALT_OP_INSTANCE_OF: /* 0x20 */ 15196 /* File: armv5te/alt_stub.S */ 15197 /* 15198 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15199 * any interesting requests and then jump to the real instruction 15200 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15201 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15202 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15203 * bail to the real handler if breakFlags==0. 15204 */ 15205 ldrb r3, [rSELF, #offThread_breakFlags] 15206 adrl lr, dvmAsmInstructionStart + (32 * 64) 15207 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15208 cmp r3, #0 15209 bxeq lr @ nothing to do - jump to real handler 15210 EXPORT_PC() 15211 mov r0, rPC @ arg0 15212 mov r1, rFP @ arg1 15213 mov r2, rSELF @ arg2 15214 b dvmCheckBefore @ (dPC,dFP,self) tail call 15215 15216 /* ------------------------------ */ 15217 .balign 64 15218 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */ 15219 /* File: armv5te/alt_stub.S */ 15220 /* 15221 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15222 * any interesting requests and then jump to the real instruction 15223 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15224 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15225 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15226 * bail to the real handler if breakFlags==0. 15227 */ 15228 ldrb r3, [rSELF, #offThread_breakFlags] 15229 adrl lr, dvmAsmInstructionStart + (33 * 64) 15230 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15231 cmp r3, #0 15232 bxeq lr @ nothing to do - jump to real handler 15233 EXPORT_PC() 15234 mov r0, rPC @ arg0 15235 mov r1, rFP @ arg1 15236 mov r2, rSELF @ arg2 15237 b dvmCheckBefore @ (dPC,dFP,self) tail call 15238 15239 /* ------------------------------ */ 15240 .balign 64 15241 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */ 15242 /* File: armv5te/alt_stub.S */ 15243 /* 15244 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15245 * any interesting requests and then jump to the real instruction 15246 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15247 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15248 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15249 * bail to the real handler if breakFlags==0. 15250 */ 15251 ldrb r3, [rSELF, #offThread_breakFlags] 15252 adrl lr, dvmAsmInstructionStart + (34 * 64) 15253 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15254 cmp r3, #0 15255 bxeq lr @ nothing to do - jump to real handler 15256 EXPORT_PC() 15257 mov r0, rPC @ arg0 15258 mov r1, rFP @ arg1 15259 mov r2, rSELF @ arg2 15260 b dvmCheckBefore @ (dPC,dFP,self) tail call 15261 15262 /* ------------------------------ */ 15263 .balign 64 15264 .L_ALT_OP_NEW_ARRAY: /* 0x23 */ 15265 /* File: armv5te/alt_stub.S */ 15266 /* 15267 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15268 * any interesting requests and then jump to the real instruction 15269 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15270 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15271 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15272 * bail to the real handler if breakFlags==0. 15273 */ 15274 ldrb r3, [rSELF, #offThread_breakFlags] 15275 adrl lr, dvmAsmInstructionStart + (35 * 64) 15276 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15277 cmp r3, #0 15278 bxeq lr @ nothing to do - jump to real handler 15279 EXPORT_PC() 15280 mov r0, rPC @ arg0 15281 mov r1, rFP @ arg1 15282 mov r2, rSELF @ arg2 15283 b dvmCheckBefore @ (dPC,dFP,self) tail call 15284 15285 /* ------------------------------ */ 15286 .balign 64 15287 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */ 15288 /* File: armv5te/alt_stub.S */ 15289 /* 15290 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15291 * any interesting requests and then jump to the real instruction 15292 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15293 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15294 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15295 * bail to the real handler if breakFlags==0. 15296 */ 15297 ldrb r3, [rSELF, #offThread_breakFlags] 15298 adrl lr, dvmAsmInstructionStart + (36 * 64) 15299 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15300 cmp r3, #0 15301 bxeq lr @ nothing to do - jump to real handler 15302 EXPORT_PC() 15303 mov r0, rPC @ arg0 15304 mov r1, rFP @ arg1 15305 mov r2, rSELF @ arg2 15306 b dvmCheckBefore @ (dPC,dFP,self) tail call 15307 15308 /* ------------------------------ */ 15309 .balign 64 15310 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 15311 /* File: armv5te/alt_stub.S */ 15312 /* 15313 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15314 * any interesting requests and then jump to the real instruction 15315 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15316 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15317 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15318 * bail to the real handler if breakFlags==0. 15319 */ 15320 ldrb r3, [rSELF, #offThread_breakFlags] 15321 adrl lr, dvmAsmInstructionStart + (37 * 64) 15322 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15323 cmp r3, #0 15324 bxeq lr @ nothing to do - jump to real handler 15325 EXPORT_PC() 15326 mov r0, rPC @ arg0 15327 mov r1, rFP @ arg1 15328 mov r2, rSELF @ arg2 15329 b dvmCheckBefore @ (dPC,dFP,self) tail call 15330 15331 /* ------------------------------ */ 15332 .balign 64 15333 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */ 15334 /* File: armv5te/alt_stub.S */ 15335 /* 15336 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15337 * any interesting requests and then jump to the real instruction 15338 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15339 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15340 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15341 * bail to the real handler if breakFlags==0. 15342 */ 15343 ldrb r3, [rSELF, #offThread_breakFlags] 15344 adrl lr, dvmAsmInstructionStart + (38 * 64) 15345 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15346 cmp r3, #0 15347 bxeq lr @ nothing to do - jump to real handler 15348 EXPORT_PC() 15349 mov r0, rPC @ arg0 15350 mov r1, rFP @ arg1 15351 mov r2, rSELF @ arg2 15352 b dvmCheckBefore @ (dPC,dFP,self) tail call 15353 15354 /* ------------------------------ */ 15355 .balign 64 15356 .L_ALT_OP_THROW: /* 0x27 */ 15357 /* File: armv5te/alt_stub.S */ 15358 /* 15359 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15360 * any interesting requests and then jump to the real instruction 15361 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15362 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15363 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15364 * bail to the real handler if breakFlags==0. 15365 */ 15366 ldrb r3, [rSELF, #offThread_breakFlags] 15367 adrl lr, dvmAsmInstructionStart + (39 * 64) 15368 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15369 cmp r3, #0 15370 bxeq lr @ nothing to do - jump to real handler 15371 EXPORT_PC() 15372 mov r0, rPC @ arg0 15373 mov r1, rFP @ arg1 15374 mov r2, rSELF @ arg2 15375 b dvmCheckBefore @ (dPC,dFP,self) tail call 15376 15377 /* ------------------------------ */ 15378 .balign 64 15379 .L_ALT_OP_GOTO: /* 0x28 */ 15380 /* File: armv5te/alt_stub.S */ 15381 /* 15382 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15383 * any interesting requests and then jump to the real instruction 15384 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15385 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15386 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15387 * bail to the real handler if breakFlags==0. 15388 */ 15389 ldrb r3, [rSELF, #offThread_breakFlags] 15390 adrl lr, dvmAsmInstructionStart + (40 * 64) 15391 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15392 cmp r3, #0 15393 bxeq lr @ nothing to do - jump to real handler 15394 EXPORT_PC() 15395 mov r0, rPC @ arg0 15396 mov r1, rFP @ arg1 15397 mov r2, rSELF @ arg2 15398 b dvmCheckBefore @ (dPC,dFP,self) tail call 15399 15400 /* ------------------------------ */ 15401 .balign 64 15402 .L_ALT_OP_GOTO_16: /* 0x29 */ 15403 /* File: armv5te/alt_stub.S */ 15404 /* 15405 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15406 * any interesting requests and then jump to the real instruction 15407 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15408 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15409 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15410 * bail to the real handler if breakFlags==0. 15411 */ 15412 ldrb r3, [rSELF, #offThread_breakFlags] 15413 adrl lr, dvmAsmInstructionStart + (41 * 64) 15414 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15415 cmp r3, #0 15416 bxeq lr @ nothing to do - jump to real handler 15417 EXPORT_PC() 15418 mov r0, rPC @ arg0 15419 mov r1, rFP @ arg1 15420 mov r2, rSELF @ arg2 15421 b dvmCheckBefore @ (dPC,dFP,self) tail call 15422 15423 /* ------------------------------ */ 15424 .balign 64 15425 .L_ALT_OP_GOTO_32: /* 0x2a */ 15426 /* File: armv5te/alt_stub.S */ 15427 /* 15428 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15429 * any interesting requests and then jump to the real instruction 15430 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15431 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15432 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15433 * bail to the real handler if breakFlags==0. 15434 */ 15435 ldrb r3, [rSELF, #offThread_breakFlags] 15436 adrl lr, dvmAsmInstructionStart + (42 * 64) 15437 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15438 cmp r3, #0 15439 bxeq lr @ nothing to do - jump to real handler 15440 EXPORT_PC() 15441 mov r0, rPC @ arg0 15442 mov r1, rFP @ arg1 15443 mov r2, rSELF @ arg2 15444 b dvmCheckBefore @ (dPC,dFP,self) tail call 15445 15446 /* ------------------------------ */ 15447 .balign 64 15448 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */ 15449 /* File: armv5te/alt_stub.S */ 15450 /* 15451 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15452 * any interesting requests and then jump to the real instruction 15453 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15454 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15455 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15456 * bail to the real handler if breakFlags==0. 15457 */ 15458 ldrb r3, [rSELF, #offThread_breakFlags] 15459 adrl lr, dvmAsmInstructionStart + (43 * 64) 15460 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15461 cmp r3, #0 15462 bxeq lr @ nothing to do - jump to real handler 15463 EXPORT_PC() 15464 mov r0, rPC @ arg0 15465 mov r1, rFP @ arg1 15466 mov r2, rSELF @ arg2 15467 b dvmCheckBefore @ (dPC,dFP,self) tail call 15468 15469 /* ------------------------------ */ 15470 .balign 64 15471 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */ 15472 /* File: armv5te/alt_stub.S */ 15473 /* 15474 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15475 * any interesting requests and then jump to the real instruction 15476 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15477 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15478 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15479 * bail to the real handler if breakFlags==0. 15480 */ 15481 ldrb r3, [rSELF, #offThread_breakFlags] 15482 adrl lr, dvmAsmInstructionStart + (44 * 64) 15483 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15484 cmp r3, #0 15485 bxeq lr @ nothing to do - jump to real handler 15486 EXPORT_PC() 15487 mov r0, rPC @ arg0 15488 mov r1, rFP @ arg1 15489 mov r2, rSELF @ arg2 15490 b dvmCheckBefore @ (dPC,dFP,self) tail call 15491 15492 /* ------------------------------ */ 15493 .balign 64 15494 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */ 15495 /* File: armv5te/alt_stub.S */ 15496 /* 15497 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15498 * any interesting requests and then jump to the real instruction 15499 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15500 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15501 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15502 * bail to the real handler if breakFlags==0. 15503 */ 15504 ldrb r3, [rSELF, #offThread_breakFlags] 15505 adrl lr, dvmAsmInstructionStart + (45 * 64) 15506 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15507 cmp r3, #0 15508 bxeq lr @ nothing to do - jump to real handler 15509 EXPORT_PC() 15510 mov r0, rPC @ arg0 15511 mov r1, rFP @ arg1 15512 mov r2, rSELF @ arg2 15513 b dvmCheckBefore @ (dPC,dFP,self) tail call 15514 15515 /* ------------------------------ */ 15516 .balign 64 15517 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */ 15518 /* File: armv5te/alt_stub.S */ 15519 /* 15520 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15521 * any interesting requests and then jump to the real instruction 15522 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15523 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15524 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15525 * bail to the real handler if breakFlags==0. 15526 */ 15527 ldrb r3, [rSELF, #offThread_breakFlags] 15528 adrl lr, dvmAsmInstructionStart + (46 * 64) 15529 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15530 cmp r3, #0 15531 bxeq lr @ nothing to do - jump to real handler 15532 EXPORT_PC() 15533 mov r0, rPC @ arg0 15534 mov r1, rFP @ arg1 15535 mov r2, rSELF @ arg2 15536 b dvmCheckBefore @ (dPC,dFP,self) tail call 15537 15538 /* ------------------------------ */ 15539 .balign 64 15540 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */ 15541 /* File: armv5te/alt_stub.S */ 15542 /* 15543 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15544 * any interesting requests and then jump to the real instruction 15545 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15546 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15547 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15548 * bail to the real handler if breakFlags==0. 15549 */ 15550 ldrb r3, [rSELF, #offThread_breakFlags] 15551 adrl lr, dvmAsmInstructionStart + (47 * 64) 15552 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15553 cmp r3, #0 15554 bxeq lr @ nothing to do - jump to real handler 15555 EXPORT_PC() 15556 mov r0, rPC @ arg0 15557 mov r1, rFP @ arg1 15558 mov r2, rSELF @ arg2 15559 b dvmCheckBefore @ (dPC,dFP,self) tail call 15560 15561 /* ------------------------------ */ 15562 .balign 64 15563 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */ 15564 /* File: armv5te/alt_stub.S */ 15565 /* 15566 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15567 * any interesting requests and then jump to the real instruction 15568 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15569 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15570 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15571 * bail to the real handler if breakFlags==0. 15572 */ 15573 ldrb r3, [rSELF, #offThread_breakFlags] 15574 adrl lr, dvmAsmInstructionStart + (48 * 64) 15575 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15576 cmp r3, #0 15577 bxeq lr @ nothing to do - jump to real handler 15578 EXPORT_PC() 15579 mov r0, rPC @ arg0 15580 mov r1, rFP @ arg1 15581 mov r2, rSELF @ arg2 15582 b dvmCheckBefore @ (dPC,dFP,self) tail call 15583 15584 /* ------------------------------ */ 15585 .balign 64 15586 .L_ALT_OP_CMP_LONG: /* 0x31 */ 15587 /* File: armv5te/alt_stub.S */ 15588 /* 15589 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15590 * any interesting requests and then jump to the real instruction 15591 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15592 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15593 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15594 * bail to the real handler if breakFlags==0. 15595 */ 15596 ldrb r3, [rSELF, #offThread_breakFlags] 15597 adrl lr, dvmAsmInstructionStart + (49 * 64) 15598 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15599 cmp r3, #0 15600 bxeq lr @ nothing to do - jump to real handler 15601 EXPORT_PC() 15602 mov r0, rPC @ arg0 15603 mov r1, rFP @ arg1 15604 mov r2, rSELF @ arg2 15605 b dvmCheckBefore @ (dPC,dFP,self) tail call 15606 15607 /* ------------------------------ */ 15608 .balign 64 15609 .L_ALT_OP_IF_EQ: /* 0x32 */ 15610 /* File: armv5te/alt_stub.S */ 15611 /* 15612 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15613 * any interesting requests and then jump to the real instruction 15614 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15615 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15616 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15617 * bail to the real handler if breakFlags==0. 15618 */ 15619 ldrb r3, [rSELF, #offThread_breakFlags] 15620 adrl lr, dvmAsmInstructionStart + (50 * 64) 15621 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15622 cmp r3, #0 15623 bxeq lr @ nothing to do - jump to real handler 15624 EXPORT_PC() 15625 mov r0, rPC @ arg0 15626 mov r1, rFP @ arg1 15627 mov r2, rSELF @ arg2 15628 b dvmCheckBefore @ (dPC,dFP,self) tail call 15629 15630 /* ------------------------------ */ 15631 .balign 64 15632 .L_ALT_OP_IF_NE: /* 0x33 */ 15633 /* File: armv5te/alt_stub.S */ 15634 /* 15635 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15636 * any interesting requests and then jump to the real instruction 15637 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15638 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15639 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15640 * bail to the real handler if breakFlags==0. 15641 */ 15642 ldrb r3, [rSELF, #offThread_breakFlags] 15643 adrl lr, dvmAsmInstructionStart + (51 * 64) 15644 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15645 cmp r3, #0 15646 bxeq lr @ nothing to do - jump to real handler 15647 EXPORT_PC() 15648 mov r0, rPC @ arg0 15649 mov r1, rFP @ arg1 15650 mov r2, rSELF @ arg2 15651 b dvmCheckBefore @ (dPC,dFP,self) tail call 15652 15653 /* ------------------------------ */ 15654 .balign 64 15655 .L_ALT_OP_IF_LT: /* 0x34 */ 15656 /* File: armv5te/alt_stub.S */ 15657 /* 15658 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15659 * any interesting requests and then jump to the real instruction 15660 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15661 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15662 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15663 * bail to the real handler if breakFlags==0. 15664 */ 15665 ldrb r3, [rSELF, #offThread_breakFlags] 15666 adrl lr, dvmAsmInstructionStart + (52 * 64) 15667 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15668 cmp r3, #0 15669 bxeq lr @ nothing to do - jump to real handler 15670 EXPORT_PC() 15671 mov r0, rPC @ arg0 15672 mov r1, rFP @ arg1 15673 mov r2, rSELF @ arg2 15674 b dvmCheckBefore @ (dPC,dFP,self) tail call 15675 15676 /* ------------------------------ */ 15677 .balign 64 15678 .L_ALT_OP_IF_GE: /* 0x35 */ 15679 /* File: armv5te/alt_stub.S */ 15680 /* 15681 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15682 * any interesting requests and then jump to the real instruction 15683 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15684 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15685 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15686 * bail to the real handler if breakFlags==0. 15687 */ 15688 ldrb r3, [rSELF, #offThread_breakFlags] 15689 adrl lr, dvmAsmInstructionStart + (53 * 64) 15690 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15691 cmp r3, #0 15692 bxeq lr @ nothing to do - jump to real handler 15693 EXPORT_PC() 15694 mov r0, rPC @ arg0 15695 mov r1, rFP @ arg1 15696 mov r2, rSELF @ arg2 15697 b dvmCheckBefore @ (dPC,dFP,self) tail call 15698 15699 /* ------------------------------ */ 15700 .balign 64 15701 .L_ALT_OP_IF_GT: /* 0x36 */ 15702 /* File: armv5te/alt_stub.S */ 15703 /* 15704 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15705 * any interesting requests and then jump to the real instruction 15706 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15707 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15708 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15709 * bail to the real handler if breakFlags==0. 15710 */ 15711 ldrb r3, [rSELF, #offThread_breakFlags] 15712 adrl lr, dvmAsmInstructionStart + (54 * 64) 15713 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15714 cmp r3, #0 15715 bxeq lr @ nothing to do - jump to real handler 15716 EXPORT_PC() 15717 mov r0, rPC @ arg0 15718 mov r1, rFP @ arg1 15719 mov r2, rSELF @ arg2 15720 b dvmCheckBefore @ (dPC,dFP,self) tail call 15721 15722 /* ------------------------------ */ 15723 .balign 64 15724 .L_ALT_OP_IF_LE: /* 0x37 */ 15725 /* File: armv5te/alt_stub.S */ 15726 /* 15727 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15728 * any interesting requests and then jump to the real instruction 15729 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15730 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15731 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15732 * bail to the real handler if breakFlags==0. 15733 */ 15734 ldrb r3, [rSELF, #offThread_breakFlags] 15735 adrl lr, dvmAsmInstructionStart + (55 * 64) 15736 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15737 cmp r3, #0 15738 bxeq lr @ nothing to do - jump to real handler 15739 EXPORT_PC() 15740 mov r0, rPC @ arg0 15741 mov r1, rFP @ arg1 15742 mov r2, rSELF @ arg2 15743 b dvmCheckBefore @ (dPC,dFP,self) tail call 15744 15745 /* ------------------------------ */ 15746 .balign 64 15747 .L_ALT_OP_IF_EQZ: /* 0x38 */ 15748 /* File: armv5te/alt_stub.S */ 15749 /* 15750 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15751 * any interesting requests and then jump to the real instruction 15752 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15753 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15754 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15755 * bail to the real handler if breakFlags==0. 15756 */ 15757 ldrb r3, [rSELF, #offThread_breakFlags] 15758 adrl lr, dvmAsmInstructionStart + (56 * 64) 15759 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15760 cmp r3, #0 15761 bxeq lr @ nothing to do - jump to real handler 15762 EXPORT_PC() 15763 mov r0, rPC @ arg0 15764 mov r1, rFP @ arg1 15765 mov r2, rSELF @ arg2 15766 b dvmCheckBefore @ (dPC,dFP,self) tail call 15767 15768 /* ------------------------------ */ 15769 .balign 64 15770 .L_ALT_OP_IF_NEZ: /* 0x39 */ 15771 /* File: armv5te/alt_stub.S */ 15772 /* 15773 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15774 * any interesting requests and then jump to the real instruction 15775 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15776 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15777 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15778 * bail to the real handler if breakFlags==0. 15779 */ 15780 ldrb r3, [rSELF, #offThread_breakFlags] 15781 adrl lr, dvmAsmInstructionStart + (57 * 64) 15782 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15783 cmp r3, #0 15784 bxeq lr @ nothing to do - jump to real handler 15785 EXPORT_PC() 15786 mov r0, rPC @ arg0 15787 mov r1, rFP @ arg1 15788 mov r2, rSELF @ arg2 15789 b dvmCheckBefore @ (dPC,dFP,self) tail call 15790 15791 /* ------------------------------ */ 15792 .balign 64 15793 .L_ALT_OP_IF_LTZ: /* 0x3a */ 15794 /* File: armv5te/alt_stub.S */ 15795 /* 15796 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15797 * any interesting requests and then jump to the real instruction 15798 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15799 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15800 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15801 * bail to the real handler if breakFlags==0. 15802 */ 15803 ldrb r3, [rSELF, #offThread_breakFlags] 15804 adrl lr, dvmAsmInstructionStart + (58 * 64) 15805 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15806 cmp r3, #0 15807 bxeq lr @ nothing to do - jump to real handler 15808 EXPORT_PC() 15809 mov r0, rPC @ arg0 15810 mov r1, rFP @ arg1 15811 mov r2, rSELF @ arg2 15812 b dvmCheckBefore @ (dPC,dFP,self) tail call 15813 15814 /* ------------------------------ */ 15815 .balign 64 15816 .L_ALT_OP_IF_GEZ: /* 0x3b */ 15817 /* File: armv5te/alt_stub.S */ 15818 /* 15819 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15820 * any interesting requests and then jump to the real instruction 15821 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15822 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15823 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15824 * bail to the real handler if breakFlags==0. 15825 */ 15826 ldrb r3, [rSELF, #offThread_breakFlags] 15827 adrl lr, dvmAsmInstructionStart + (59 * 64) 15828 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15829 cmp r3, #0 15830 bxeq lr @ nothing to do - jump to real handler 15831 EXPORT_PC() 15832 mov r0, rPC @ arg0 15833 mov r1, rFP @ arg1 15834 mov r2, rSELF @ arg2 15835 b dvmCheckBefore @ (dPC,dFP,self) tail call 15836 15837 /* ------------------------------ */ 15838 .balign 64 15839 .L_ALT_OP_IF_GTZ: /* 0x3c */ 15840 /* File: armv5te/alt_stub.S */ 15841 /* 15842 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15843 * any interesting requests and then jump to the real instruction 15844 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15845 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15846 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15847 * bail to the real handler if breakFlags==0. 15848 */ 15849 ldrb r3, [rSELF, #offThread_breakFlags] 15850 adrl lr, dvmAsmInstructionStart + (60 * 64) 15851 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15852 cmp r3, #0 15853 bxeq lr @ nothing to do - jump to real handler 15854 EXPORT_PC() 15855 mov r0, rPC @ arg0 15856 mov r1, rFP @ arg1 15857 mov r2, rSELF @ arg2 15858 b dvmCheckBefore @ (dPC,dFP,self) tail call 15859 15860 /* ------------------------------ */ 15861 .balign 64 15862 .L_ALT_OP_IF_LEZ: /* 0x3d */ 15863 /* File: armv5te/alt_stub.S */ 15864 /* 15865 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15866 * any interesting requests and then jump to the real instruction 15867 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15868 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15869 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15870 * bail to the real handler if breakFlags==0. 15871 */ 15872 ldrb r3, [rSELF, #offThread_breakFlags] 15873 adrl lr, dvmAsmInstructionStart + (61 * 64) 15874 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15875 cmp r3, #0 15876 bxeq lr @ nothing to do - jump to real handler 15877 EXPORT_PC() 15878 mov r0, rPC @ arg0 15879 mov r1, rFP @ arg1 15880 mov r2, rSELF @ arg2 15881 b dvmCheckBefore @ (dPC,dFP,self) tail call 15882 15883 /* ------------------------------ */ 15884 .balign 64 15885 .L_ALT_OP_UNUSED_3E: /* 0x3e */ 15886 /* File: armv5te/alt_stub.S */ 15887 /* 15888 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15889 * any interesting requests and then jump to the real instruction 15890 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15891 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15892 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15893 * bail to the real handler if breakFlags==0. 15894 */ 15895 ldrb r3, [rSELF, #offThread_breakFlags] 15896 adrl lr, dvmAsmInstructionStart + (62 * 64) 15897 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15898 cmp r3, #0 15899 bxeq lr @ nothing to do - jump to real handler 15900 EXPORT_PC() 15901 mov r0, rPC @ arg0 15902 mov r1, rFP @ arg1 15903 mov r2, rSELF @ arg2 15904 b dvmCheckBefore @ (dPC,dFP,self) tail call 15905 15906 /* ------------------------------ */ 15907 .balign 64 15908 .L_ALT_OP_UNUSED_3F: /* 0x3f */ 15909 /* File: armv5te/alt_stub.S */ 15910 /* 15911 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15912 * any interesting requests and then jump to the real instruction 15913 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15914 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15915 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15916 * bail to the real handler if breakFlags==0. 15917 */ 15918 ldrb r3, [rSELF, #offThread_breakFlags] 15919 adrl lr, dvmAsmInstructionStart + (63 * 64) 15920 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15921 cmp r3, #0 15922 bxeq lr @ nothing to do - jump to real handler 15923 EXPORT_PC() 15924 mov r0, rPC @ arg0 15925 mov r1, rFP @ arg1 15926 mov r2, rSELF @ arg2 15927 b dvmCheckBefore @ (dPC,dFP,self) tail call 15928 15929 /* ------------------------------ */ 15930 .balign 64 15931 .L_ALT_OP_UNUSED_40: /* 0x40 */ 15932 /* File: armv5te/alt_stub.S */ 15933 /* 15934 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15935 * any interesting requests and then jump to the real instruction 15936 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15937 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15938 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15939 * bail to the real handler if breakFlags==0. 15940 */ 15941 ldrb r3, [rSELF, #offThread_breakFlags] 15942 adrl lr, dvmAsmInstructionStart + (64 * 64) 15943 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15944 cmp r3, #0 15945 bxeq lr @ nothing to do - jump to real handler 15946 EXPORT_PC() 15947 mov r0, rPC @ arg0 15948 mov r1, rFP @ arg1 15949 mov r2, rSELF @ arg2 15950 b dvmCheckBefore @ (dPC,dFP,self) tail call 15951 15952 /* ------------------------------ */ 15953 .balign 64 15954 .L_ALT_OP_UNUSED_41: /* 0x41 */ 15955 /* File: armv5te/alt_stub.S */ 15956 /* 15957 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15958 * any interesting requests and then jump to the real instruction 15959 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15960 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15961 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15962 * bail to the real handler if breakFlags==0. 15963 */ 15964 ldrb r3, [rSELF, #offThread_breakFlags] 15965 adrl lr, dvmAsmInstructionStart + (65 * 64) 15966 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15967 cmp r3, #0 15968 bxeq lr @ nothing to do - jump to real handler 15969 EXPORT_PC() 15970 mov r0, rPC @ arg0 15971 mov r1, rFP @ arg1 15972 mov r2, rSELF @ arg2 15973 b dvmCheckBefore @ (dPC,dFP,self) tail call 15974 15975 /* ------------------------------ */ 15976 .balign 64 15977 .L_ALT_OP_UNUSED_42: /* 0x42 */ 15978 /* File: armv5te/alt_stub.S */ 15979 /* 15980 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 15981 * any interesting requests and then jump to the real instruction 15982 * handler. Note that the call to dvmCheckBefore is done as a tail call. 15983 * rIBASE updates won't be seen until a refresh, and we can tell we have a 15984 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 15985 * bail to the real handler if breakFlags==0. 15986 */ 15987 ldrb r3, [rSELF, #offThread_breakFlags] 15988 adrl lr, dvmAsmInstructionStart + (66 * 64) 15989 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 15990 cmp r3, #0 15991 bxeq lr @ nothing to do - jump to real handler 15992 EXPORT_PC() 15993 mov r0, rPC @ arg0 15994 mov r1, rFP @ arg1 15995 mov r2, rSELF @ arg2 15996 b dvmCheckBefore @ (dPC,dFP,self) tail call 15997 15998 /* ------------------------------ */ 15999 .balign 64 16000 .L_ALT_OP_UNUSED_43: /* 0x43 */ 16001 /* File: armv5te/alt_stub.S */ 16002 /* 16003 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16004 * any interesting requests and then jump to the real instruction 16005 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16006 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16007 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16008 * bail to the real handler if breakFlags==0. 16009 */ 16010 ldrb r3, [rSELF, #offThread_breakFlags] 16011 adrl lr, dvmAsmInstructionStart + (67 * 64) 16012 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16013 cmp r3, #0 16014 bxeq lr @ nothing to do - jump to real handler 16015 EXPORT_PC() 16016 mov r0, rPC @ arg0 16017 mov r1, rFP @ arg1 16018 mov r2, rSELF @ arg2 16019 b dvmCheckBefore @ (dPC,dFP,self) tail call 16020 16021 /* ------------------------------ */ 16022 .balign 64 16023 .L_ALT_OP_AGET: /* 0x44 */ 16024 /* File: armv5te/alt_stub.S */ 16025 /* 16026 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16027 * any interesting requests and then jump to the real instruction 16028 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16029 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16030 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16031 * bail to the real handler if breakFlags==0. 16032 */ 16033 ldrb r3, [rSELF, #offThread_breakFlags] 16034 adrl lr, dvmAsmInstructionStart + (68 * 64) 16035 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16036 cmp r3, #0 16037 bxeq lr @ nothing to do - jump to real handler 16038 EXPORT_PC() 16039 mov r0, rPC @ arg0 16040 mov r1, rFP @ arg1 16041 mov r2, rSELF @ arg2 16042 b dvmCheckBefore @ (dPC,dFP,self) tail call 16043 16044 /* ------------------------------ */ 16045 .balign 64 16046 .L_ALT_OP_AGET_WIDE: /* 0x45 */ 16047 /* File: armv5te/alt_stub.S */ 16048 /* 16049 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16050 * any interesting requests and then jump to the real instruction 16051 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16052 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16053 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16054 * bail to the real handler if breakFlags==0. 16055 */ 16056 ldrb r3, [rSELF, #offThread_breakFlags] 16057 adrl lr, dvmAsmInstructionStart + (69 * 64) 16058 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16059 cmp r3, #0 16060 bxeq lr @ nothing to do - jump to real handler 16061 EXPORT_PC() 16062 mov r0, rPC @ arg0 16063 mov r1, rFP @ arg1 16064 mov r2, rSELF @ arg2 16065 b dvmCheckBefore @ (dPC,dFP,self) tail call 16066 16067 /* ------------------------------ */ 16068 .balign 64 16069 .L_ALT_OP_AGET_OBJECT: /* 0x46 */ 16070 /* File: armv5te/alt_stub.S */ 16071 /* 16072 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16073 * any interesting requests and then jump to the real instruction 16074 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16075 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16076 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16077 * bail to the real handler if breakFlags==0. 16078 */ 16079 ldrb r3, [rSELF, #offThread_breakFlags] 16080 adrl lr, dvmAsmInstructionStart + (70 * 64) 16081 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16082 cmp r3, #0 16083 bxeq lr @ nothing to do - jump to real handler 16084 EXPORT_PC() 16085 mov r0, rPC @ arg0 16086 mov r1, rFP @ arg1 16087 mov r2, rSELF @ arg2 16088 b dvmCheckBefore @ (dPC,dFP,self) tail call 16089 16090 /* ------------------------------ */ 16091 .balign 64 16092 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */ 16093 /* File: armv5te/alt_stub.S */ 16094 /* 16095 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16096 * any interesting requests and then jump to the real instruction 16097 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16098 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16099 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16100 * bail to the real handler if breakFlags==0. 16101 */ 16102 ldrb r3, [rSELF, #offThread_breakFlags] 16103 adrl lr, dvmAsmInstructionStart + (71 * 64) 16104 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16105 cmp r3, #0 16106 bxeq lr @ nothing to do - jump to real handler 16107 EXPORT_PC() 16108 mov r0, rPC @ arg0 16109 mov r1, rFP @ arg1 16110 mov r2, rSELF @ arg2 16111 b dvmCheckBefore @ (dPC,dFP,self) tail call 16112 16113 /* ------------------------------ */ 16114 .balign 64 16115 .L_ALT_OP_AGET_BYTE: /* 0x48 */ 16116 /* File: armv5te/alt_stub.S */ 16117 /* 16118 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16119 * any interesting requests and then jump to the real instruction 16120 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16121 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16122 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16123 * bail to the real handler if breakFlags==0. 16124 */ 16125 ldrb r3, [rSELF, #offThread_breakFlags] 16126 adrl lr, dvmAsmInstructionStart + (72 * 64) 16127 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16128 cmp r3, #0 16129 bxeq lr @ nothing to do - jump to real handler 16130 EXPORT_PC() 16131 mov r0, rPC @ arg0 16132 mov r1, rFP @ arg1 16133 mov r2, rSELF @ arg2 16134 b dvmCheckBefore @ (dPC,dFP,self) tail call 16135 16136 /* ------------------------------ */ 16137 .balign 64 16138 .L_ALT_OP_AGET_CHAR: /* 0x49 */ 16139 /* File: armv5te/alt_stub.S */ 16140 /* 16141 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16142 * any interesting requests and then jump to the real instruction 16143 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16144 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16145 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16146 * bail to the real handler if breakFlags==0. 16147 */ 16148 ldrb r3, [rSELF, #offThread_breakFlags] 16149 adrl lr, dvmAsmInstructionStart + (73 * 64) 16150 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16151 cmp r3, #0 16152 bxeq lr @ nothing to do - jump to real handler 16153 EXPORT_PC() 16154 mov r0, rPC @ arg0 16155 mov r1, rFP @ arg1 16156 mov r2, rSELF @ arg2 16157 b dvmCheckBefore @ (dPC,dFP,self) tail call 16158 16159 /* ------------------------------ */ 16160 .balign 64 16161 .L_ALT_OP_AGET_SHORT: /* 0x4a */ 16162 /* File: armv5te/alt_stub.S */ 16163 /* 16164 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16165 * any interesting requests and then jump to the real instruction 16166 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16167 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16168 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16169 * bail to the real handler if breakFlags==0. 16170 */ 16171 ldrb r3, [rSELF, #offThread_breakFlags] 16172 adrl lr, dvmAsmInstructionStart + (74 * 64) 16173 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16174 cmp r3, #0 16175 bxeq lr @ nothing to do - jump to real handler 16176 EXPORT_PC() 16177 mov r0, rPC @ arg0 16178 mov r1, rFP @ arg1 16179 mov r2, rSELF @ arg2 16180 b dvmCheckBefore @ (dPC,dFP,self) tail call 16181 16182 /* ------------------------------ */ 16183 .balign 64 16184 .L_ALT_OP_APUT: /* 0x4b */ 16185 /* File: armv5te/alt_stub.S */ 16186 /* 16187 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16188 * any interesting requests and then jump to the real instruction 16189 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16190 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16191 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16192 * bail to the real handler if breakFlags==0. 16193 */ 16194 ldrb r3, [rSELF, #offThread_breakFlags] 16195 adrl lr, dvmAsmInstructionStart + (75 * 64) 16196 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16197 cmp r3, #0 16198 bxeq lr @ nothing to do - jump to real handler 16199 EXPORT_PC() 16200 mov r0, rPC @ arg0 16201 mov r1, rFP @ arg1 16202 mov r2, rSELF @ arg2 16203 b dvmCheckBefore @ (dPC,dFP,self) tail call 16204 16205 /* ------------------------------ */ 16206 .balign 64 16207 .L_ALT_OP_APUT_WIDE: /* 0x4c */ 16208 /* File: armv5te/alt_stub.S */ 16209 /* 16210 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16211 * any interesting requests and then jump to the real instruction 16212 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16213 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16214 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16215 * bail to the real handler if breakFlags==0. 16216 */ 16217 ldrb r3, [rSELF, #offThread_breakFlags] 16218 adrl lr, dvmAsmInstructionStart + (76 * 64) 16219 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16220 cmp r3, #0 16221 bxeq lr @ nothing to do - jump to real handler 16222 EXPORT_PC() 16223 mov r0, rPC @ arg0 16224 mov r1, rFP @ arg1 16225 mov r2, rSELF @ arg2 16226 b dvmCheckBefore @ (dPC,dFP,self) tail call 16227 16228 /* ------------------------------ */ 16229 .balign 64 16230 .L_ALT_OP_APUT_OBJECT: /* 0x4d */ 16231 /* File: armv5te/alt_stub.S */ 16232 /* 16233 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16234 * any interesting requests and then jump to the real instruction 16235 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16236 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16237 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16238 * bail to the real handler if breakFlags==0. 16239 */ 16240 ldrb r3, [rSELF, #offThread_breakFlags] 16241 adrl lr, dvmAsmInstructionStart + (77 * 64) 16242 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16243 cmp r3, #0 16244 bxeq lr @ nothing to do - jump to real handler 16245 EXPORT_PC() 16246 mov r0, rPC @ arg0 16247 mov r1, rFP @ arg1 16248 mov r2, rSELF @ arg2 16249 b dvmCheckBefore @ (dPC,dFP,self) tail call 16250 16251 /* ------------------------------ */ 16252 .balign 64 16253 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */ 16254 /* File: armv5te/alt_stub.S */ 16255 /* 16256 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16257 * any interesting requests and then jump to the real instruction 16258 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16259 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16260 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16261 * bail to the real handler if breakFlags==0. 16262 */ 16263 ldrb r3, [rSELF, #offThread_breakFlags] 16264 adrl lr, dvmAsmInstructionStart + (78 * 64) 16265 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16266 cmp r3, #0 16267 bxeq lr @ nothing to do - jump to real handler 16268 EXPORT_PC() 16269 mov r0, rPC @ arg0 16270 mov r1, rFP @ arg1 16271 mov r2, rSELF @ arg2 16272 b dvmCheckBefore @ (dPC,dFP,self) tail call 16273 16274 /* ------------------------------ */ 16275 .balign 64 16276 .L_ALT_OP_APUT_BYTE: /* 0x4f */ 16277 /* File: armv5te/alt_stub.S */ 16278 /* 16279 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16280 * any interesting requests and then jump to the real instruction 16281 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16282 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16283 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16284 * bail to the real handler if breakFlags==0. 16285 */ 16286 ldrb r3, [rSELF, #offThread_breakFlags] 16287 adrl lr, dvmAsmInstructionStart + (79 * 64) 16288 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16289 cmp r3, #0 16290 bxeq lr @ nothing to do - jump to real handler 16291 EXPORT_PC() 16292 mov r0, rPC @ arg0 16293 mov r1, rFP @ arg1 16294 mov r2, rSELF @ arg2 16295 b dvmCheckBefore @ (dPC,dFP,self) tail call 16296 16297 /* ------------------------------ */ 16298 .balign 64 16299 .L_ALT_OP_APUT_CHAR: /* 0x50 */ 16300 /* File: armv5te/alt_stub.S */ 16301 /* 16302 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16303 * any interesting requests and then jump to the real instruction 16304 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16305 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16306 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16307 * bail to the real handler if breakFlags==0. 16308 */ 16309 ldrb r3, [rSELF, #offThread_breakFlags] 16310 adrl lr, dvmAsmInstructionStart + (80 * 64) 16311 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16312 cmp r3, #0 16313 bxeq lr @ nothing to do - jump to real handler 16314 EXPORT_PC() 16315 mov r0, rPC @ arg0 16316 mov r1, rFP @ arg1 16317 mov r2, rSELF @ arg2 16318 b dvmCheckBefore @ (dPC,dFP,self) tail call 16319 16320 /* ------------------------------ */ 16321 .balign 64 16322 .L_ALT_OP_APUT_SHORT: /* 0x51 */ 16323 /* File: armv5te/alt_stub.S */ 16324 /* 16325 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16326 * any interesting requests and then jump to the real instruction 16327 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16328 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16329 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16330 * bail to the real handler if breakFlags==0. 16331 */ 16332 ldrb r3, [rSELF, #offThread_breakFlags] 16333 adrl lr, dvmAsmInstructionStart + (81 * 64) 16334 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16335 cmp r3, #0 16336 bxeq lr @ nothing to do - jump to real handler 16337 EXPORT_PC() 16338 mov r0, rPC @ arg0 16339 mov r1, rFP @ arg1 16340 mov r2, rSELF @ arg2 16341 b dvmCheckBefore @ (dPC,dFP,self) tail call 16342 16343 /* ------------------------------ */ 16344 .balign 64 16345 .L_ALT_OP_IGET: /* 0x52 */ 16346 /* File: armv5te/alt_stub.S */ 16347 /* 16348 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16349 * any interesting requests and then jump to the real instruction 16350 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16351 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16352 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16353 * bail to the real handler if breakFlags==0. 16354 */ 16355 ldrb r3, [rSELF, #offThread_breakFlags] 16356 adrl lr, dvmAsmInstructionStart + (82 * 64) 16357 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16358 cmp r3, #0 16359 bxeq lr @ nothing to do - jump to real handler 16360 EXPORT_PC() 16361 mov r0, rPC @ arg0 16362 mov r1, rFP @ arg1 16363 mov r2, rSELF @ arg2 16364 b dvmCheckBefore @ (dPC,dFP,self) tail call 16365 16366 /* ------------------------------ */ 16367 .balign 64 16368 .L_ALT_OP_IGET_WIDE: /* 0x53 */ 16369 /* File: armv5te/alt_stub.S */ 16370 /* 16371 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16372 * any interesting requests and then jump to the real instruction 16373 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16374 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16375 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16376 * bail to the real handler if breakFlags==0. 16377 */ 16378 ldrb r3, [rSELF, #offThread_breakFlags] 16379 adrl lr, dvmAsmInstructionStart + (83 * 64) 16380 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16381 cmp r3, #0 16382 bxeq lr @ nothing to do - jump to real handler 16383 EXPORT_PC() 16384 mov r0, rPC @ arg0 16385 mov r1, rFP @ arg1 16386 mov r2, rSELF @ arg2 16387 b dvmCheckBefore @ (dPC,dFP,self) tail call 16388 16389 /* ------------------------------ */ 16390 .balign 64 16391 .L_ALT_OP_IGET_OBJECT: /* 0x54 */ 16392 /* File: armv5te/alt_stub.S */ 16393 /* 16394 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16395 * any interesting requests and then jump to the real instruction 16396 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16397 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16398 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16399 * bail to the real handler if breakFlags==0. 16400 */ 16401 ldrb r3, [rSELF, #offThread_breakFlags] 16402 adrl lr, dvmAsmInstructionStart + (84 * 64) 16403 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16404 cmp r3, #0 16405 bxeq lr @ nothing to do - jump to real handler 16406 EXPORT_PC() 16407 mov r0, rPC @ arg0 16408 mov r1, rFP @ arg1 16409 mov r2, rSELF @ arg2 16410 b dvmCheckBefore @ (dPC,dFP,self) tail call 16411 16412 /* ------------------------------ */ 16413 .balign 64 16414 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */ 16415 /* File: armv5te/alt_stub.S */ 16416 /* 16417 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16418 * any interesting requests and then jump to the real instruction 16419 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16420 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16421 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16422 * bail to the real handler if breakFlags==0. 16423 */ 16424 ldrb r3, [rSELF, #offThread_breakFlags] 16425 adrl lr, dvmAsmInstructionStart + (85 * 64) 16426 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16427 cmp r3, #0 16428 bxeq lr @ nothing to do - jump to real handler 16429 EXPORT_PC() 16430 mov r0, rPC @ arg0 16431 mov r1, rFP @ arg1 16432 mov r2, rSELF @ arg2 16433 b dvmCheckBefore @ (dPC,dFP,self) tail call 16434 16435 /* ------------------------------ */ 16436 .balign 64 16437 .L_ALT_OP_IGET_BYTE: /* 0x56 */ 16438 /* File: armv5te/alt_stub.S */ 16439 /* 16440 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16441 * any interesting requests and then jump to the real instruction 16442 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16443 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16444 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16445 * bail to the real handler if breakFlags==0. 16446 */ 16447 ldrb r3, [rSELF, #offThread_breakFlags] 16448 adrl lr, dvmAsmInstructionStart + (86 * 64) 16449 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16450 cmp r3, #0 16451 bxeq lr @ nothing to do - jump to real handler 16452 EXPORT_PC() 16453 mov r0, rPC @ arg0 16454 mov r1, rFP @ arg1 16455 mov r2, rSELF @ arg2 16456 b dvmCheckBefore @ (dPC,dFP,self) tail call 16457 16458 /* ------------------------------ */ 16459 .balign 64 16460 .L_ALT_OP_IGET_CHAR: /* 0x57 */ 16461 /* File: armv5te/alt_stub.S */ 16462 /* 16463 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16464 * any interesting requests and then jump to the real instruction 16465 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16466 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16467 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16468 * bail to the real handler if breakFlags==0. 16469 */ 16470 ldrb r3, [rSELF, #offThread_breakFlags] 16471 adrl lr, dvmAsmInstructionStart + (87 * 64) 16472 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16473 cmp r3, #0 16474 bxeq lr @ nothing to do - jump to real handler 16475 EXPORT_PC() 16476 mov r0, rPC @ arg0 16477 mov r1, rFP @ arg1 16478 mov r2, rSELF @ arg2 16479 b dvmCheckBefore @ (dPC,dFP,self) tail call 16480 16481 /* ------------------------------ */ 16482 .balign 64 16483 .L_ALT_OP_IGET_SHORT: /* 0x58 */ 16484 /* File: armv5te/alt_stub.S */ 16485 /* 16486 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16487 * any interesting requests and then jump to the real instruction 16488 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16489 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16490 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16491 * bail to the real handler if breakFlags==0. 16492 */ 16493 ldrb r3, [rSELF, #offThread_breakFlags] 16494 adrl lr, dvmAsmInstructionStart + (88 * 64) 16495 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16496 cmp r3, #0 16497 bxeq lr @ nothing to do - jump to real handler 16498 EXPORT_PC() 16499 mov r0, rPC @ arg0 16500 mov r1, rFP @ arg1 16501 mov r2, rSELF @ arg2 16502 b dvmCheckBefore @ (dPC,dFP,self) tail call 16503 16504 /* ------------------------------ */ 16505 .balign 64 16506 .L_ALT_OP_IPUT: /* 0x59 */ 16507 /* File: armv5te/alt_stub.S */ 16508 /* 16509 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16510 * any interesting requests and then jump to the real instruction 16511 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16512 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16513 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16514 * bail to the real handler if breakFlags==0. 16515 */ 16516 ldrb r3, [rSELF, #offThread_breakFlags] 16517 adrl lr, dvmAsmInstructionStart + (89 * 64) 16518 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16519 cmp r3, #0 16520 bxeq lr @ nothing to do - jump to real handler 16521 EXPORT_PC() 16522 mov r0, rPC @ arg0 16523 mov r1, rFP @ arg1 16524 mov r2, rSELF @ arg2 16525 b dvmCheckBefore @ (dPC,dFP,self) tail call 16526 16527 /* ------------------------------ */ 16528 .balign 64 16529 .L_ALT_OP_IPUT_WIDE: /* 0x5a */ 16530 /* File: armv5te/alt_stub.S */ 16531 /* 16532 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16533 * any interesting requests and then jump to the real instruction 16534 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16535 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16536 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16537 * bail to the real handler if breakFlags==0. 16538 */ 16539 ldrb r3, [rSELF, #offThread_breakFlags] 16540 adrl lr, dvmAsmInstructionStart + (90 * 64) 16541 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16542 cmp r3, #0 16543 bxeq lr @ nothing to do - jump to real handler 16544 EXPORT_PC() 16545 mov r0, rPC @ arg0 16546 mov r1, rFP @ arg1 16547 mov r2, rSELF @ arg2 16548 b dvmCheckBefore @ (dPC,dFP,self) tail call 16549 16550 /* ------------------------------ */ 16551 .balign 64 16552 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */ 16553 /* File: armv5te/alt_stub.S */ 16554 /* 16555 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16556 * any interesting requests and then jump to the real instruction 16557 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16558 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16559 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16560 * bail to the real handler if breakFlags==0. 16561 */ 16562 ldrb r3, [rSELF, #offThread_breakFlags] 16563 adrl lr, dvmAsmInstructionStart + (91 * 64) 16564 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16565 cmp r3, #0 16566 bxeq lr @ nothing to do - jump to real handler 16567 EXPORT_PC() 16568 mov r0, rPC @ arg0 16569 mov r1, rFP @ arg1 16570 mov r2, rSELF @ arg2 16571 b dvmCheckBefore @ (dPC,dFP,self) tail call 16572 16573 /* ------------------------------ */ 16574 .balign 64 16575 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */ 16576 /* File: armv5te/alt_stub.S */ 16577 /* 16578 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16579 * any interesting requests and then jump to the real instruction 16580 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16581 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16582 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16583 * bail to the real handler if breakFlags==0. 16584 */ 16585 ldrb r3, [rSELF, #offThread_breakFlags] 16586 adrl lr, dvmAsmInstructionStart + (92 * 64) 16587 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16588 cmp r3, #0 16589 bxeq lr @ nothing to do - jump to real handler 16590 EXPORT_PC() 16591 mov r0, rPC @ arg0 16592 mov r1, rFP @ arg1 16593 mov r2, rSELF @ arg2 16594 b dvmCheckBefore @ (dPC,dFP,self) tail call 16595 16596 /* ------------------------------ */ 16597 .balign 64 16598 .L_ALT_OP_IPUT_BYTE: /* 0x5d */ 16599 /* File: armv5te/alt_stub.S */ 16600 /* 16601 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16602 * any interesting requests and then jump to the real instruction 16603 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16604 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16605 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16606 * bail to the real handler if breakFlags==0. 16607 */ 16608 ldrb r3, [rSELF, #offThread_breakFlags] 16609 adrl lr, dvmAsmInstructionStart + (93 * 64) 16610 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16611 cmp r3, #0 16612 bxeq lr @ nothing to do - jump to real handler 16613 EXPORT_PC() 16614 mov r0, rPC @ arg0 16615 mov r1, rFP @ arg1 16616 mov r2, rSELF @ arg2 16617 b dvmCheckBefore @ (dPC,dFP,self) tail call 16618 16619 /* ------------------------------ */ 16620 .balign 64 16621 .L_ALT_OP_IPUT_CHAR: /* 0x5e */ 16622 /* File: armv5te/alt_stub.S */ 16623 /* 16624 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16625 * any interesting requests and then jump to the real instruction 16626 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16627 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16628 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16629 * bail to the real handler if breakFlags==0. 16630 */ 16631 ldrb r3, [rSELF, #offThread_breakFlags] 16632 adrl lr, dvmAsmInstructionStart + (94 * 64) 16633 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16634 cmp r3, #0 16635 bxeq lr @ nothing to do - jump to real handler 16636 EXPORT_PC() 16637 mov r0, rPC @ arg0 16638 mov r1, rFP @ arg1 16639 mov r2, rSELF @ arg2 16640 b dvmCheckBefore @ (dPC,dFP,self) tail call 16641 16642 /* ------------------------------ */ 16643 .balign 64 16644 .L_ALT_OP_IPUT_SHORT: /* 0x5f */ 16645 /* File: armv5te/alt_stub.S */ 16646 /* 16647 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16648 * any interesting requests and then jump to the real instruction 16649 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16650 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16651 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16652 * bail to the real handler if breakFlags==0. 16653 */ 16654 ldrb r3, [rSELF, #offThread_breakFlags] 16655 adrl lr, dvmAsmInstructionStart + (95 * 64) 16656 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16657 cmp r3, #0 16658 bxeq lr @ nothing to do - jump to real handler 16659 EXPORT_PC() 16660 mov r0, rPC @ arg0 16661 mov r1, rFP @ arg1 16662 mov r2, rSELF @ arg2 16663 b dvmCheckBefore @ (dPC,dFP,self) tail call 16664 16665 /* ------------------------------ */ 16666 .balign 64 16667 .L_ALT_OP_SGET: /* 0x60 */ 16668 /* File: armv5te/alt_stub.S */ 16669 /* 16670 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16671 * any interesting requests and then jump to the real instruction 16672 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16673 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16674 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16675 * bail to the real handler if breakFlags==0. 16676 */ 16677 ldrb r3, [rSELF, #offThread_breakFlags] 16678 adrl lr, dvmAsmInstructionStart + (96 * 64) 16679 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16680 cmp r3, #0 16681 bxeq lr @ nothing to do - jump to real handler 16682 EXPORT_PC() 16683 mov r0, rPC @ arg0 16684 mov r1, rFP @ arg1 16685 mov r2, rSELF @ arg2 16686 b dvmCheckBefore @ (dPC,dFP,self) tail call 16687 16688 /* ------------------------------ */ 16689 .balign 64 16690 .L_ALT_OP_SGET_WIDE: /* 0x61 */ 16691 /* File: armv5te/alt_stub.S */ 16692 /* 16693 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16694 * any interesting requests and then jump to the real instruction 16695 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16696 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16697 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16698 * bail to the real handler if breakFlags==0. 16699 */ 16700 ldrb r3, [rSELF, #offThread_breakFlags] 16701 adrl lr, dvmAsmInstructionStart + (97 * 64) 16702 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16703 cmp r3, #0 16704 bxeq lr @ nothing to do - jump to real handler 16705 EXPORT_PC() 16706 mov r0, rPC @ arg0 16707 mov r1, rFP @ arg1 16708 mov r2, rSELF @ arg2 16709 b dvmCheckBefore @ (dPC,dFP,self) tail call 16710 16711 /* ------------------------------ */ 16712 .balign 64 16713 .L_ALT_OP_SGET_OBJECT: /* 0x62 */ 16714 /* File: armv5te/alt_stub.S */ 16715 /* 16716 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16717 * any interesting requests and then jump to the real instruction 16718 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16719 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16720 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16721 * bail to the real handler if breakFlags==0. 16722 */ 16723 ldrb r3, [rSELF, #offThread_breakFlags] 16724 adrl lr, dvmAsmInstructionStart + (98 * 64) 16725 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16726 cmp r3, #0 16727 bxeq lr @ nothing to do - jump to real handler 16728 EXPORT_PC() 16729 mov r0, rPC @ arg0 16730 mov r1, rFP @ arg1 16731 mov r2, rSELF @ arg2 16732 b dvmCheckBefore @ (dPC,dFP,self) tail call 16733 16734 /* ------------------------------ */ 16735 .balign 64 16736 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */ 16737 /* File: armv5te/alt_stub.S */ 16738 /* 16739 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16740 * any interesting requests and then jump to the real instruction 16741 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16742 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16743 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16744 * bail to the real handler if breakFlags==0. 16745 */ 16746 ldrb r3, [rSELF, #offThread_breakFlags] 16747 adrl lr, dvmAsmInstructionStart + (99 * 64) 16748 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16749 cmp r3, #0 16750 bxeq lr @ nothing to do - jump to real handler 16751 EXPORT_PC() 16752 mov r0, rPC @ arg0 16753 mov r1, rFP @ arg1 16754 mov r2, rSELF @ arg2 16755 b dvmCheckBefore @ (dPC,dFP,self) tail call 16756 16757 /* ------------------------------ */ 16758 .balign 64 16759 .L_ALT_OP_SGET_BYTE: /* 0x64 */ 16760 /* File: armv5te/alt_stub.S */ 16761 /* 16762 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16763 * any interesting requests and then jump to the real instruction 16764 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16765 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16766 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16767 * bail to the real handler if breakFlags==0. 16768 */ 16769 ldrb r3, [rSELF, #offThread_breakFlags] 16770 adrl lr, dvmAsmInstructionStart + (100 * 64) 16771 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16772 cmp r3, #0 16773 bxeq lr @ nothing to do - jump to real handler 16774 EXPORT_PC() 16775 mov r0, rPC @ arg0 16776 mov r1, rFP @ arg1 16777 mov r2, rSELF @ arg2 16778 b dvmCheckBefore @ (dPC,dFP,self) tail call 16779 16780 /* ------------------------------ */ 16781 .balign 64 16782 .L_ALT_OP_SGET_CHAR: /* 0x65 */ 16783 /* File: armv5te/alt_stub.S */ 16784 /* 16785 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16786 * any interesting requests and then jump to the real instruction 16787 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16788 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16789 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16790 * bail to the real handler if breakFlags==0. 16791 */ 16792 ldrb r3, [rSELF, #offThread_breakFlags] 16793 adrl lr, dvmAsmInstructionStart + (101 * 64) 16794 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16795 cmp r3, #0 16796 bxeq lr @ nothing to do - jump to real handler 16797 EXPORT_PC() 16798 mov r0, rPC @ arg0 16799 mov r1, rFP @ arg1 16800 mov r2, rSELF @ arg2 16801 b dvmCheckBefore @ (dPC,dFP,self) tail call 16802 16803 /* ------------------------------ */ 16804 .balign 64 16805 .L_ALT_OP_SGET_SHORT: /* 0x66 */ 16806 /* File: armv5te/alt_stub.S */ 16807 /* 16808 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16809 * any interesting requests and then jump to the real instruction 16810 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16811 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16812 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16813 * bail to the real handler if breakFlags==0. 16814 */ 16815 ldrb r3, [rSELF, #offThread_breakFlags] 16816 adrl lr, dvmAsmInstructionStart + (102 * 64) 16817 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16818 cmp r3, #0 16819 bxeq lr @ nothing to do - jump to real handler 16820 EXPORT_PC() 16821 mov r0, rPC @ arg0 16822 mov r1, rFP @ arg1 16823 mov r2, rSELF @ arg2 16824 b dvmCheckBefore @ (dPC,dFP,self) tail call 16825 16826 /* ------------------------------ */ 16827 .balign 64 16828 .L_ALT_OP_SPUT: /* 0x67 */ 16829 /* File: armv5te/alt_stub.S */ 16830 /* 16831 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16832 * any interesting requests and then jump to the real instruction 16833 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16834 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16835 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16836 * bail to the real handler if breakFlags==0. 16837 */ 16838 ldrb r3, [rSELF, #offThread_breakFlags] 16839 adrl lr, dvmAsmInstructionStart + (103 * 64) 16840 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16841 cmp r3, #0 16842 bxeq lr @ nothing to do - jump to real handler 16843 EXPORT_PC() 16844 mov r0, rPC @ arg0 16845 mov r1, rFP @ arg1 16846 mov r2, rSELF @ arg2 16847 b dvmCheckBefore @ (dPC,dFP,self) tail call 16848 16849 /* ------------------------------ */ 16850 .balign 64 16851 .L_ALT_OP_SPUT_WIDE: /* 0x68 */ 16852 /* File: armv5te/alt_stub.S */ 16853 /* 16854 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16855 * any interesting requests and then jump to the real instruction 16856 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16857 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16858 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16859 * bail to the real handler if breakFlags==0. 16860 */ 16861 ldrb r3, [rSELF, #offThread_breakFlags] 16862 adrl lr, dvmAsmInstructionStart + (104 * 64) 16863 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16864 cmp r3, #0 16865 bxeq lr @ nothing to do - jump to real handler 16866 EXPORT_PC() 16867 mov r0, rPC @ arg0 16868 mov r1, rFP @ arg1 16869 mov r2, rSELF @ arg2 16870 b dvmCheckBefore @ (dPC,dFP,self) tail call 16871 16872 /* ------------------------------ */ 16873 .balign 64 16874 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */ 16875 /* File: armv5te/alt_stub.S */ 16876 /* 16877 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16878 * any interesting requests and then jump to the real instruction 16879 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16880 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16881 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16882 * bail to the real handler if breakFlags==0. 16883 */ 16884 ldrb r3, [rSELF, #offThread_breakFlags] 16885 adrl lr, dvmAsmInstructionStart + (105 * 64) 16886 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16887 cmp r3, #0 16888 bxeq lr @ nothing to do - jump to real handler 16889 EXPORT_PC() 16890 mov r0, rPC @ arg0 16891 mov r1, rFP @ arg1 16892 mov r2, rSELF @ arg2 16893 b dvmCheckBefore @ (dPC,dFP,self) tail call 16894 16895 /* ------------------------------ */ 16896 .balign 64 16897 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */ 16898 /* File: armv5te/alt_stub.S */ 16899 /* 16900 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16901 * any interesting requests and then jump to the real instruction 16902 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16903 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16904 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16905 * bail to the real handler if breakFlags==0. 16906 */ 16907 ldrb r3, [rSELF, #offThread_breakFlags] 16908 adrl lr, dvmAsmInstructionStart + (106 * 64) 16909 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16910 cmp r3, #0 16911 bxeq lr @ nothing to do - jump to real handler 16912 EXPORT_PC() 16913 mov r0, rPC @ arg0 16914 mov r1, rFP @ arg1 16915 mov r2, rSELF @ arg2 16916 b dvmCheckBefore @ (dPC,dFP,self) tail call 16917 16918 /* ------------------------------ */ 16919 .balign 64 16920 .L_ALT_OP_SPUT_BYTE: /* 0x6b */ 16921 /* File: armv5te/alt_stub.S */ 16922 /* 16923 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16924 * any interesting requests and then jump to the real instruction 16925 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16926 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16927 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16928 * bail to the real handler if breakFlags==0. 16929 */ 16930 ldrb r3, [rSELF, #offThread_breakFlags] 16931 adrl lr, dvmAsmInstructionStart + (107 * 64) 16932 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16933 cmp r3, #0 16934 bxeq lr @ nothing to do - jump to real handler 16935 EXPORT_PC() 16936 mov r0, rPC @ arg0 16937 mov r1, rFP @ arg1 16938 mov r2, rSELF @ arg2 16939 b dvmCheckBefore @ (dPC,dFP,self) tail call 16940 16941 /* ------------------------------ */ 16942 .balign 64 16943 .L_ALT_OP_SPUT_CHAR: /* 0x6c */ 16944 /* File: armv5te/alt_stub.S */ 16945 /* 16946 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16947 * any interesting requests and then jump to the real instruction 16948 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16949 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16950 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16951 * bail to the real handler if breakFlags==0. 16952 */ 16953 ldrb r3, [rSELF, #offThread_breakFlags] 16954 adrl lr, dvmAsmInstructionStart + (108 * 64) 16955 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16956 cmp r3, #0 16957 bxeq lr @ nothing to do - jump to real handler 16958 EXPORT_PC() 16959 mov r0, rPC @ arg0 16960 mov r1, rFP @ arg1 16961 mov r2, rSELF @ arg2 16962 b dvmCheckBefore @ (dPC,dFP,self) tail call 16963 16964 /* ------------------------------ */ 16965 .balign 64 16966 .L_ALT_OP_SPUT_SHORT: /* 0x6d */ 16967 /* File: armv5te/alt_stub.S */ 16968 /* 16969 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16970 * any interesting requests and then jump to the real instruction 16971 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16972 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16973 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16974 * bail to the real handler if breakFlags==0. 16975 */ 16976 ldrb r3, [rSELF, #offThread_breakFlags] 16977 adrl lr, dvmAsmInstructionStart + (109 * 64) 16978 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 16979 cmp r3, #0 16980 bxeq lr @ nothing to do - jump to real handler 16981 EXPORT_PC() 16982 mov r0, rPC @ arg0 16983 mov r1, rFP @ arg1 16984 mov r2, rSELF @ arg2 16985 b dvmCheckBefore @ (dPC,dFP,self) tail call 16986 16987 /* ------------------------------ */ 16988 .balign 64 16989 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */ 16990 /* File: armv5te/alt_stub.S */ 16991 /* 16992 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 16993 * any interesting requests and then jump to the real instruction 16994 * handler. Note that the call to dvmCheckBefore is done as a tail call. 16995 * rIBASE updates won't be seen until a refresh, and we can tell we have a 16996 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 16997 * bail to the real handler if breakFlags==0. 16998 */ 16999 ldrb r3, [rSELF, #offThread_breakFlags] 17000 adrl lr, dvmAsmInstructionStart + (110 * 64) 17001 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17002 cmp r3, #0 17003 bxeq lr @ nothing to do - jump to real handler 17004 EXPORT_PC() 17005 mov r0, rPC @ arg0 17006 mov r1, rFP @ arg1 17007 mov r2, rSELF @ arg2 17008 b dvmCheckBefore @ (dPC,dFP,self) tail call 17009 17010 /* ------------------------------ */ 17011 .balign 64 17012 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */ 17013 /* File: armv5te/alt_stub.S */ 17014 /* 17015 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17016 * any interesting requests and then jump to the real instruction 17017 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17018 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17019 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17020 * bail to the real handler if breakFlags==0. 17021 */ 17022 ldrb r3, [rSELF, #offThread_breakFlags] 17023 adrl lr, dvmAsmInstructionStart + (111 * 64) 17024 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17025 cmp r3, #0 17026 bxeq lr @ nothing to do - jump to real handler 17027 EXPORT_PC() 17028 mov r0, rPC @ arg0 17029 mov r1, rFP @ arg1 17030 mov r2, rSELF @ arg2 17031 b dvmCheckBefore @ (dPC,dFP,self) tail call 17032 17033 /* ------------------------------ */ 17034 .balign 64 17035 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */ 17036 /* File: armv5te/alt_stub.S */ 17037 /* 17038 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17039 * any interesting requests and then jump to the real instruction 17040 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17041 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17042 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17043 * bail to the real handler if breakFlags==0. 17044 */ 17045 ldrb r3, [rSELF, #offThread_breakFlags] 17046 adrl lr, dvmAsmInstructionStart + (112 * 64) 17047 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17048 cmp r3, #0 17049 bxeq lr @ nothing to do - jump to real handler 17050 EXPORT_PC() 17051 mov r0, rPC @ arg0 17052 mov r1, rFP @ arg1 17053 mov r2, rSELF @ arg2 17054 b dvmCheckBefore @ (dPC,dFP,self) tail call 17055 17056 /* ------------------------------ */ 17057 .balign 64 17058 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */ 17059 /* File: armv5te/alt_stub.S */ 17060 /* 17061 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17062 * any interesting requests and then jump to the real instruction 17063 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17064 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17065 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17066 * bail to the real handler if breakFlags==0. 17067 */ 17068 ldrb r3, [rSELF, #offThread_breakFlags] 17069 adrl lr, dvmAsmInstructionStart + (113 * 64) 17070 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17071 cmp r3, #0 17072 bxeq lr @ nothing to do - jump to real handler 17073 EXPORT_PC() 17074 mov r0, rPC @ arg0 17075 mov r1, rFP @ arg1 17076 mov r2, rSELF @ arg2 17077 b dvmCheckBefore @ (dPC,dFP,self) tail call 17078 17079 /* ------------------------------ */ 17080 .balign 64 17081 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */ 17082 /* File: armv5te/alt_stub.S */ 17083 /* 17084 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17085 * any interesting requests and then jump to the real instruction 17086 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17087 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17088 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17089 * bail to the real handler if breakFlags==0. 17090 */ 17091 ldrb r3, [rSELF, #offThread_breakFlags] 17092 adrl lr, dvmAsmInstructionStart + (114 * 64) 17093 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17094 cmp r3, #0 17095 bxeq lr @ nothing to do - jump to real handler 17096 EXPORT_PC() 17097 mov r0, rPC @ arg0 17098 mov r1, rFP @ arg1 17099 mov r2, rSELF @ arg2 17100 b dvmCheckBefore @ (dPC,dFP,self) tail call 17101 17102 /* ------------------------------ */ 17103 .balign 64 17104 .L_ALT_OP_UNUSED_73: /* 0x73 */ 17105 /* File: armv5te/alt_stub.S */ 17106 /* 17107 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17108 * any interesting requests and then jump to the real instruction 17109 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17110 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17111 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17112 * bail to the real handler if breakFlags==0. 17113 */ 17114 ldrb r3, [rSELF, #offThread_breakFlags] 17115 adrl lr, dvmAsmInstructionStart + (115 * 64) 17116 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17117 cmp r3, #0 17118 bxeq lr @ nothing to do - jump to real handler 17119 EXPORT_PC() 17120 mov r0, rPC @ arg0 17121 mov r1, rFP @ arg1 17122 mov r2, rSELF @ arg2 17123 b dvmCheckBefore @ (dPC,dFP,self) tail call 17124 17125 /* ------------------------------ */ 17126 .balign 64 17127 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 17128 /* File: armv5te/alt_stub.S */ 17129 /* 17130 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17131 * any interesting requests and then jump to the real instruction 17132 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17133 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17134 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17135 * bail to the real handler if breakFlags==0. 17136 */ 17137 ldrb r3, [rSELF, #offThread_breakFlags] 17138 adrl lr, dvmAsmInstructionStart + (116 * 64) 17139 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17140 cmp r3, #0 17141 bxeq lr @ nothing to do - jump to real handler 17142 EXPORT_PC() 17143 mov r0, rPC @ arg0 17144 mov r1, rFP @ arg1 17145 mov r2, rSELF @ arg2 17146 b dvmCheckBefore @ (dPC,dFP,self) tail call 17147 17148 /* ------------------------------ */ 17149 .balign 64 17150 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 17151 /* File: armv5te/alt_stub.S */ 17152 /* 17153 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17154 * any interesting requests and then jump to the real instruction 17155 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17156 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17157 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17158 * bail to the real handler if breakFlags==0. 17159 */ 17160 ldrb r3, [rSELF, #offThread_breakFlags] 17161 adrl lr, dvmAsmInstructionStart + (117 * 64) 17162 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17163 cmp r3, #0 17164 bxeq lr @ nothing to do - jump to real handler 17165 EXPORT_PC() 17166 mov r0, rPC @ arg0 17167 mov r1, rFP @ arg1 17168 mov r2, rSELF @ arg2 17169 b dvmCheckBefore @ (dPC,dFP,self) tail call 17170 17171 /* ------------------------------ */ 17172 .balign 64 17173 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 17174 /* File: armv5te/alt_stub.S */ 17175 /* 17176 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17177 * any interesting requests and then jump to the real instruction 17178 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17179 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17180 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17181 * bail to the real handler if breakFlags==0. 17182 */ 17183 ldrb r3, [rSELF, #offThread_breakFlags] 17184 adrl lr, dvmAsmInstructionStart + (118 * 64) 17185 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17186 cmp r3, #0 17187 bxeq lr @ nothing to do - jump to real handler 17188 EXPORT_PC() 17189 mov r0, rPC @ arg0 17190 mov r1, rFP @ arg1 17191 mov r2, rSELF @ arg2 17192 b dvmCheckBefore @ (dPC,dFP,self) tail call 17193 17194 /* ------------------------------ */ 17195 .balign 64 17196 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 17197 /* File: armv5te/alt_stub.S */ 17198 /* 17199 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17200 * any interesting requests and then jump to the real instruction 17201 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17202 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17203 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17204 * bail to the real handler if breakFlags==0. 17205 */ 17206 ldrb r3, [rSELF, #offThread_breakFlags] 17207 adrl lr, dvmAsmInstructionStart + (119 * 64) 17208 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17209 cmp r3, #0 17210 bxeq lr @ nothing to do - jump to real handler 17211 EXPORT_PC() 17212 mov r0, rPC @ arg0 17213 mov r1, rFP @ arg1 17214 mov r2, rSELF @ arg2 17215 b dvmCheckBefore @ (dPC,dFP,self) tail call 17216 17217 /* ------------------------------ */ 17218 .balign 64 17219 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 17220 /* File: armv5te/alt_stub.S */ 17221 /* 17222 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17223 * any interesting requests and then jump to the real instruction 17224 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17225 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17226 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17227 * bail to the real handler if breakFlags==0. 17228 */ 17229 ldrb r3, [rSELF, #offThread_breakFlags] 17230 adrl lr, dvmAsmInstructionStart + (120 * 64) 17231 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17232 cmp r3, #0 17233 bxeq lr @ nothing to do - jump to real handler 17234 EXPORT_PC() 17235 mov r0, rPC @ arg0 17236 mov r1, rFP @ arg1 17237 mov r2, rSELF @ arg2 17238 b dvmCheckBefore @ (dPC,dFP,self) tail call 17239 17240 /* ------------------------------ */ 17241 .balign 64 17242 .L_ALT_OP_UNUSED_79: /* 0x79 */ 17243 /* File: armv5te/alt_stub.S */ 17244 /* 17245 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17246 * any interesting requests and then jump to the real instruction 17247 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17248 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17249 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17250 * bail to the real handler if breakFlags==0. 17251 */ 17252 ldrb r3, [rSELF, #offThread_breakFlags] 17253 adrl lr, dvmAsmInstructionStart + (121 * 64) 17254 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17255 cmp r3, #0 17256 bxeq lr @ nothing to do - jump to real handler 17257 EXPORT_PC() 17258 mov r0, rPC @ arg0 17259 mov r1, rFP @ arg1 17260 mov r2, rSELF @ arg2 17261 b dvmCheckBefore @ (dPC,dFP,self) tail call 17262 17263 /* ------------------------------ */ 17264 .balign 64 17265 .L_ALT_OP_UNUSED_7A: /* 0x7a */ 17266 /* File: armv5te/alt_stub.S */ 17267 /* 17268 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17269 * any interesting requests and then jump to the real instruction 17270 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17271 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17272 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17273 * bail to the real handler if breakFlags==0. 17274 */ 17275 ldrb r3, [rSELF, #offThread_breakFlags] 17276 adrl lr, dvmAsmInstructionStart + (122 * 64) 17277 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17278 cmp r3, #0 17279 bxeq lr @ nothing to do - jump to real handler 17280 EXPORT_PC() 17281 mov r0, rPC @ arg0 17282 mov r1, rFP @ arg1 17283 mov r2, rSELF @ arg2 17284 b dvmCheckBefore @ (dPC,dFP,self) tail call 17285 17286 /* ------------------------------ */ 17287 .balign 64 17288 .L_ALT_OP_NEG_INT: /* 0x7b */ 17289 /* File: armv5te/alt_stub.S */ 17290 /* 17291 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17292 * any interesting requests and then jump to the real instruction 17293 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17294 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17295 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17296 * bail to the real handler if breakFlags==0. 17297 */ 17298 ldrb r3, [rSELF, #offThread_breakFlags] 17299 adrl lr, dvmAsmInstructionStart + (123 * 64) 17300 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17301 cmp r3, #0 17302 bxeq lr @ nothing to do - jump to real handler 17303 EXPORT_PC() 17304 mov r0, rPC @ arg0 17305 mov r1, rFP @ arg1 17306 mov r2, rSELF @ arg2 17307 b dvmCheckBefore @ (dPC,dFP,self) tail call 17308 17309 /* ------------------------------ */ 17310 .balign 64 17311 .L_ALT_OP_NOT_INT: /* 0x7c */ 17312 /* File: armv5te/alt_stub.S */ 17313 /* 17314 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17315 * any interesting requests and then jump to the real instruction 17316 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17317 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17318 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17319 * bail to the real handler if breakFlags==0. 17320 */ 17321 ldrb r3, [rSELF, #offThread_breakFlags] 17322 adrl lr, dvmAsmInstructionStart + (124 * 64) 17323 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17324 cmp r3, #0 17325 bxeq lr @ nothing to do - jump to real handler 17326 EXPORT_PC() 17327 mov r0, rPC @ arg0 17328 mov r1, rFP @ arg1 17329 mov r2, rSELF @ arg2 17330 b dvmCheckBefore @ (dPC,dFP,self) tail call 17331 17332 /* ------------------------------ */ 17333 .balign 64 17334 .L_ALT_OP_NEG_LONG: /* 0x7d */ 17335 /* File: armv5te/alt_stub.S */ 17336 /* 17337 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17338 * any interesting requests and then jump to the real instruction 17339 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17340 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17341 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17342 * bail to the real handler if breakFlags==0. 17343 */ 17344 ldrb r3, [rSELF, #offThread_breakFlags] 17345 adrl lr, dvmAsmInstructionStart + (125 * 64) 17346 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17347 cmp r3, #0 17348 bxeq lr @ nothing to do - jump to real handler 17349 EXPORT_PC() 17350 mov r0, rPC @ arg0 17351 mov r1, rFP @ arg1 17352 mov r2, rSELF @ arg2 17353 b dvmCheckBefore @ (dPC,dFP,self) tail call 17354 17355 /* ------------------------------ */ 17356 .balign 64 17357 .L_ALT_OP_NOT_LONG: /* 0x7e */ 17358 /* File: armv5te/alt_stub.S */ 17359 /* 17360 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17361 * any interesting requests and then jump to the real instruction 17362 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17363 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17364 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17365 * bail to the real handler if breakFlags==0. 17366 */ 17367 ldrb r3, [rSELF, #offThread_breakFlags] 17368 adrl lr, dvmAsmInstructionStart + (126 * 64) 17369 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17370 cmp r3, #0 17371 bxeq lr @ nothing to do - jump to real handler 17372 EXPORT_PC() 17373 mov r0, rPC @ arg0 17374 mov r1, rFP @ arg1 17375 mov r2, rSELF @ arg2 17376 b dvmCheckBefore @ (dPC,dFP,self) tail call 17377 17378 /* ------------------------------ */ 17379 .balign 64 17380 .L_ALT_OP_NEG_FLOAT: /* 0x7f */ 17381 /* File: armv5te/alt_stub.S */ 17382 /* 17383 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17384 * any interesting requests and then jump to the real instruction 17385 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17386 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17387 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17388 * bail to the real handler if breakFlags==0. 17389 */ 17390 ldrb r3, [rSELF, #offThread_breakFlags] 17391 adrl lr, dvmAsmInstructionStart + (127 * 64) 17392 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17393 cmp r3, #0 17394 bxeq lr @ nothing to do - jump to real handler 17395 EXPORT_PC() 17396 mov r0, rPC @ arg0 17397 mov r1, rFP @ arg1 17398 mov r2, rSELF @ arg2 17399 b dvmCheckBefore @ (dPC,dFP,self) tail call 17400 17401 /* ------------------------------ */ 17402 .balign 64 17403 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */ 17404 /* File: armv5te/alt_stub.S */ 17405 /* 17406 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17407 * any interesting requests and then jump to the real instruction 17408 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17409 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17410 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17411 * bail to the real handler if breakFlags==0. 17412 */ 17413 ldrb r3, [rSELF, #offThread_breakFlags] 17414 adrl lr, dvmAsmInstructionStart + (128 * 64) 17415 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17416 cmp r3, #0 17417 bxeq lr @ nothing to do - jump to real handler 17418 EXPORT_PC() 17419 mov r0, rPC @ arg0 17420 mov r1, rFP @ arg1 17421 mov r2, rSELF @ arg2 17422 b dvmCheckBefore @ (dPC,dFP,self) tail call 17423 17424 /* ------------------------------ */ 17425 .balign 64 17426 .L_ALT_OP_INT_TO_LONG: /* 0x81 */ 17427 /* File: armv5te/alt_stub.S */ 17428 /* 17429 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17430 * any interesting requests and then jump to the real instruction 17431 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17432 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17433 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17434 * bail to the real handler if breakFlags==0. 17435 */ 17436 ldrb r3, [rSELF, #offThread_breakFlags] 17437 adrl lr, dvmAsmInstructionStart + (129 * 64) 17438 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17439 cmp r3, #0 17440 bxeq lr @ nothing to do - jump to real handler 17441 EXPORT_PC() 17442 mov r0, rPC @ arg0 17443 mov r1, rFP @ arg1 17444 mov r2, rSELF @ arg2 17445 b dvmCheckBefore @ (dPC,dFP,self) tail call 17446 17447 /* ------------------------------ */ 17448 .balign 64 17449 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */ 17450 /* File: armv5te/alt_stub.S */ 17451 /* 17452 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17453 * any interesting requests and then jump to the real instruction 17454 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17455 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17456 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17457 * bail to the real handler if breakFlags==0. 17458 */ 17459 ldrb r3, [rSELF, #offThread_breakFlags] 17460 adrl lr, dvmAsmInstructionStart + (130 * 64) 17461 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17462 cmp r3, #0 17463 bxeq lr @ nothing to do - jump to real handler 17464 EXPORT_PC() 17465 mov r0, rPC @ arg0 17466 mov r1, rFP @ arg1 17467 mov r2, rSELF @ arg2 17468 b dvmCheckBefore @ (dPC,dFP,self) tail call 17469 17470 /* ------------------------------ */ 17471 .balign 64 17472 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */ 17473 /* File: armv5te/alt_stub.S */ 17474 /* 17475 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17476 * any interesting requests and then jump to the real instruction 17477 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17478 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17479 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17480 * bail to the real handler if breakFlags==0. 17481 */ 17482 ldrb r3, [rSELF, #offThread_breakFlags] 17483 adrl lr, dvmAsmInstructionStart + (131 * 64) 17484 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17485 cmp r3, #0 17486 bxeq lr @ nothing to do - jump to real handler 17487 EXPORT_PC() 17488 mov r0, rPC @ arg0 17489 mov r1, rFP @ arg1 17490 mov r2, rSELF @ arg2 17491 b dvmCheckBefore @ (dPC,dFP,self) tail call 17492 17493 /* ------------------------------ */ 17494 .balign 64 17495 .L_ALT_OP_LONG_TO_INT: /* 0x84 */ 17496 /* File: armv5te/alt_stub.S */ 17497 /* 17498 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17499 * any interesting requests and then jump to the real instruction 17500 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17501 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17502 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17503 * bail to the real handler if breakFlags==0. 17504 */ 17505 ldrb r3, [rSELF, #offThread_breakFlags] 17506 adrl lr, dvmAsmInstructionStart + (132 * 64) 17507 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17508 cmp r3, #0 17509 bxeq lr @ nothing to do - jump to real handler 17510 EXPORT_PC() 17511 mov r0, rPC @ arg0 17512 mov r1, rFP @ arg1 17513 mov r2, rSELF @ arg2 17514 b dvmCheckBefore @ (dPC,dFP,self) tail call 17515 17516 /* ------------------------------ */ 17517 .balign 64 17518 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */ 17519 /* File: armv5te/alt_stub.S */ 17520 /* 17521 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17522 * any interesting requests and then jump to the real instruction 17523 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17524 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17525 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17526 * bail to the real handler if breakFlags==0. 17527 */ 17528 ldrb r3, [rSELF, #offThread_breakFlags] 17529 adrl lr, dvmAsmInstructionStart + (133 * 64) 17530 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17531 cmp r3, #0 17532 bxeq lr @ nothing to do - jump to real handler 17533 EXPORT_PC() 17534 mov r0, rPC @ arg0 17535 mov r1, rFP @ arg1 17536 mov r2, rSELF @ arg2 17537 b dvmCheckBefore @ (dPC,dFP,self) tail call 17538 17539 /* ------------------------------ */ 17540 .balign 64 17541 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */ 17542 /* File: armv5te/alt_stub.S */ 17543 /* 17544 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17545 * any interesting requests and then jump to the real instruction 17546 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17547 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17548 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17549 * bail to the real handler if breakFlags==0. 17550 */ 17551 ldrb r3, [rSELF, #offThread_breakFlags] 17552 adrl lr, dvmAsmInstructionStart + (134 * 64) 17553 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17554 cmp r3, #0 17555 bxeq lr @ nothing to do - jump to real handler 17556 EXPORT_PC() 17557 mov r0, rPC @ arg0 17558 mov r1, rFP @ arg1 17559 mov r2, rSELF @ arg2 17560 b dvmCheckBefore @ (dPC,dFP,self) tail call 17561 17562 /* ------------------------------ */ 17563 .balign 64 17564 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */ 17565 /* File: armv5te/alt_stub.S */ 17566 /* 17567 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17568 * any interesting requests and then jump to the real instruction 17569 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17570 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17571 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17572 * bail to the real handler if breakFlags==0. 17573 */ 17574 ldrb r3, [rSELF, #offThread_breakFlags] 17575 adrl lr, dvmAsmInstructionStart + (135 * 64) 17576 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17577 cmp r3, #0 17578 bxeq lr @ nothing to do - jump to real handler 17579 EXPORT_PC() 17580 mov r0, rPC @ arg0 17581 mov r1, rFP @ arg1 17582 mov r2, rSELF @ arg2 17583 b dvmCheckBefore @ (dPC,dFP,self) tail call 17584 17585 /* ------------------------------ */ 17586 .balign 64 17587 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */ 17588 /* File: armv5te/alt_stub.S */ 17589 /* 17590 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17591 * any interesting requests and then jump to the real instruction 17592 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17593 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17594 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17595 * bail to the real handler if breakFlags==0. 17596 */ 17597 ldrb r3, [rSELF, #offThread_breakFlags] 17598 adrl lr, dvmAsmInstructionStart + (136 * 64) 17599 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17600 cmp r3, #0 17601 bxeq lr @ nothing to do - jump to real handler 17602 EXPORT_PC() 17603 mov r0, rPC @ arg0 17604 mov r1, rFP @ arg1 17605 mov r2, rSELF @ arg2 17606 b dvmCheckBefore @ (dPC,dFP,self) tail call 17607 17608 /* ------------------------------ */ 17609 .balign 64 17610 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 17611 /* File: armv5te/alt_stub.S */ 17612 /* 17613 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17614 * any interesting requests and then jump to the real instruction 17615 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17616 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17617 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17618 * bail to the real handler if breakFlags==0. 17619 */ 17620 ldrb r3, [rSELF, #offThread_breakFlags] 17621 adrl lr, dvmAsmInstructionStart + (137 * 64) 17622 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17623 cmp r3, #0 17624 bxeq lr @ nothing to do - jump to real handler 17625 EXPORT_PC() 17626 mov r0, rPC @ arg0 17627 mov r1, rFP @ arg1 17628 mov r2, rSELF @ arg2 17629 b dvmCheckBefore @ (dPC,dFP,self) tail call 17630 17631 /* ------------------------------ */ 17632 .balign 64 17633 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */ 17634 /* File: armv5te/alt_stub.S */ 17635 /* 17636 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17637 * any interesting requests and then jump to the real instruction 17638 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17639 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17640 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17641 * bail to the real handler if breakFlags==0. 17642 */ 17643 ldrb r3, [rSELF, #offThread_breakFlags] 17644 adrl lr, dvmAsmInstructionStart + (138 * 64) 17645 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17646 cmp r3, #0 17647 bxeq lr @ nothing to do - jump to real handler 17648 EXPORT_PC() 17649 mov r0, rPC @ arg0 17650 mov r1, rFP @ arg1 17651 mov r2, rSELF @ arg2 17652 b dvmCheckBefore @ (dPC,dFP,self) tail call 17653 17654 /* ------------------------------ */ 17655 .balign 64 17656 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */ 17657 /* File: armv5te/alt_stub.S */ 17658 /* 17659 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17660 * any interesting requests and then jump to the real instruction 17661 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17662 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17663 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17664 * bail to the real handler if breakFlags==0. 17665 */ 17666 ldrb r3, [rSELF, #offThread_breakFlags] 17667 adrl lr, dvmAsmInstructionStart + (139 * 64) 17668 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17669 cmp r3, #0 17670 bxeq lr @ nothing to do - jump to real handler 17671 EXPORT_PC() 17672 mov r0, rPC @ arg0 17673 mov r1, rFP @ arg1 17674 mov r2, rSELF @ arg2 17675 b dvmCheckBefore @ (dPC,dFP,self) tail call 17676 17677 /* ------------------------------ */ 17678 .balign 64 17679 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 17680 /* File: armv5te/alt_stub.S */ 17681 /* 17682 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17683 * any interesting requests and then jump to the real instruction 17684 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17685 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17686 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17687 * bail to the real handler if breakFlags==0. 17688 */ 17689 ldrb r3, [rSELF, #offThread_breakFlags] 17690 adrl lr, dvmAsmInstructionStart + (140 * 64) 17691 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17692 cmp r3, #0 17693 bxeq lr @ nothing to do - jump to real handler 17694 EXPORT_PC() 17695 mov r0, rPC @ arg0 17696 mov r1, rFP @ arg1 17697 mov r2, rSELF @ arg2 17698 b dvmCheckBefore @ (dPC,dFP,self) tail call 17699 17700 /* ------------------------------ */ 17701 .balign 64 17702 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */ 17703 /* File: armv5te/alt_stub.S */ 17704 /* 17705 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17706 * any interesting requests and then jump to the real instruction 17707 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17708 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17709 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17710 * bail to the real handler if breakFlags==0. 17711 */ 17712 ldrb r3, [rSELF, #offThread_breakFlags] 17713 adrl lr, dvmAsmInstructionStart + (141 * 64) 17714 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17715 cmp r3, #0 17716 bxeq lr @ nothing to do - jump to real handler 17717 EXPORT_PC() 17718 mov r0, rPC @ arg0 17719 mov r1, rFP @ arg1 17720 mov r2, rSELF @ arg2 17721 b dvmCheckBefore @ (dPC,dFP,self) tail call 17722 17723 /* ------------------------------ */ 17724 .balign 64 17725 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */ 17726 /* File: armv5te/alt_stub.S */ 17727 /* 17728 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17729 * any interesting requests and then jump to the real instruction 17730 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17731 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17732 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17733 * bail to the real handler if breakFlags==0. 17734 */ 17735 ldrb r3, [rSELF, #offThread_breakFlags] 17736 adrl lr, dvmAsmInstructionStart + (142 * 64) 17737 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17738 cmp r3, #0 17739 bxeq lr @ nothing to do - jump to real handler 17740 EXPORT_PC() 17741 mov r0, rPC @ arg0 17742 mov r1, rFP @ arg1 17743 mov r2, rSELF @ arg2 17744 b dvmCheckBefore @ (dPC,dFP,self) tail call 17745 17746 /* ------------------------------ */ 17747 .balign 64 17748 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */ 17749 /* File: armv5te/alt_stub.S */ 17750 /* 17751 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17752 * any interesting requests and then jump to the real instruction 17753 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17754 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17755 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17756 * bail to the real handler if breakFlags==0. 17757 */ 17758 ldrb r3, [rSELF, #offThread_breakFlags] 17759 adrl lr, dvmAsmInstructionStart + (143 * 64) 17760 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17761 cmp r3, #0 17762 bxeq lr @ nothing to do - jump to real handler 17763 EXPORT_PC() 17764 mov r0, rPC @ arg0 17765 mov r1, rFP @ arg1 17766 mov r2, rSELF @ arg2 17767 b dvmCheckBefore @ (dPC,dFP,self) tail call 17768 17769 /* ------------------------------ */ 17770 .balign 64 17771 .L_ALT_OP_ADD_INT: /* 0x90 */ 17772 /* File: armv5te/alt_stub.S */ 17773 /* 17774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17775 * any interesting requests and then jump to the real instruction 17776 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17777 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17779 * bail to the real handler if breakFlags==0. 17780 */ 17781 ldrb r3, [rSELF, #offThread_breakFlags] 17782 adrl lr, dvmAsmInstructionStart + (144 * 64) 17783 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17784 cmp r3, #0 17785 bxeq lr @ nothing to do - jump to real handler 17786 EXPORT_PC() 17787 mov r0, rPC @ arg0 17788 mov r1, rFP @ arg1 17789 mov r2, rSELF @ arg2 17790 b dvmCheckBefore @ (dPC,dFP,self) tail call 17791 17792 /* ------------------------------ */ 17793 .balign 64 17794 .L_ALT_OP_SUB_INT: /* 0x91 */ 17795 /* File: armv5te/alt_stub.S */ 17796 /* 17797 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17798 * any interesting requests and then jump to the real instruction 17799 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17800 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17801 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17802 * bail to the real handler if breakFlags==0. 17803 */ 17804 ldrb r3, [rSELF, #offThread_breakFlags] 17805 adrl lr, dvmAsmInstructionStart + (145 * 64) 17806 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17807 cmp r3, #0 17808 bxeq lr @ nothing to do - jump to real handler 17809 EXPORT_PC() 17810 mov r0, rPC @ arg0 17811 mov r1, rFP @ arg1 17812 mov r2, rSELF @ arg2 17813 b dvmCheckBefore @ (dPC,dFP,self) tail call 17814 17815 /* ------------------------------ */ 17816 .balign 64 17817 .L_ALT_OP_MUL_INT: /* 0x92 */ 17818 /* File: armv5te/alt_stub.S */ 17819 /* 17820 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17821 * any interesting requests and then jump to the real instruction 17822 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17823 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17824 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17825 * bail to the real handler if breakFlags==0. 17826 */ 17827 ldrb r3, [rSELF, #offThread_breakFlags] 17828 adrl lr, dvmAsmInstructionStart + (146 * 64) 17829 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17830 cmp r3, #0 17831 bxeq lr @ nothing to do - jump to real handler 17832 EXPORT_PC() 17833 mov r0, rPC @ arg0 17834 mov r1, rFP @ arg1 17835 mov r2, rSELF @ arg2 17836 b dvmCheckBefore @ (dPC,dFP,self) tail call 17837 17838 /* ------------------------------ */ 17839 .balign 64 17840 .L_ALT_OP_DIV_INT: /* 0x93 */ 17841 /* File: armv5te/alt_stub.S */ 17842 /* 17843 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17844 * any interesting requests and then jump to the real instruction 17845 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17846 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17847 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17848 * bail to the real handler if breakFlags==0. 17849 */ 17850 ldrb r3, [rSELF, #offThread_breakFlags] 17851 adrl lr, dvmAsmInstructionStart + (147 * 64) 17852 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17853 cmp r3, #0 17854 bxeq lr @ nothing to do - jump to real handler 17855 EXPORT_PC() 17856 mov r0, rPC @ arg0 17857 mov r1, rFP @ arg1 17858 mov r2, rSELF @ arg2 17859 b dvmCheckBefore @ (dPC,dFP,self) tail call 17860 17861 /* ------------------------------ */ 17862 .balign 64 17863 .L_ALT_OP_REM_INT: /* 0x94 */ 17864 /* File: armv5te/alt_stub.S */ 17865 /* 17866 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17867 * any interesting requests and then jump to the real instruction 17868 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17869 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17870 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17871 * bail to the real handler if breakFlags==0. 17872 */ 17873 ldrb r3, [rSELF, #offThread_breakFlags] 17874 adrl lr, dvmAsmInstructionStart + (148 * 64) 17875 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17876 cmp r3, #0 17877 bxeq lr @ nothing to do - jump to real handler 17878 EXPORT_PC() 17879 mov r0, rPC @ arg0 17880 mov r1, rFP @ arg1 17881 mov r2, rSELF @ arg2 17882 b dvmCheckBefore @ (dPC,dFP,self) tail call 17883 17884 /* ------------------------------ */ 17885 .balign 64 17886 .L_ALT_OP_AND_INT: /* 0x95 */ 17887 /* File: armv5te/alt_stub.S */ 17888 /* 17889 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17890 * any interesting requests and then jump to the real instruction 17891 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17892 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17893 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17894 * bail to the real handler if breakFlags==0. 17895 */ 17896 ldrb r3, [rSELF, #offThread_breakFlags] 17897 adrl lr, dvmAsmInstructionStart + (149 * 64) 17898 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17899 cmp r3, #0 17900 bxeq lr @ nothing to do - jump to real handler 17901 EXPORT_PC() 17902 mov r0, rPC @ arg0 17903 mov r1, rFP @ arg1 17904 mov r2, rSELF @ arg2 17905 b dvmCheckBefore @ (dPC,dFP,self) tail call 17906 17907 /* ------------------------------ */ 17908 .balign 64 17909 .L_ALT_OP_OR_INT: /* 0x96 */ 17910 /* File: armv5te/alt_stub.S */ 17911 /* 17912 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17913 * any interesting requests and then jump to the real instruction 17914 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17915 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17916 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17917 * bail to the real handler if breakFlags==0. 17918 */ 17919 ldrb r3, [rSELF, #offThread_breakFlags] 17920 adrl lr, dvmAsmInstructionStart + (150 * 64) 17921 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17922 cmp r3, #0 17923 bxeq lr @ nothing to do - jump to real handler 17924 EXPORT_PC() 17925 mov r0, rPC @ arg0 17926 mov r1, rFP @ arg1 17927 mov r2, rSELF @ arg2 17928 b dvmCheckBefore @ (dPC,dFP,self) tail call 17929 17930 /* ------------------------------ */ 17931 .balign 64 17932 .L_ALT_OP_XOR_INT: /* 0x97 */ 17933 /* File: armv5te/alt_stub.S */ 17934 /* 17935 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17936 * any interesting requests and then jump to the real instruction 17937 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17938 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17939 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17940 * bail to the real handler if breakFlags==0. 17941 */ 17942 ldrb r3, [rSELF, #offThread_breakFlags] 17943 adrl lr, dvmAsmInstructionStart + (151 * 64) 17944 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17945 cmp r3, #0 17946 bxeq lr @ nothing to do - jump to real handler 17947 EXPORT_PC() 17948 mov r0, rPC @ arg0 17949 mov r1, rFP @ arg1 17950 mov r2, rSELF @ arg2 17951 b dvmCheckBefore @ (dPC,dFP,self) tail call 17952 17953 /* ------------------------------ */ 17954 .balign 64 17955 .L_ALT_OP_SHL_INT: /* 0x98 */ 17956 /* File: armv5te/alt_stub.S */ 17957 /* 17958 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17959 * any interesting requests and then jump to the real instruction 17960 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17961 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17962 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17963 * bail to the real handler if breakFlags==0. 17964 */ 17965 ldrb r3, [rSELF, #offThread_breakFlags] 17966 adrl lr, dvmAsmInstructionStart + (152 * 64) 17967 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17968 cmp r3, #0 17969 bxeq lr @ nothing to do - jump to real handler 17970 EXPORT_PC() 17971 mov r0, rPC @ arg0 17972 mov r1, rFP @ arg1 17973 mov r2, rSELF @ arg2 17974 b dvmCheckBefore @ (dPC,dFP,self) tail call 17975 17976 /* ------------------------------ */ 17977 .balign 64 17978 .L_ALT_OP_SHR_INT: /* 0x99 */ 17979 /* File: armv5te/alt_stub.S */ 17980 /* 17981 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 17982 * any interesting requests and then jump to the real instruction 17983 * handler. Note that the call to dvmCheckBefore is done as a tail call. 17984 * rIBASE updates won't be seen until a refresh, and we can tell we have a 17985 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 17986 * bail to the real handler if breakFlags==0. 17987 */ 17988 ldrb r3, [rSELF, #offThread_breakFlags] 17989 adrl lr, dvmAsmInstructionStart + (153 * 64) 17990 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 17991 cmp r3, #0 17992 bxeq lr @ nothing to do - jump to real handler 17993 EXPORT_PC() 17994 mov r0, rPC @ arg0 17995 mov r1, rFP @ arg1 17996 mov r2, rSELF @ arg2 17997 b dvmCheckBefore @ (dPC,dFP,self) tail call 17998 17999 /* ------------------------------ */ 18000 .balign 64 18001 .L_ALT_OP_USHR_INT: /* 0x9a */ 18002 /* File: armv5te/alt_stub.S */ 18003 /* 18004 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18005 * any interesting requests and then jump to the real instruction 18006 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18007 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18008 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18009 * bail to the real handler if breakFlags==0. 18010 */ 18011 ldrb r3, [rSELF, #offThread_breakFlags] 18012 adrl lr, dvmAsmInstructionStart + (154 * 64) 18013 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18014 cmp r3, #0 18015 bxeq lr @ nothing to do - jump to real handler 18016 EXPORT_PC() 18017 mov r0, rPC @ arg0 18018 mov r1, rFP @ arg1 18019 mov r2, rSELF @ arg2 18020 b dvmCheckBefore @ (dPC,dFP,self) tail call 18021 18022 /* ------------------------------ */ 18023 .balign 64 18024 .L_ALT_OP_ADD_LONG: /* 0x9b */ 18025 /* File: armv5te/alt_stub.S */ 18026 /* 18027 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18028 * any interesting requests and then jump to the real instruction 18029 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18030 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18031 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18032 * bail to the real handler if breakFlags==0. 18033 */ 18034 ldrb r3, [rSELF, #offThread_breakFlags] 18035 adrl lr, dvmAsmInstructionStart + (155 * 64) 18036 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18037 cmp r3, #0 18038 bxeq lr @ nothing to do - jump to real handler 18039 EXPORT_PC() 18040 mov r0, rPC @ arg0 18041 mov r1, rFP @ arg1 18042 mov r2, rSELF @ arg2 18043 b dvmCheckBefore @ (dPC,dFP,self) tail call 18044 18045 /* ------------------------------ */ 18046 .balign 64 18047 .L_ALT_OP_SUB_LONG: /* 0x9c */ 18048 /* File: armv5te/alt_stub.S */ 18049 /* 18050 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18051 * any interesting requests and then jump to the real instruction 18052 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18053 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18054 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18055 * bail to the real handler if breakFlags==0. 18056 */ 18057 ldrb r3, [rSELF, #offThread_breakFlags] 18058 adrl lr, dvmAsmInstructionStart + (156 * 64) 18059 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18060 cmp r3, #0 18061 bxeq lr @ nothing to do - jump to real handler 18062 EXPORT_PC() 18063 mov r0, rPC @ arg0 18064 mov r1, rFP @ arg1 18065 mov r2, rSELF @ arg2 18066 b dvmCheckBefore @ (dPC,dFP,self) tail call 18067 18068 /* ------------------------------ */ 18069 .balign 64 18070 .L_ALT_OP_MUL_LONG: /* 0x9d */ 18071 /* File: armv5te/alt_stub.S */ 18072 /* 18073 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18074 * any interesting requests and then jump to the real instruction 18075 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18076 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18077 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18078 * bail to the real handler if breakFlags==0. 18079 */ 18080 ldrb r3, [rSELF, #offThread_breakFlags] 18081 adrl lr, dvmAsmInstructionStart + (157 * 64) 18082 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18083 cmp r3, #0 18084 bxeq lr @ nothing to do - jump to real handler 18085 EXPORT_PC() 18086 mov r0, rPC @ arg0 18087 mov r1, rFP @ arg1 18088 mov r2, rSELF @ arg2 18089 b dvmCheckBefore @ (dPC,dFP,self) tail call 18090 18091 /* ------------------------------ */ 18092 .balign 64 18093 .L_ALT_OP_DIV_LONG: /* 0x9e */ 18094 /* File: armv5te/alt_stub.S */ 18095 /* 18096 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18097 * any interesting requests and then jump to the real instruction 18098 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18099 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18100 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18101 * bail to the real handler if breakFlags==0. 18102 */ 18103 ldrb r3, [rSELF, #offThread_breakFlags] 18104 adrl lr, dvmAsmInstructionStart + (158 * 64) 18105 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18106 cmp r3, #0 18107 bxeq lr @ nothing to do - jump to real handler 18108 EXPORT_PC() 18109 mov r0, rPC @ arg0 18110 mov r1, rFP @ arg1 18111 mov r2, rSELF @ arg2 18112 b dvmCheckBefore @ (dPC,dFP,self) tail call 18113 18114 /* ------------------------------ */ 18115 .balign 64 18116 .L_ALT_OP_REM_LONG: /* 0x9f */ 18117 /* File: armv5te/alt_stub.S */ 18118 /* 18119 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18120 * any interesting requests and then jump to the real instruction 18121 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18122 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18123 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18124 * bail to the real handler if breakFlags==0. 18125 */ 18126 ldrb r3, [rSELF, #offThread_breakFlags] 18127 adrl lr, dvmAsmInstructionStart + (159 * 64) 18128 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18129 cmp r3, #0 18130 bxeq lr @ nothing to do - jump to real handler 18131 EXPORT_PC() 18132 mov r0, rPC @ arg0 18133 mov r1, rFP @ arg1 18134 mov r2, rSELF @ arg2 18135 b dvmCheckBefore @ (dPC,dFP,self) tail call 18136 18137 /* ------------------------------ */ 18138 .balign 64 18139 .L_ALT_OP_AND_LONG: /* 0xa0 */ 18140 /* File: armv5te/alt_stub.S */ 18141 /* 18142 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18143 * any interesting requests and then jump to the real instruction 18144 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18145 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18146 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18147 * bail to the real handler if breakFlags==0. 18148 */ 18149 ldrb r3, [rSELF, #offThread_breakFlags] 18150 adrl lr, dvmAsmInstructionStart + (160 * 64) 18151 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18152 cmp r3, #0 18153 bxeq lr @ nothing to do - jump to real handler 18154 EXPORT_PC() 18155 mov r0, rPC @ arg0 18156 mov r1, rFP @ arg1 18157 mov r2, rSELF @ arg2 18158 b dvmCheckBefore @ (dPC,dFP,self) tail call 18159 18160 /* ------------------------------ */ 18161 .balign 64 18162 .L_ALT_OP_OR_LONG: /* 0xa1 */ 18163 /* File: armv5te/alt_stub.S */ 18164 /* 18165 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18166 * any interesting requests and then jump to the real instruction 18167 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18168 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18169 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18170 * bail to the real handler if breakFlags==0. 18171 */ 18172 ldrb r3, [rSELF, #offThread_breakFlags] 18173 adrl lr, dvmAsmInstructionStart + (161 * 64) 18174 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18175 cmp r3, #0 18176 bxeq lr @ nothing to do - jump to real handler 18177 EXPORT_PC() 18178 mov r0, rPC @ arg0 18179 mov r1, rFP @ arg1 18180 mov r2, rSELF @ arg2 18181 b dvmCheckBefore @ (dPC,dFP,self) tail call 18182 18183 /* ------------------------------ */ 18184 .balign 64 18185 .L_ALT_OP_XOR_LONG: /* 0xa2 */ 18186 /* File: armv5te/alt_stub.S */ 18187 /* 18188 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18189 * any interesting requests and then jump to the real instruction 18190 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18191 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18192 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18193 * bail to the real handler if breakFlags==0. 18194 */ 18195 ldrb r3, [rSELF, #offThread_breakFlags] 18196 adrl lr, dvmAsmInstructionStart + (162 * 64) 18197 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18198 cmp r3, #0 18199 bxeq lr @ nothing to do - jump to real handler 18200 EXPORT_PC() 18201 mov r0, rPC @ arg0 18202 mov r1, rFP @ arg1 18203 mov r2, rSELF @ arg2 18204 b dvmCheckBefore @ (dPC,dFP,self) tail call 18205 18206 /* ------------------------------ */ 18207 .balign 64 18208 .L_ALT_OP_SHL_LONG: /* 0xa3 */ 18209 /* File: armv5te/alt_stub.S */ 18210 /* 18211 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18212 * any interesting requests and then jump to the real instruction 18213 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18214 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18215 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18216 * bail to the real handler if breakFlags==0. 18217 */ 18218 ldrb r3, [rSELF, #offThread_breakFlags] 18219 adrl lr, dvmAsmInstructionStart + (163 * 64) 18220 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18221 cmp r3, #0 18222 bxeq lr @ nothing to do - jump to real handler 18223 EXPORT_PC() 18224 mov r0, rPC @ arg0 18225 mov r1, rFP @ arg1 18226 mov r2, rSELF @ arg2 18227 b dvmCheckBefore @ (dPC,dFP,self) tail call 18228 18229 /* ------------------------------ */ 18230 .balign 64 18231 .L_ALT_OP_SHR_LONG: /* 0xa4 */ 18232 /* File: armv5te/alt_stub.S */ 18233 /* 18234 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18235 * any interesting requests and then jump to the real instruction 18236 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18237 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18238 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18239 * bail to the real handler if breakFlags==0. 18240 */ 18241 ldrb r3, [rSELF, #offThread_breakFlags] 18242 adrl lr, dvmAsmInstructionStart + (164 * 64) 18243 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18244 cmp r3, #0 18245 bxeq lr @ nothing to do - jump to real handler 18246 EXPORT_PC() 18247 mov r0, rPC @ arg0 18248 mov r1, rFP @ arg1 18249 mov r2, rSELF @ arg2 18250 b dvmCheckBefore @ (dPC,dFP,self) tail call 18251 18252 /* ------------------------------ */ 18253 .balign 64 18254 .L_ALT_OP_USHR_LONG: /* 0xa5 */ 18255 /* File: armv5te/alt_stub.S */ 18256 /* 18257 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18258 * any interesting requests and then jump to the real instruction 18259 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18260 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18261 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18262 * bail to the real handler if breakFlags==0. 18263 */ 18264 ldrb r3, [rSELF, #offThread_breakFlags] 18265 adrl lr, dvmAsmInstructionStart + (165 * 64) 18266 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18267 cmp r3, #0 18268 bxeq lr @ nothing to do - jump to real handler 18269 EXPORT_PC() 18270 mov r0, rPC @ arg0 18271 mov r1, rFP @ arg1 18272 mov r2, rSELF @ arg2 18273 b dvmCheckBefore @ (dPC,dFP,self) tail call 18274 18275 /* ------------------------------ */ 18276 .balign 64 18277 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */ 18278 /* File: armv5te/alt_stub.S */ 18279 /* 18280 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18281 * any interesting requests and then jump to the real instruction 18282 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18283 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18284 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18285 * bail to the real handler if breakFlags==0. 18286 */ 18287 ldrb r3, [rSELF, #offThread_breakFlags] 18288 adrl lr, dvmAsmInstructionStart + (166 * 64) 18289 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18290 cmp r3, #0 18291 bxeq lr @ nothing to do - jump to real handler 18292 EXPORT_PC() 18293 mov r0, rPC @ arg0 18294 mov r1, rFP @ arg1 18295 mov r2, rSELF @ arg2 18296 b dvmCheckBefore @ (dPC,dFP,self) tail call 18297 18298 /* ------------------------------ */ 18299 .balign 64 18300 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */ 18301 /* File: armv5te/alt_stub.S */ 18302 /* 18303 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18304 * any interesting requests and then jump to the real instruction 18305 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18306 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18307 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18308 * bail to the real handler if breakFlags==0. 18309 */ 18310 ldrb r3, [rSELF, #offThread_breakFlags] 18311 adrl lr, dvmAsmInstructionStart + (167 * 64) 18312 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18313 cmp r3, #0 18314 bxeq lr @ nothing to do - jump to real handler 18315 EXPORT_PC() 18316 mov r0, rPC @ arg0 18317 mov r1, rFP @ arg1 18318 mov r2, rSELF @ arg2 18319 b dvmCheckBefore @ (dPC,dFP,self) tail call 18320 18321 /* ------------------------------ */ 18322 .balign 64 18323 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */ 18324 /* File: armv5te/alt_stub.S */ 18325 /* 18326 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18327 * any interesting requests and then jump to the real instruction 18328 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18329 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18330 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18331 * bail to the real handler if breakFlags==0. 18332 */ 18333 ldrb r3, [rSELF, #offThread_breakFlags] 18334 adrl lr, dvmAsmInstructionStart + (168 * 64) 18335 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18336 cmp r3, #0 18337 bxeq lr @ nothing to do - jump to real handler 18338 EXPORT_PC() 18339 mov r0, rPC @ arg0 18340 mov r1, rFP @ arg1 18341 mov r2, rSELF @ arg2 18342 b dvmCheckBefore @ (dPC,dFP,self) tail call 18343 18344 /* ------------------------------ */ 18345 .balign 64 18346 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */ 18347 /* File: armv5te/alt_stub.S */ 18348 /* 18349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18350 * any interesting requests and then jump to the real instruction 18351 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18352 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18354 * bail to the real handler if breakFlags==0. 18355 */ 18356 ldrb r3, [rSELF, #offThread_breakFlags] 18357 adrl lr, dvmAsmInstructionStart + (169 * 64) 18358 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18359 cmp r3, #0 18360 bxeq lr @ nothing to do - jump to real handler 18361 EXPORT_PC() 18362 mov r0, rPC @ arg0 18363 mov r1, rFP @ arg1 18364 mov r2, rSELF @ arg2 18365 b dvmCheckBefore @ (dPC,dFP,self) tail call 18366 18367 /* ------------------------------ */ 18368 .balign 64 18369 .L_ALT_OP_REM_FLOAT: /* 0xaa */ 18370 /* File: armv5te/alt_stub.S */ 18371 /* 18372 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18373 * any interesting requests and then jump to the real instruction 18374 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18375 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18376 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18377 * bail to the real handler if breakFlags==0. 18378 */ 18379 ldrb r3, [rSELF, #offThread_breakFlags] 18380 adrl lr, dvmAsmInstructionStart + (170 * 64) 18381 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18382 cmp r3, #0 18383 bxeq lr @ nothing to do - jump to real handler 18384 EXPORT_PC() 18385 mov r0, rPC @ arg0 18386 mov r1, rFP @ arg1 18387 mov r2, rSELF @ arg2 18388 b dvmCheckBefore @ (dPC,dFP,self) tail call 18389 18390 /* ------------------------------ */ 18391 .balign 64 18392 .L_ALT_OP_ADD_DOUBLE: /* 0xab */ 18393 /* File: armv5te/alt_stub.S */ 18394 /* 18395 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18396 * any interesting requests and then jump to the real instruction 18397 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18398 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18399 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18400 * bail to the real handler if breakFlags==0. 18401 */ 18402 ldrb r3, [rSELF, #offThread_breakFlags] 18403 adrl lr, dvmAsmInstructionStart + (171 * 64) 18404 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18405 cmp r3, #0 18406 bxeq lr @ nothing to do - jump to real handler 18407 EXPORT_PC() 18408 mov r0, rPC @ arg0 18409 mov r1, rFP @ arg1 18410 mov r2, rSELF @ arg2 18411 b dvmCheckBefore @ (dPC,dFP,self) tail call 18412 18413 /* ------------------------------ */ 18414 .balign 64 18415 .L_ALT_OP_SUB_DOUBLE: /* 0xac */ 18416 /* File: armv5te/alt_stub.S */ 18417 /* 18418 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18419 * any interesting requests and then jump to the real instruction 18420 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18421 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18422 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18423 * bail to the real handler if breakFlags==0. 18424 */ 18425 ldrb r3, [rSELF, #offThread_breakFlags] 18426 adrl lr, dvmAsmInstructionStart + (172 * 64) 18427 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18428 cmp r3, #0 18429 bxeq lr @ nothing to do - jump to real handler 18430 EXPORT_PC() 18431 mov r0, rPC @ arg0 18432 mov r1, rFP @ arg1 18433 mov r2, rSELF @ arg2 18434 b dvmCheckBefore @ (dPC,dFP,self) tail call 18435 18436 /* ------------------------------ */ 18437 .balign 64 18438 .L_ALT_OP_MUL_DOUBLE: /* 0xad */ 18439 /* File: armv5te/alt_stub.S */ 18440 /* 18441 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18442 * any interesting requests and then jump to the real instruction 18443 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18444 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18445 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18446 * bail to the real handler if breakFlags==0. 18447 */ 18448 ldrb r3, [rSELF, #offThread_breakFlags] 18449 adrl lr, dvmAsmInstructionStart + (173 * 64) 18450 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18451 cmp r3, #0 18452 bxeq lr @ nothing to do - jump to real handler 18453 EXPORT_PC() 18454 mov r0, rPC @ arg0 18455 mov r1, rFP @ arg1 18456 mov r2, rSELF @ arg2 18457 b dvmCheckBefore @ (dPC,dFP,self) tail call 18458 18459 /* ------------------------------ */ 18460 .balign 64 18461 .L_ALT_OP_DIV_DOUBLE: /* 0xae */ 18462 /* File: armv5te/alt_stub.S */ 18463 /* 18464 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18465 * any interesting requests and then jump to the real instruction 18466 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18467 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18468 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18469 * bail to the real handler if breakFlags==0. 18470 */ 18471 ldrb r3, [rSELF, #offThread_breakFlags] 18472 adrl lr, dvmAsmInstructionStart + (174 * 64) 18473 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18474 cmp r3, #0 18475 bxeq lr @ nothing to do - jump to real handler 18476 EXPORT_PC() 18477 mov r0, rPC @ arg0 18478 mov r1, rFP @ arg1 18479 mov r2, rSELF @ arg2 18480 b dvmCheckBefore @ (dPC,dFP,self) tail call 18481 18482 /* ------------------------------ */ 18483 .balign 64 18484 .L_ALT_OP_REM_DOUBLE: /* 0xaf */ 18485 /* File: armv5te/alt_stub.S */ 18486 /* 18487 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18488 * any interesting requests and then jump to the real instruction 18489 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18490 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18491 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18492 * bail to the real handler if breakFlags==0. 18493 */ 18494 ldrb r3, [rSELF, #offThread_breakFlags] 18495 adrl lr, dvmAsmInstructionStart + (175 * 64) 18496 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18497 cmp r3, #0 18498 bxeq lr @ nothing to do - jump to real handler 18499 EXPORT_PC() 18500 mov r0, rPC @ arg0 18501 mov r1, rFP @ arg1 18502 mov r2, rSELF @ arg2 18503 b dvmCheckBefore @ (dPC,dFP,self) tail call 18504 18505 /* ------------------------------ */ 18506 .balign 64 18507 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */ 18508 /* File: armv5te/alt_stub.S */ 18509 /* 18510 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18511 * any interesting requests and then jump to the real instruction 18512 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18513 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18514 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18515 * bail to the real handler if breakFlags==0. 18516 */ 18517 ldrb r3, [rSELF, #offThread_breakFlags] 18518 adrl lr, dvmAsmInstructionStart + (176 * 64) 18519 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18520 cmp r3, #0 18521 bxeq lr @ nothing to do - jump to real handler 18522 EXPORT_PC() 18523 mov r0, rPC @ arg0 18524 mov r1, rFP @ arg1 18525 mov r2, rSELF @ arg2 18526 b dvmCheckBefore @ (dPC,dFP,self) tail call 18527 18528 /* ------------------------------ */ 18529 .balign 64 18530 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */ 18531 /* File: armv5te/alt_stub.S */ 18532 /* 18533 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18534 * any interesting requests and then jump to the real instruction 18535 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18536 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18537 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18538 * bail to the real handler if breakFlags==0. 18539 */ 18540 ldrb r3, [rSELF, #offThread_breakFlags] 18541 adrl lr, dvmAsmInstructionStart + (177 * 64) 18542 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18543 cmp r3, #0 18544 bxeq lr @ nothing to do - jump to real handler 18545 EXPORT_PC() 18546 mov r0, rPC @ arg0 18547 mov r1, rFP @ arg1 18548 mov r2, rSELF @ arg2 18549 b dvmCheckBefore @ (dPC,dFP,self) tail call 18550 18551 /* ------------------------------ */ 18552 .balign 64 18553 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */ 18554 /* File: armv5te/alt_stub.S */ 18555 /* 18556 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18557 * any interesting requests and then jump to the real instruction 18558 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18559 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18560 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18561 * bail to the real handler if breakFlags==0. 18562 */ 18563 ldrb r3, [rSELF, #offThread_breakFlags] 18564 adrl lr, dvmAsmInstructionStart + (178 * 64) 18565 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18566 cmp r3, #0 18567 bxeq lr @ nothing to do - jump to real handler 18568 EXPORT_PC() 18569 mov r0, rPC @ arg0 18570 mov r1, rFP @ arg1 18571 mov r2, rSELF @ arg2 18572 b dvmCheckBefore @ (dPC,dFP,self) tail call 18573 18574 /* ------------------------------ */ 18575 .balign 64 18576 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */ 18577 /* File: armv5te/alt_stub.S */ 18578 /* 18579 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18580 * any interesting requests and then jump to the real instruction 18581 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18582 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18583 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18584 * bail to the real handler if breakFlags==0. 18585 */ 18586 ldrb r3, [rSELF, #offThread_breakFlags] 18587 adrl lr, dvmAsmInstructionStart + (179 * 64) 18588 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18589 cmp r3, #0 18590 bxeq lr @ nothing to do - jump to real handler 18591 EXPORT_PC() 18592 mov r0, rPC @ arg0 18593 mov r1, rFP @ arg1 18594 mov r2, rSELF @ arg2 18595 b dvmCheckBefore @ (dPC,dFP,self) tail call 18596 18597 /* ------------------------------ */ 18598 .balign 64 18599 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */ 18600 /* File: armv5te/alt_stub.S */ 18601 /* 18602 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18603 * any interesting requests and then jump to the real instruction 18604 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18605 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18606 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18607 * bail to the real handler if breakFlags==0. 18608 */ 18609 ldrb r3, [rSELF, #offThread_breakFlags] 18610 adrl lr, dvmAsmInstructionStart + (180 * 64) 18611 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18612 cmp r3, #0 18613 bxeq lr @ nothing to do - jump to real handler 18614 EXPORT_PC() 18615 mov r0, rPC @ arg0 18616 mov r1, rFP @ arg1 18617 mov r2, rSELF @ arg2 18618 b dvmCheckBefore @ (dPC,dFP,self) tail call 18619 18620 /* ------------------------------ */ 18621 .balign 64 18622 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */ 18623 /* File: armv5te/alt_stub.S */ 18624 /* 18625 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18626 * any interesting requests and then jump to the real instruction 18627 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18628 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18629 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18630 * bail to the real handler if breakFlags==0. 18631 */ 18632 ldrb r3, [rSELF, #offThread_breakFlags] 18633 adrl lr, dvmAsmInstructionStart + (181 * 64) 18634 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18635 cmp r3, #0 18636 bxeq lr @ nothing to do - jump to real handler 18637 EXPORT_PC() 18638 mov r0, rPC @ arg0 18639 mov r1, rFP @ arg1 18640 mov r2, rSELF @ arg2 18641 b dvmCheckBefore @ (dPC,dFP,self) tail call 18642 18643 /* ------------------------------ */ 18644 .balign 64 18645 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */ 18646 /* File: armv5te/alt_stub.S */ 18647 /* 18648 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18649 * any interesting requests and then jump to the real instruction 18650 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18651 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18652 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18653 * bail to the real handler if breakFlags==0. 18654 */ 18655 ldrb r3, [rSELF, #offThread_breakFlags] 18656 adrl lr, dvmAsmInstructionStart + (182 * 64) 18657 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18658 cmp r3, #0 18659 bxeq lr @ nothing to do - jump to real handler 18660 EXPORT_PC() 18661 mov r0, rPC @ arg0 18662 mov r1, rFP @ arg1 18663 mov r2, rSELF @ arg2 18664 b dvmCheckBefore @ (dPC,dFP,self) tail call 18665 18666 /* ------------------------------ */ 18667 .balign 64 18668 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */ 18669 /* File: armv5te/alt_stub.S */ 18670 /* 18671 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18672 * any interesting requests and then jump to the real instruction 18673 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18674 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18675 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18676 * bail to the real handler if breakFlags==0. 18677 */ 18678 ldrb r3, [rSELF, #offThread_breakFlags] 18679 adrl lr, dvmAsmInstructionStart + (183 * 64) 18680 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18681 cmp r3, #0 18682 bxeq lr @ nothing to do - jump to real handler 18683 EXPORT_PC() 18684 mov r0, rPC @ arg0 18685 mov r1, rFP @ arg1 18686 mov r2, rSELF @ arg2 18687 b dvmCheckBefore @ (dPC,dFP,self) tail call 18688 18689 /* ------------------------------ */ 18690 .balign 64 18691 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */ 18692 /* File: armv5te/alt_stub.S */ 18693 /* 18694 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18695 * any interesting requests and then jump to the real instruction 18696 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18697 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18698 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18699 * bail to the real handler if breakFlags==0. 18700 */ 18701 ldrb r3, [rSELF, #offThread_breakFlags] 18702 adrl lr, dvmAsmInstructionStart + (184 * 64) 18703 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18704 cmp r3, #0 18705 bxeq lr @ nothing to do - jump to real handler 18706 EXPORT_PC() 18707 mov r0, rPC @ arg0 18708 mov r1, rFP @ arg1 18709 mov r2, rSELF @ arg2 18710 b dvmCheckBefore @ (dPC,dFP,self) tail call 18711 18712 /* ------------------------------ */ 18713 .balign 64 18714 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */ 18715 /* File: armv5te/alt_stub.S */ 18716 /* 18717 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18718 * any interesting requests and then jump to the real instruction 18719 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18720 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18721 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18722 * bail to the real handler if breakFlags==0. 18723 */ 18724 ldrb r3, [rSELF, #offThread_breakFlags] 18725 adrl lr, dvmAsmInstructionStart + (185 * 64) 18726 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18727 cmp r3, #0 18728 bxeq lr @ nothing to do - jump to real handler 18729 EXPORT_PC() 18730 mov r0, rPC @ arg0 18731 mov r1, rFP @ arg1 18732 mov r2, rSELF @ arg2 18733 b dvmCheckBefore @ (dPC,dFP,self) tail call 18734 18735 /* ------------------------------ */ 18736 .balign 64 18737 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */ 18738 /* File: armv5te/alt_stub.S */ 18739 /* 18740 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18741 * any interesting requests and then jump to the real instruction 18742 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18743 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18744 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18745 * bail to the real handler if breakFlags==0. 18746 */ 18747 ldrb r3, [rSELF, #offThread_breakFlags] 18748 adrl lr, dvmAsmInstructionStart + (186 * 64) 18749 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18750 cmp r3, #0 18751 bxeq lr @ nothing to do - jump to real handler 18752 EXPORT_PC() 18753 mov r0, rPC @ arg0 18754 mov r1, rFP @ arg1 18755 mov r2, rSELF @ arg2 18756 b dvmCheckBefore @ (dPC,dFP,self) tail call 18757 18758 /* ------------------------------ */ 18759 .balign 64 18760 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */ 18761 /* File: armv5te/alt_stub.S */ 18762 /* 18763 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18764 * any interesting requests and then jump to the real instruction 18765 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18766 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18767 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18768 * bail to the real handler if breakFlags==0. 18769 */ 18770 ldrb r3, [rSELF, #offThread_breakFlags] 18771 adrl lr, dvmAsmInstructionStart + (187 * 64) 18772 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18773 cmp r3, #0 18774 bxeq lr @ nothing to do - jump to real handler 18775 EXPORT_PC() 18776 mov r0, rPC @ arg0 18777 mov r1, rFP @ arg1 18778 mov r2, rSELF @ arg2 18779 b dvmCheckBefore @ (dPC,dFP,self) tail call 18780 18781 /* ------------------------------ */ 18782 .balign 64 18783 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */ 18784 /* File: armv5te/alt_stub.S */ 18785 /* 18786 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18787 * any interesting requests and then jump to the real instruction 18788 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18789 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18790 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18791 * bail to the real handler if breakFlags==0. 18792 */ 18793 ldrb r3, [rSELF, #offThread_breakFlags] 18794 adrl lr, dvmAsmInstructionStart + (188 * 64) 18795 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18796 cmp r3, #0 18797 bxeq lr @ nothing to do - jump to real handler 18798 EXPORT_PC() 18799 mov r0, rPC @ arg0 18800 mov r1, rFP @ arg1 18801 mov r2, rSELF @ arg2 18802 b dvmCheckBefore @ (dPC,dFP,self) tail call 18803 18804 /* ------------------------------ */ 18805 .balign 64 18806 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */ 18807 /* File: armv5te/alt_stub.S */ 18808 /* 18809 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18810 * any interesting requests and then jump to the real instruction 18811 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18812 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18813 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18814 * bail to the real handler if breakFlags==0. 18815 */ 18816 ldrb r3, [rSELF, #offThread_breakFlags] 18817 adrl lr, dvmAsmInstructionStart + (189 * 64) 18818 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18819 cmp r3, #0 18820 bxeq lr @ nothing to do - jump to real handler 18821 EXPORT_PC() 18822 mov r0, rPC @ arg0 18823 mov r1, rFP @ arg1 18824 mov r2, rSELF @ arg2 18825 b dvmCheckBefore @ (dPC,dFP,self) tail call 18826 18827 /* ------------------------------ */ 18828 .balign 64 18829 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */ 18830 /* File: armv5te/alt_stub.S */ 18831 /* 18832 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18833 * any interesting requests and then jump to the real instruction 18834 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18835 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18836 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18837 * bail to the real handler if breakFlags==0. 18838 */ 18839 ldrb r3, [rSELF, #offThread_breakFlags] 18840 adrl lr, dvmAsmInstructionStart + (190 * 64) 18841 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18842 cmp r3, #0 18843 bxeq lr @ nothing to do - jump to real handler 18844 EXPORT_PC() 18845 mov r0, rPC @ arg0 18846 mov r1, rFP @ arg1 18847 mov r2, rSELF @ arg2 18848 b dvmCheckBefore @ (dPC,dFP,self) tail call 18849 18850 /* ------------------------------ */ 18851 .balign 64 18852 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */ 18853 /* File: armv5te/alt_stub.S */ 18854 /* 18855 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18856 * any interesting requests and then jump to the real instruction 18857 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18858 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18859 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18860 * bail to the real handler if breakFlags==0. 18861 */ 18862 ldrb r3, [rSELF, #offThread_breakFlags] 18863 adrl lr, dvmAsmInstructionStart + (191 * 64) 18864 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18865 cmp r3, #0 18866 bxeq lr @ nothing to do - jump to real handler 18867 EXPORT_PC() 18868 mov r0, rPC @ arg0 18869 mov r1, rFP @ arg1 18870 mov r2, rSELF @ arg2 18871 b dvmCheckBefore @ (dPC,dFP,self) tail call 18872 18873 /* ------------------------------ */ 18874 .balign 64 18875 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */ 18876 /* File: armv5te/alt_stub.S */ 18877 /* 18878 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18879 * any interesting requests and then jump to the real instruction 18880 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18881 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18882 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18883 * bail to the real handler if breakFlags==0. 18884 */ 18885 ldrb r3, [rSELF, #offThread_breakFlags] 18886 adrl lr, dvmAsmInstructionStart + (192 * 64) 18887 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18888 cmp r3, #0 18889 bxeq lr @ nothing to do - jump to real handler 18890 EXPORT_PC() 18891 mov r0, rPC @ arg0 18892 mov r1, rFP @ arg1 18893 mov r2, rSELF @ arg2 18894 b dvmCheckBefore @ (dPC,dFP,self) tail call 18895 18896 /* ------------------------------ */ 18897 .balign 64 18898 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */ 18899 /* File: armv5te/alt_stub.S */ 18900 /* 18901 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18902 * any interesting requests and then jump to the real instruction 18903 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18904 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18905 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18906 * bail to the real handler if breakFlags==0. 18907 */ 18908 ldrb r3, [rSELF, #offThread_breakFlags] 18909 adrl lr, dvmAsmInstructionStart + (193 * 64) 18910 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18911 cmp r3, #0 18912 bxeq lr @ nothing to do - jump to real handler 18913 EXPORT_PC() 18914 mov r0, rPC @ arg0 18915 mov r1, rFP @ arg1 18916 mov r2, rSELF @ arg2 18917 b dvmCheckBefore @ (dPC,dFP,self) tail call 18918 18919 /* ------------------------------ */ 18920 .balign 64 18921 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */ 18922 /* File: armv5te/alt_stub.S */ 18923 /* 18924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18925 * any interesting requests and then jump to the real instruction 18926 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18927 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18929 * bail to the real handler if breakFlags==0. 18930 */ 18931 ldrb r3, [rSELF, #offThread_breakFlags] 18932 adrl lr, dvmAsmInstructionStart + (194 * 64) 18933 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18934 cmp r3, #0 18935 bxeq lr @ nothing to do - jump to real handler 18936 EXPORT_PC() 18937 mov r0, rPC @ arg0 18938 mov r1, rFP @ arg1 18939 mov r2, rSELF @ arg2 18940 b dvmCheckBefore @ (dPC,dFP,self) tail call 18941 18942 /* ------------------------------ */ 18943 .balign 64 18944 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */ 18945 /* File: armv5te/alt_stub.S */ 18946 /* 18947 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18948 * any interesting requests and then jump to the real instruction 18949 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18950 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18951 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18952 * bail to the real handler if breakFlags==0. 18953 */ 18954 ldrb r3, [rSELF, #offThread_breakFlags] 18955 adrl lr, dvmAsmInstructionStart + (195 * 64) 18956 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18957 cmp r3, #0 18958 bxeq lr @ nothing to do - jump to real handler 18959 EXPORT_PC() 18960 mov r0, rPC @ arg0 18961 mov r1, rFP @ arg1 18962 mov r2, rSELF @ arg2 18963 b dvmCheckBefore @ (dPC,dFP,self) tail call 18964 18965 /* ------------------------------ */ 18966 .balign 64 18967 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */ 18968 /* File: armv5te/alt_stub.S */ 18969 /* 18970 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18971 * any interesting requests and then jump to the real instruction 18972 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18973 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18974 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18975 * bail to the real handler if breakFlags==0. 18976 */ 18977 ldrb r3, [rSELF, #offThread_breakFlags] 18978 adrl lr, dvmAsmInstructionStart + (196 * 64) 18979 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 18980 cmp r3, #0 18981 bxeq lr @ nothing to do - jump to real handler 18982 EXPORT_PC() 18983 mov r0, rPC @ arg0 18984 mov r1, rFP @ arg1 18985 mov r2, rSELF @ arg2 18986 b dvmCheckBefore @ (dPC,dFP,self) tail call 18987 18988 /* ------------------------------ */ 18989 .balign 64 18990 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */ 18991 /* File: armv5te/alt_stub.S */ 18992 /* 18993 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 18994 * any interesting requests and then jump to the real instruction 18995 * handler. Note that the call to dvmCheckBefore is done as a tail call. 18996 * rIBASE updates won't be seen until a refresh, and we can tell we have a 18997 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 18998 * bail to the real handler if breakFlags==0. 18999 */ 19000 ldrb r3, [rSELF, #offThread_breakFlags] 19001 adrl lr, dvmAsmInstructionStart + (197 * 64) 19002 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19003 cmp r3, #0 19004 bxeq lr @ nothing to do - jump to real handler 19005 EXPORT_PC() 19006 mov r0, rPC @ arg0 19007 mov r1, rFP @ arg1 19008 mov r2, rSELF @ arg2 19009 b dvmCheckBefore @ (dPC,dFP,self) tail call 19010 19011 /* ------------------------------ */ 19012 .balign 64 19013 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 19014 /* File: armv5te/alt_stub.S */ 19015 /* 19016 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19017 * any interesting requests and then jump to the real instruction 19018 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19019 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19020 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19021 * bail to the real handler if breakFlags==0. 19022 */ 19023 ldrb r3, [rSELF, #offThread_breakFlags] 19024 adrl lr, dvmAsmInstructionStart + (198 * 64) 19025 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19026 cmp r3, #0 19027 bxeq lr @ nothing to do - jump to real handler 19028 EXPORT_PC() 19029 mov r0, rPC @ arg0 19030 mov r1, rFP @ arg1 19031 mov r2, rSELF @ arg2 19032 b dvmCheckBefore @ (dPC,dFP,self) tail call 19033 19034 /* ------------------------------ */ 19035 .balign 64 19036 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 19037 /* File: armv5te/alt_stub.S */ 19038 /* 19039 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19040 * any interesting requests and then jump to the real instruction 19041 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19042 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19043 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19044 * bail to the real handler if breakFlags==0. 19045 */ 19046 ldrb r3, [rSELF, #offThread_breakFlags] 19047 adrl lr, dvmAsmInstructionStart + (199 * 64) 19048 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19049 cmp r3, #0 19050 bxeq lr @ nothing to do - jump to real handler 19051 EXPORT_PC() 19052 mov r0, rPC @ arg0 19053 mov r1, rFP @ arg1 19054 mov r2, rSELF @ arg2 19055 b dvmCheckBefore @ (dPC,dFP,self) tail call 19056 19057 /* ------------------------------ */ 19058 .balign 64 19059 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 19060 /* File: armv5te/alt_stub.S */ 19061 /* 19062 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19063 * any interesting requests and then jump to the real instruction 19064 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19065 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19066 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19067 * bail to the real handler if breakFlags==0. 19068 */ 19069 ldrb r3, [rSELF, #offThread_breakFlags] 19070 adrl lr, dvmAsmInstructionStart + (200 * 64) 19071 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19072 cmp r3, #0 19073 bxeq lr @ nothing to do - jump to real handler 19074 EXPORT_PC() 19075 mov r0, rPC @ arg0 19076 mov r1, rFP @ arg1 19077 mov r2, rSELF @ arg2 19078 b dvmCheckBefore @ (dPC,dFP,self) tail call 19079 19080 /* ------------------------------ */ 19081 .balign 64 19082 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 19083 /* File: armv5te/alt_stub.S */ 19084 /* 19085 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19086 * any interesting requests and then jump to the real instruction 19087 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19088 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19089 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19090 * bail to the real handler if breakFlags==0. 19091 */ 19092 ldrb r3, [rSELF, #offThread_breakFlags] 19093 adrl lr, dvmAsmInstructionStart + (201 * 64) 19094 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19095 cmp r3, #0 19096 bxeq lr @ nothing to do - jump to real handler 19097 EXPORT_PC() 19098 mov r0, rPC @ arg0 19099 mov r1, rFP @ arg1 19100 mov r2, rSELF @ arg2 19101 b dvmCheckBefore @ (dPC,dFP,self) tail call 19102 19103 /* ------------------------------ */ 19104 .balign 64 19105 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */ 19106 /* File: armv5te/alt_stub.S */ 19107 /* 19108 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19109 * any interesting requests and then jump to the real instruction 19110 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19111 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19112 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19113 * bail to the real handler if breakFlags==0. 19114 */ 19115 ldrb r3, [rSELF, #offThread_breakFlags] 19116 adrl lr, dvmAsmInstructionStart + (202 * 64) 19117 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19118 cmp r3, #0 19119 bxeq lr @ nothing to do - jump to real handler 19120 EXPORT_PC() 19121 mov r0, rPC @ arg0 19122 mov r1, rFP @ arg1 19123 mov r2, rSELF @ arg2 19124 b dvmCheckBefore @ (dPC,dFP,self) tail call 19125 19126 /* ------------------------------ */ 19127 .balign 64 19128 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 19129 /* File: armv5te/alt_stub.S */ 19130 /* 19131 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19132 * any interesting requests and then jump to the real instruction 19133 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19134 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19135 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19136 * bail to the real handler if breakFlags==0. 19137 */ 19138 ldrb r3, [rSELF, #offThread_breakFlags] 19139 adrl lr, dvmAsmInstructionStart + (203 * 64) 19140 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19141 cmp r3, #0 19142 bxeq lr @ nothing to do - jump to real handler 19143 EXPORT_PC() 19144 mov r0, rPC @ arg0 19145 mov r1, rFP @ arg1 19146 mov r2, rSELF @ arg2 19147 b dvmCheckBefore @ (dPC,dFP,self) tail call 19148 19149 /* ------------------------------ */ 19150 .balign 64 19151 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 19152 /* File: armv5te/alt_stub.S */ 19153 /* 19154 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19155 * any interesting requests and then jump to the real instruction 19156 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19157 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19158 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19159 * bail to the real handler if breakFlags==0. 19160 */ 19161 ldrb r3, [rSELF, #offThread_breakFlags] 19162 adrl lr, dvmAsmInstructionStart + (204 * 64) 19163 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19164 cmp r3, #0 19165 bxeq lr @ nothing to do - jump to real handler 19166 EXPORT_PC() 19167 mov r0, rPC @ arg0 19168 mov r1, rFP @ arg1 19169 mov r2, rSELF @ arg2 19170 b dvmCheckBefore @ (dPC,dFP,self) tail call 19171 19172 /* ------------------------------ */ 19173 .balign 64 19174 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 19175 /* File: armv5te/alt_stub.S */ 19176 /* 19177 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19178 * any interesting requests and then jump to the real instruction 19179 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19180 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19181 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19182 * bail to the real handler if breakFlags==0. 19183 */ 19184 ldrb r3, [rSELF, #offThread_breakFlags] 19185 adrl lr, dvmAsmInstructionStart + (205 * 64) 19186 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19187 cmp r3, #0 19188 bxeq lr @ nothing to do - jump to real handler 19189 EXPORT_PC() 19190 mov r0, rPC @ arg0 19191 mov r1, rFP @ arg1 19192 mov r2, rSELF @ arg2 19193 b dvmCheckBefore @ (dPC,dFP,self) tail call 19194 19195 /* ------------------------------ */ 19196 .balign 64 19197 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 19198 /* File: armv5te/alt_stub.S */ 19199 /* 19200 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19201 * any interesting requests and then jump to the real instruction 19202 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19203 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19204 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19205 * bail to the real handler if breakFlags==0. 19206 */ 19207 ldrb r3, [rSELF, #offThread_breakFlags] 19208 adrl lr, dvmAsmInstructionStart + (206 * 64) 19209 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19210 cmp r3, #0 19211 bxeq lr @ nothing to do - jump to real handler 19212 EXPORT_PC() 19213 mov r0, rPC @ arg0 19214 mov r1, rFP @ arg1 19215 mov r2, rSELF @ arg2 19216 b dvmCheckBefore @ (dPC,dFP,self) tail call 19217 19218 /* ------------------------------ */ 19219 .balign 64 19220 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 19221 /* File: armv5te/alt_stub.S */ 19222 /* 19223 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19224 * any interesting requests and then jump to the real instruction 19225 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19226 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19227 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19228 * bail to the real handler if breakFlags==0. 19229 */ 19230 ldrb r3, [rSELF, #offThread_breakFlags] 19231 adrl lr, dvmAsmInstructionStart + (207 * 64) 19232 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19233 cmp r3, #0 19234 bxeq lr @ nothing to do - jump to real handler 19235 EXPORT_PC() 19236 mov r0, rPC @ arg0 19237 mov r1, rFP @ arg1 19238 mov r2, rSELF @ arg2 19239 b dvmCheckBefore @ (dPC,dFP,self) tail call 19240 19241 /* ------------------------------ */ 19242 .balign 64 19243 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */ 19244 /* File: armv5te/alt_stub.S */ 19245 /* 19246 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19247 * any interesting requests and then jump to the real instruction 19248 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19249 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19250 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19251 * bail to the real handler if breakFlags==0. 19252 */ 19253 ldrb r3, [rSELF, #offThread_breakFlags] 19254 adrl lr, dvmAsmInstructionStart + (208 * 64) 19255 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19256 cmp r3, #0 19257 bxeq lr @ nothing to do - jump to real handler 19258 EXPORT_PC() 19259 mov r0, rPC @ arg0 19260 mov r1, rFP @ arg1 19261 mov r2, rSELF @ arg2 19262 b dvmCheckBefore @ (dPC,dFP,self) tail call 19263 19264 /* ------------------------------ */ 19265 .balign 64 19266 .L_ALT_OP_RSUB_INT: /* 0xd1 */ 19267 /* File: armv5te/alt_stub.S */ 19268 /* 19269 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19270 * any interesting requests and then jump to the real instruction 19271 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19272 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19273 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19274 * bail to the real handler if breakFlags==0. 19275 */ 19276 ldrb r3, [rSELF, #offThread_breakFlags] 19277 adrl lr, dvmAsmInstructionStart + (209 * 64) 19278 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19279 cmp r3, #0 19280 bxeq lr @ nothing to do - jump to real handler 19281 EXPORT_PC() 19282 mov r0, rPC @ arg0 19283 mov r1, rFP @ arg1 19284 mov r2, rSELF @ arg2 19285 b dvmCheckBefore @ (dPC,dFP,self) tail call 19286 19287 /* ------------------------------ */ 19288 .balign 64 19289 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */ 19290 /* File: armv5te/alt_stub.S */ 19291 /* 19292 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19293 * any interesting requests and then jump to the real instruction 19294 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19295 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19296 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19297 * bail to the real handler if breakFlags==0. 19298 */ 19299 ldrb r3, [rSELF, #offThread_breakFlags] 19300 adrl lr, dvmAsmInstructionStart + (210 * 64) 19301 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19302 cmp r3, #0 19303 bxeq lr @ nothing to do - jump to real handler 19304 EXPORT_PC() 19305 mov r0, rPC @ arg0 19306 mov r1, rFP @ arg1 19307 mov r2, rSELF @ arg2 19308 b dvmCheckBefore @ (dPC,dFP,self) tail call 19309 19310 /* ------------------------------ */ 19311 .balign 64 19312 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */ 19313 /* File: armv5te/alt_stub.S */ 19314 /* 19315 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19316 * any interesting requests and then jump to the real instruction 19317 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19318 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19319 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19320 * bail to the real handler if breakFlags==0. 19321 */ 19322 ldrb r3, [rSELF, #offThread_breakFlags] 19323 adrl lr, dvmAsmInstructionStart + (211 * 64) 19324 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19325 cmp r3, #0 19326 bxeq lr @ nothing to do - jump to real handler 19327 EXPORT_PC() 19328 mov r0, rPC @ arg0 19329 mov r1, rFP @ arg1 19330 mov r2, rSELF @ arg2 19331 b dvmCheckBefore @ (dPC,dFP,self) tail call 19332 19333 /* ------------------------------ */ 19334 .balign 64 19335 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */ 19336 /* File: armv5te/alt_stub.S */ 19337 /* 19338 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19339 * any interesting requests and then jump to the real instruction 19340 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19341 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19342 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19343 * bail to the real handler if breakFlags==0. 19344 */ 19345 ldrb r3, [rSELF, #offThread_breakFlags] 19346 adrl lr, dvmAsmInstructionStart + (212 * 64) 19347 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19348 cmp r3, #0 19349 bxeq lr @ nothing to do - jump to real handler 19350 EXPORT_PC() 19351 mov r0, rPC @ arg0 19352 mov r1, rFP @ arg1 19353 mov r2, rSELF @ arg2 19354 b dvmCheckBefore @ (dPC,dFP,self) tail call 19355 19356 /* ------------------------------ */ 19357 .balign 64 19358 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */ 19359 /* File: armv5te/alt_stub.S */ 19360 /* 19361 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19362 * any interesting requests and then jump to the real instruction 19363 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19364 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19365 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19366 * bail to the real handler if breakFlags==0. 19367 */ 19368 ldrb r3, [rSELF, #offThread_breakFlags] 19369 adrl lr, dvmAsmInstructionStart + (213 * 64) 19370 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19371 cmp r3, #0 19372 bxeq lr @ nothing to do - jump to real handler 19373 EXPORT_PC() 19374 mov r0, rPC @ arg0 19375 mov r1, rFP @ arg1 19376 mov r2, rSELF @ arg2 19377 b dvmCheckBefore @ (dPC,dFP,self) tail call 19378 19379 /* ------------------------------ */ 19380 .balign 64 19381 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */ 19382 /* File: armv5te/alt_stub.S */ 19383 /* 19384 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19385 * any interesting requests and then jump to the real instruction 19386 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19387 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19388 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19389 * bail to the real handler if breakFlags==0. 19390 */ 19391 ldrb r3, [rSELF, #offThread_breakFlags] 19392 adrl lr, dvmAsmInstructionStart + (214 * 64) 19393 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19394 cmp r3, #0 19395 bxeq lr @ nothing to do - jump to real handler 19396 EXPORT_PC() 19397 mov r0, rPC @ arg0 19398 mov r1, rFP @ arg1 19399 mov r2, rSELF @ arg2 19400 b dvmCheckBefore @ (dPC,dFP,self) tail call 19401 19402 /* ------------------------------ */ 19403 .balign 64 19404 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */ 19405 /* File: armv5te/alt_stub.S */ 19406 /* 19407 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19408 * any interesting requests and then jump to the real instruction 19409 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19410 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19411 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19412 * bail to the real handler if breakFlags==0. 19413 */ 19414 ldrb r3, [rSELF, #offThread_breakFlags] 19415 adrl lr, dvmAsmInstructionStart + (215 * 64) 19416 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19417 cmp r3, #0 19418 bxeq lr @ nothing to do - jump to real handler 19419 EXPORT_PC() 19420 mov r0, rPC @ arg0 19421 mov r1, rFP @ arg1 19422 mov r2, rSELF @ arg2 19423 b dvmCheckBefore @ (dPC,dFP,self) tail call 19424 19425 /* ------------------------------ */ 19426 .balign 64 19427 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */ 19428 /* File: armv5te/alt_stub.S */ 19429 /* 19430 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19431 * any interesting requests and then jump to the real instruction 19432 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19433 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19434 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19435 * bail to the real handler if breakFlags==0. 19436 */ 19437 ldrb r3, [rSELF, #offThread_breakFlags] 19438 adrl lr, dvmAsmInstructionStart + (216 * 64) 19439 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19440 cmp r3, #0 19441 bxeq lr @ nothing to do - jump to real handler 19442 EXPORT_PC() 19443 mov r0, rPC @ arg0 19444 mov r1, rFP @ arg1 19445 mov r2, rSELF @ arg2 19446 b dvmCheckBefore @ (dPC,dFP,self) tail call 19447 19448 /* ------------------------------ */ 19449 .balign 64 19450 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */ 19451 /* File: armv5te/alt_stub.S */ 19452 /* 19453 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19454 * any interesting requests and then jump to the real instruction 19455 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19456 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19457 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19458 * bail to the real handler if breakFlags==0. 19459 */ 19460 ldrb r3, [rSELF, #offThread_breakFlags] 19461 adrl lr, dvmAsmInstructionStart + (217 * 64) 19462 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19463 cmp r3, #0 19464 bxeq lr @ nothing to do - jump to real handler 19465 EXPORT_PC() 19466 mov r0, rPC @ arg0 19467 mov r1, rFP @ arg1 19468 mov r2, rSELF @ arg2 19469 b dvmCheckBefore @ (dPC,dFP,self) tail call 19470 19471 /* ------------------------------ */ 19472 .balign 64 19473 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */ 19474 /* File: armv5te/alt_stub.S */ 19475 /* 19476 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19477 * any interesting requests and then jump to the real instruction 19478 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19479 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19480 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19481 * bail to the real handler if breakFlags==0. 19482 */ 19483 ldrb r3, [rSELF, #offThread_breakFlags] 19484 adrl lr, dvmAsmInstructionStart + (218 * 64) 19485 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19486 cmp r3, #0 19487 bxeq lr @ nothing to do - jump to real handler 19488 EXPORT_PC() 19489 mov r0, rPC @ arg0 19490 mov r1, rFP @ arg1 19491 mov r2, rSELF @ arg2 19492 b dvmCheckBefore @ (dPC,dFP,self) tail call 19493 19494 /* ------------------------------ */ 19495 .balign 64 19496 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */ 19497 /* File: armv5te/alt_stub.S */ 19498 /* 19499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19500 * any interesting requests and then jump to the real instruction 19501 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19502 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19504 * bail to the real handler if breakFlags==0. 19505 */ 19506 ldrb r3, [rSELF, #offThread_breakFlags] 19507 adrl lr, dvmAsmInstructionStart + (219 * 64) 19508 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19509 cmp r3, #0 19510 bxeq lr @ nothing to do - jump to real handler 19511 EXPORT_PC() 19512 mov r0, rPC @ arg0 19513 mov r1, rFP @ arg1 19514 mov r2, rSELF @ arg2 19515 b dvmCheckBefore @ (dPC,dFP,self) tail call 19516 19517 /* ------------------------------ */ 19518 .balign 64 19519 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */ 19520 /* File: armv5te/alt_stub.S */ 19521 /* 19522 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19523 * any interesting requests and then jump to the real instruction 19524 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19525 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19526 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19527 * bail to the real handler if breakFlags==0. 19528 */ 19529 ldrb r3, [rSELF, #offThread_breakFlags] 19530 adrl lr, dvmAsmInstructionStart + (220 * 64) 19531 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19532 cmp r3, #0 19533 bxeq lr @ nothing to do - jump to real handler 19534 EXPORT_PC() 19535 mov r0, rPC @ arg0 19536 mov r1, rFP @ arg1 19537 mov r2, rSELF @ arg2 19538 b dvmCheckBefore @ (dPC,dFP,self) tail call 19539 19540 /* ------------------------------ */ 19541 .balign 64 19542 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */ 19543 /* File: armv5te/alt_stub.S */ 19544 /* 19545 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19546 * any interesting requests and then jump to the real instruction 19547 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19548 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19549 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19550 * bail to the real handler if breakFlags==0. 19551 */ 19552 ldrb r3, [rSELF, #offThread_breakFlags] 19553 adrl lr, dvmAsmInstructionStart + (221 * 64) 19554 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19555 cmp r3, #0 19556 bxeq lr @ nothing to do - jump to real handler 19557 EXPORT_PC() 19558 mov r0, rPC @ arg0 19559 mov r1, rFP @ arg1 19560 mov r2, rSELF @ arg2 19561 b dvmCheckBefore @ (dPC,dFP,self) tail call 19562 19563 /* ------------------------------ */ 19564 .balign 64 19565 .L_ALT_OP_OR_INT_LIT8: /* 0xde */ 19566 /* File: armv5te/alt_stub.S */ 19567 /* 19568 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19569 * any interesting requests and then jump to the real instruction 19570 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19571 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19572 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19573 * bail to the real handler if breakFlags==0. 19574 */ 19575 ldrb r3, [rSELF, #offThread_breakFlags] 19576 adrl lr, dvmAsmInstructionStart + (222 * 64) 19577 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19578 cmp r3, #0 19579 bxeq lr @ nothing to do - jump to real handler 19580 EXPORT_PC() 19581 mov r0, rPC @ arg0 19582 mov r1, rFP @ arg1 19583 mov r2, rSELF @ arg2 19584 b dvmCheckBefore @ (dPC,dFP,self) tail call 19585 19586 /* ------------------------------ */ 19587 .balign 64 19588 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */ 19589 /* File: armv5te/alt_stub.S */ 19590 /* 19591 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19592 * any interesting requests and then jump to the real instruction 19593 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19594 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19595 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19596 * bail to the real handler if breakFlags==0. 19597 */ 19598 ldrb r3, [rSELF, #offThread_breakFlags] 19599 adrl lr, dvmAsmInstructionStart + (223 * 64) 19600 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19601 cmp r3, #0 19602 bxeq lr @ nothing to do - jump to real handler 19603 EXPORT_PC() 19604 mov r0, rPC @ arg0 19605 mov r1, rFP @ arg1 19606 mov r2, rSELF @ arg2 19607 b dvmCheckBefore @ (dPC,dFP,self) tail call 19608 19609 /* ------------------------------ */ 19610 .balign 64 19611 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */ 19612 /* File: armv5te/alt_stub.S */ 19613 /* 19614 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19615 * any interesting requests and then jump to the real instruction 19616 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19617 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19618 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19619 * bail to the real handler if breakFlags==0. 19620 */ 19621 ldrb r3, [rSELF, #offThread_breakFlags] 19622 adrl lr, dvmAsmInstructionStart + (224 * 64) 19623 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19624 cmp r3, #0 19625 bxeq lr @ nothing to do - jump to real handler 19626 EXPORT_PC() 19627 mov r0, rPC @ arg0 19628 mov r1, rFP @ arg1 19629 mov r2, rSELF @ arg2 19630 b dvmCheckBefore @ (dPC,dFP,self) tail call 19631 19632 /* ------------------------------ */ 19633 .balign 64 19634 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */ 19635 /* File: armv5te/alt_stub.S */ 19636 /* 19637 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19638 * any interesting requests and then jump to the real instruction 19639 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19640 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19641 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19642 * bail to the real handler if breakFlags==0. 19643 */ 19644 ldrb r3, [rSELF, #offThread_breakFlags] 19645 adrl lr, dvmAsmInstructionStart + (225 * 64) 19646 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19647 cmp r3, #0 19648 bxeq lr @ nothing to do - jump to real handler 19649 EXPORT_PC() 19650 mov r0, rPC @ arg0 19651 mov r1, rFP @ arg1 19652 mov r2, rSELF @ arg2 19653 b dvmCheckBefore @ (dPC,dFP,self) tail call 19654 19655 /* ------------------------------ */ 19656 .balign 64 19657 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */ 19658 /* File: armv5te/alt_stub.S */ 19659 /* 19660 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19661 * any interesting requests and then jump to the real instruction 19662 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19663 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19664 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19665 * bail to the real handler if breakFlags==0. 19666 */ 19667 ldrb r3, [rSELF, #offThread_breakFlags] 19668 adrl lr, dvmAsmInstructionStart + (226 * 64) 19669 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19670 cmp r3, #0 19671 bxeq lr @ nothing to do - jump to real handler 19672 EXPORT_PC() 19673 mov r0, rPC @ arg0 19674 mov r1, rFP @ arg1 19675 mov r2, rSELF @ arg2 19676 b dvmCheckBefore @ (dPC,dFP,self) tail call 19677 19678 /* ------------------------------ */ 19679 .balign 64 19680 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */ 19681 /* File: armv5te/alt_stub.S */ 19682 /* 19683 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19684 * any interesting requests and then jump to the real instruction 19685 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19686 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19687 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19688 * bail to the real handler if breakFlags==0. 19689 */ 19690 ldrb r3, [rSELF, #offThread_breakFlags] 19691 adrl lr, dvmAsmInstructionStart + (227 * 64) 19692 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19693 cmp r3, #0 19694 bxeq lr @ nothing to do - jump to real handler 19695 EXPORT_PC() 19696 mov r0, rPC @ arg0 19697 mov r1, rFP @ arg1 19698 mov r2, rSELF @ arg2 19699 b dvmCheckBefore @ (dPC,dFP,self) tail call 19700 19701 /* ------------------------------ */ 19702 .balign 64 19703 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */ 19704 /* File: armv5te/alt_stub.S */ 19705 /* 19706 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19707 * any interesting requests and then jump to the real instruction 19708 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19709 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19710 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19711 * bail to the real handler if breakFlags==0. 19712 */ 19713 ldrb r3, [rSELF, #offThread_breakFlags] 19714 adrl lr, dvmAsmInstructionStart + (228 * 64) 19715 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19716 cmp r3, #0 19717 bxeq lr @ nothing to do - jump to real handler 19718 EXPORT_PC() 19719 mov r0, rPC @ arg0 19720 mov r1, rFP @ arg1 19721 mov r2, rSELF @ arg2 19722 b dvmCheckBefore @ (dPC,dFP,self) tail call 19723 19724 /* ------------------------------ */ 19725 .balign 64 19726 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */ 19727 /* File: armv5te/alt_stub.S */ 19728 /* 19729 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19730 * any interesting requests and then jump to the real instruction 19731 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19732 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19733 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19734 * bail to the real handler if breakFlags==0. 19735 */ 19736 ldrb r3, [rSELF, #offThread_breakFlags] 19737 adrl lr, dvmAsmInstructionStart + (229 * 64) 19738 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19739 cmp r3, #0 19740 bxeq lr @ nothing to do - jump to real handler 19741 EXPORT_PC() 19742 mov r0, rPC @ arg0 19743 mov r1, rFP @ arg1 19744 mov r2, rSELF @ arg2 19745 b dvmCheckBefore @ (dPC,dFP,self) tail call 19746 19747 /* ------------------------------ */ 19748 .balign 64 19749 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */ 19750 /* File: armv5te/alt_stub.S */ 19751 /* 19752 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19753 * any interesting requests and then jump to the real instruction 19754 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19755 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19756 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19757 * bail to the real handler if breakFlags==0. 19758 */ 19759 ldrb r3, [rSELF, #offThread_breakFlags] 19760 adrl lr, dvmAsmInstructionStart + (230 * 64) 19761 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19762 cmp r3, #0 19763 bxeq lr @ nothing to do - jump to real handler 19764 EXPORT_PC() 19765 mov r0, rPC @ arg0 19766 mov r1, rFP @ arg1 19767 mov r2, rSELF @ arg2 19768 b dvmCheckBefore @ (dPC,dFP,self) tail call 19769 19770 /* ------------------------------ */ 19771 .balign 64 19772 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 19773 /* File: armv5te/alt_stub.S */ 19774 /* 19775 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19776 * any interesting requests and then jump to the real instruction 19777 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19778 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19779 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19780 * bail to the real handler if breakFlags==0. 19781 */ 19782 ldrb r3, [rSELF, #offThread_breakFlags] 19783 adrl lr, dvmAsmInstructionStart + (231 * 64) 19784 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19785 cmp r3, #0 19786 bxeq lr @ nothing to do - jump to real handler 19787 EXPORT_PC() 19788 mov r0, rPC @ arg0 19789 mov r1, rFP @ arg1 19790 mov r2, rSELF @ arg2 19791 b dvmCheckBefore @ (dPC,dFP,self) tail call 19792 19793 /* ------------------------------ */ 19794 .balign 64 19795 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 19796 /* File: armv5te/alt_stub.S */ 19797 /* 19798 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19799 * any interesting requests and then jump to the real instruction 19800 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19801 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19802 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19803 * bail to the real handler if breakFlags==0. 19804 */ 19805 ldrb r3, [rSELF, #offThread_breakFlags] 19806 adrl lr, dvmAsmInstructionStart + (232 * 64) 19807 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19808 cmp r3, #0 19809 bxeq lr @ nothing to do - jump to real handler 19810 EXPORT_PC() 19811 mov r0, rPC @ arg0 19812 mov r1, rFP @ arg1 19813 mov r2, rSELF @ arg2 19814 b dvmCheckBefore @ (dPC,dFP,self) tail call 19815 19816 /* ------------------------------ */ 19817 .balign 64 19818 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 19819 /* File: armv5te/alt_stub.S */ 19820 /* 19821 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19822 * any interesting requests and then jump to the real instruction 19823 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19824 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19825 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19826 * bail to the real handler if breakFlags==0. 19827 */ 19828 ldrb r3, [rSELF, #offThread_breakFlags] 19829 adrl lr, dvmAsmInstructionStart + (233 * 64) 19830 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19831 cmp r3, #0 19832 bxeq lr @ nothing to do - jump to real handler 19833 EXPORT_PC() 19834 mov r0, rPC @ arg0 19835 mov r1, rFP @ arg1 19836 mov r2, rSELF @ arg2 19837 b dvmCheckBefore @ (dPC,dFP,self) tail call 19838 19839 /* ------------------------------ */ 19840 .balign 64 19841 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */ 19842 /* File: armv5te/alt_stub.S */ 19843 /* 19844 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19845 * any interesting requests and then jump to the real instruction 19846 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19847 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19848 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19849 * bail to the real handler if breakFlags==0. 19850 */ 19851 ldrb r3, [rSELF, #offThread_breakFlags] 19852 adrl lr, dvmAsmInstructionStart + (234 * 64) 19853 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19854 cmp r3, #0 19855 bxeq lr @ nothing to do - jump to real handler 19856 EXPORT_PC() 19857 mov r0, rPC @ arg0 19858 mov r1, rFP @ arg1 19859 mov r2, rSELF @ arg2 19860 b dvmCheckBefore @ (dPC,dFP,self) tail call 19861 19862 /* ------------------------------ */ 19863 .balign 64 19864 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 19865 /* File: armv5te/alt_stub.S */ 19866 /* 19867 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19868 * any interesting requests and then jump to the real instruction 19869 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19870 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19871 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19872 * bail to the real handler if breakFlags==0. 19873 */ 19874 ldrb r3, [rSELF, #offThread_breakFlags] 19875 adrl lr, dvmAsmInstructionStart + (235 * 64) 19876 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19877 cmp r3, #0 19878 bxeq lr @ nothing to do - jump to real handler 19879 EXPORT_PC() 19880 mov r0, rPC @ arg0 19881 mov r1, rFP @ arg1 19882 mov r2, rSELF @ arg2 19883 b dvmCheckBefore @ (dPC,dFP,self) tail call 19884 19885 /* ------------------------------ */ 19886 .balign 64 19887 .L_ALT_OP_BREAKPOINT: /* 0xec */ 19888 /* File: armv5te/alt_stub.S */ 19889 /* 19890 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19891 * any interesting requests and then jump to the real instruction 19892 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19893 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19894 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19895 * bail to the real handler if breakFlags==0. 19896 */ 19897 ldrb r3, [rSELF, #offThread_breakFlags] 19898 adrl lr, dvmAsmInstructionStart + (236 * 64) 19899 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19900 cmp r3, #0 19901 bxeq lr @ nothing to do - jump to real handler 19902 EXPORT_PC() 19903 mov r0, rPC @ arg0 19904 mov r1, rFP @ arg1 19905 mov r2, rSELF @ arg2 19906 b dvmCheckBefore @ (dPC,dFP,self) tail call 19907 19908 /* ------------------------------ */ 19909 .balign 64 19910 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 19911 /* File: armv5te/alt_stub.S */ 19912 /* 19913 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19914 * any interesting requests and then jump to the real instruction 19915 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19916 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19917 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19918 * bail to the real handler if breakFlags==0. 19919 */ 19920 ldrb r3, [rSELF, #offThread_breakFlags] 19921 adrl lr, dvmAsmInstructionStart + (237 * 64) 19922 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19923 cmp r3, #0 19924 bxeq lr @ nothing to do - jump to real handler 19925 EXPORT_PC() 19926 mov r0, rPC @ arg0 19927 mov r1, rFP @ arg1 19928 mov r2, rSELF @ arg2 19929 b dvmCheckBefore @ (dPC,dFP,self) tail call 19930 19931 /* ------------------------------ */ 19932 .balign 64 19933 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */ 19934 /* File: armv5te/alt_stub.S */ 19935 /* 19936 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19937 * any interesting requests and then jump to the real instruction 19938 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19939 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19940 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19941 * bail to the real handler if breakFlags==0. 19942 */ 19943 ldrb r3, [rSELF, #offThread_breakFlags] 19944 adrl lr, dvmAsmInstructionStart + (238 * 64) 19945 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19946 cmp r3, #0 19947 bxeq lr @ nothing to do - jump to real handler 19948 EXPORT_PC() 19949 mov r0, rPC @ arg0 19950 mov r1, rFP @ arg1 19951 mov r2, rSELF @ arg2 19952 b dvmCheckBefore @ (dPC,dFP,self) tail call 19953 19954 /* ------------------------------ */ 19955 .balign 64 19956 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 19957 /* File: armv5te/alt_stub.S */ 19958 /* 19959 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19960 * any interesting requests and then jump to the real instruction 19961 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19962 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19963 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19964 * bail to the real handler if breakFlags==0. 19965 */ 19966 ldrb r3, [rSELF, #offThread_breakFlags] 19967 adrl lr, dvmAsmInstructionStart + (239 * 64) 19968 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19969 cmp r3, #0 19970 bxeq lr @ nothing to do - jump to real handler 19971 EXPORT_PC() 19972 mov r0, rPC @ arg0 19973 mov r1, rFP @ arg1 19974 mov r2, rSELF @ arg2 19975 b dvmCheckBefore @ (dPC,dFP,self) tail call 19976 19977 /* ------------------------------ */ 19978 .balign 64 19979 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */ 19980 /* File: armv5te/alt_stub.S */ 19981 /* 19982 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 19983 * any interesting requests and then jump to the real instruction 19984 * handler. Note that the call to dvmCheckBefore is done as a tail call. 19985 * rIBASE updates won't be seen until a refresh, and we can tell we have a 19986 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 19987 * bail to the real handler if breakFlags==0. 19988 */ 19989 ldrb r3, [rSELF, #offThread_breakFlags] 19990 adrl lr, dvmAsmInstructionStart + (240 * 64) 19991 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 19992 cmp r3, #0 19993 bxeq lr @ nothing to do - jump to real handler 19994 EXPORT_PC() 19995 mov r0, rPC @ arg0 19996 mov r1, rFP @ arg1 19997 mov r2, rSELF @ arg2 19998 b dvmCheckBefore @ (dPC,dFP,self) tail call 19999 20000 /* ------------------------------ */ 20001 .balign 64 20002 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */ 20003 /* File: armv5te/alt_stub.S */ 20004 /* 20005 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20006 * any interesting requests and then jump to the real instruction 20007 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20008 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20009 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20010 * bail to the real handler if breakFlags==0. 20011 */ 20012 ldrb r3, [rSELF, #offThread_breakFlags] 20013 adrl lr, dvmAsmInstructionStart + (241 * 64) 20014 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20015 cmp r3, #0 20016 bxeq lr @ nothing to do - jump to real handler 20017 EXPORT_PC() 20018 mov r0, rPC @ arg0 20019 mov r1, rFP @ arg1 20020 mov r2, rSELF @ arg2 20021 b dvmCheckBefore @ (dPC,dFP,self) tail call 20022 20023 /* ------------------------------ */ 20024 .balign 64 20025 .L_ALT_OP_IGET_QUICK: /* 0xf2 */ 20026 /* File: armv5te/alt_stub.S */ 20027 /* 20028 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20029 * any interesting requests and then jump to the real instruction 20030 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20031 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20032 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20033 * bail to the real handler if breakFlags==0. 20034 */ 20035 ldrb r3, [rSELF, #offThread_breakFlags] 20036 adrl lr, dvmAsmInstructionStart + (242 * 64) 20037 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20038 cmp r3, #0 20039 bxeq lr @ nothing to do - jump to real handler 20040 EXPORT_PC() 20041 mov r0, rPC @ arg0 20042 mov r1, rFP @ arg1 20043 mov r2, rSELF @ arg2 20044 b dvmCheckBefore @ (dPC,dFP,self) tail call 20045 20046 /* ------------------------------ */ 20047 .balign 64 20048 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */ 20049 /* File: armv5te/alt_stub.S */ 20050 /* 20051 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20052 * any interesting requests and then jump to the real instruction 20053 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20054 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20055 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20056 * bail to the real handler if breakFlags==0. 20057 */ 20058 ldrb r3, [rSELF, #offThread_breakFlags] 20059 adrl lr, dvmAsmInstructionStart + (243 * 64) 20060 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20061 cmp r3, #0 20062 bxeq lr @ nothing to do - jump to real handler 20063 EXPORT_PC() 20064 mov r0, rPC @ arg0 20065 mov r1, rFP @ arg1 20066 mov r2, rSELF @ arg2 20067 b dvmCheckBefore @ (dPC,dFP,self) tail call 20068 20069 /* ------------------------------ */ 20070 .balign 64 20071 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 20072 /* File: armv5te/alt_stub.S */ 20073 /* 20074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20075 * any interesting requests and then jump to the real instruction 20076 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20077 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20079 * bail to the real handler if breakFlags==0. 20080 */ 20081 ldrb r3, [rSELF, #offThread_breakFlags] 20082 adrl lr, dvmAsmInstructionStart + (244 * 64) 20083 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20084 cmp r3, #0 20085 bxeq lr @ nothing to do - jump to real handler 20086 EXPORT_PC() 20087 mov r0, rPC @ arg0 20088 mov r1, rFP @ arg1 20089 mov r2, rSELF @ arg2 20090 b dvmCheckBefore @ (dPC,dFP,self) tail call 20091 20092 /* ------------------------------ */ 20093 .balign 64 20094 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */ 20095 /* File: armv5te/alt_stub.S */ 20096 /* 20097 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20098 * any interesting requests and then jump to the real instruction 20099 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20100 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20101 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20102 * bail to the real handler if breakFlags==0. 20103 */ 20104 ldrb r3, [rSELF, #offThread_breakFlags] 20105 adrl lr, dvmAsmInstructionStart + (245 * 64) 20106 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20107 cmp r3, #0 20108 bxeq lr @ nothing to do - jump to real handler 20109 EXPORT_PC() 20110 mov r0, rPC @ arg0 20111 mov r1, rFP @ arg1 20112 mov r2, rSELF @ arg2 20113 b dvmCheckBefore @ (dPC,dFP,self) tail call 20114 20115 /* ------------------------------ */ 20116 .balign 64 20117 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 20118 /* File: armv5te/alt_stub.S */ 20119 /* 20120 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20121 * any interesting requests and then jump to the real instruction 20122 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20123 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20124 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20125 * bail to the real handler if breakFlags==0. 20126 */ 20127 ldrb r3, [rSELF, #offThread_breakFlags] 20128 adrl lr, dvmAsmInstructionStart + (246 * 64) 20129 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20130 cmp r3, #0 20131 bxeq lr @ nothing to do - jump to real handler 20132 EXPORT_PC() 20133 mov r0, rPC @ arg0 20134 mov r1, rFP @ arg1 20135 mov r2, rSELF @ arg2 20136 b dvmCheckBefore @ (dPC,dFP,self) tail call 20137 20138 /* ------------------------------ */ 20139 .balign 64 20140 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 20141 /* File: armv5te/alt_stub.S */ 20142 /* 20143 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20144 * any interesting requests and then jump to the real instruction 20145 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20146 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20147 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20148 * bail to the real handler if breakFlags==0. 20149 */ 20150 ldrb r3, [rSELF, #offThread_breakFlags] 20151 adrl lr, dvmAsmInstructionStart + (247 * 64) 20152 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20153 cmp r3, #0 20154 bxeq lr @ nothing to do - jump to real handler 20155 EXPORT_PC() 20156 mov r0, rPC @ arg0 20157 mov r1, rFP @ arg1 20158 mov r2, rSELF @ arg2 20159 b dvmCheckBefore @ (dPC,dFP,self) tail call 20160 20161 /* ------------------------------ */ 20162 .balign 64 20163 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 20164 /* File: armv5te/alt_stub.S */ 20165 /* 20166 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20167 * any interesting requests and then jump to the real instruction 20168 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20169 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20170 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20171 * bail to the real handler if breakFlags==0. 20172 */ 20173 ldrb r3, [rSELF, #offThread_breakFlags] 20174 adrl lr, dvmAsmInstructionStart + (248 * 64) 20175 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20176 cmp r3, #0 20177 bxeq lr @ nothing to do - jump to real handler 20178 EXPORT_PC() 20179 mov r0, rPC @ arg0 20180 mov r1, rFP @ arg1 20181 mov r2, rSELF @ arg2 20182 b dvmCheckBefore @ (dPC,dFP,self) tail call 20183 20184 /* ------------------------------ */ 20185 .balign 64 20186 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 20187 /* File: armv5te/alt_stub.S */ 20188 /* 20189 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20190 * any interesting requests and then jump to the real instruction 20191 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20192 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20193 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20194 * bail to the real handler if breakFlags==0. 20195 */ 20196 ldrb r3, [rSELF, #offThread_breakFlags] 20197 adrl lr, dvmAsmInstructionStart + (249 * 64) 20198 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20199 cmp r3, #0 20200 bxeq lr @ nothing to do - jump to real handler 20201 EXPORT_PC() 20202 mov r0, rPC @ arg0 20203 mov r1, rFP @ arg1 20204 mov r2, rSELF @ arg2 20205 b dvmCheckBefore @ (dPC,dFP,self) tail call 20206 20207 /* ------------------------------ */ 20208 .balign 64 20209 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 20210 /* File: armv5te/alt_stub.S */ 20211 /* 20212 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20213 * any interesting requests and then jump to the real instruction 20214 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20215 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20216 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20217 * bail to the real handler if breakFlags==0. 20218 */ 20219 ldrb r3, [rSELF, #offThread_breakFlags] 20220 adrl lr, dvmAsmInstructionStart + (250 * 64) 20221 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20222 cmp r3, #0 20223 bxeq lr @ nothing to do - jump to real handler 20224 EXPORT_PC() 20225 mov r0, rPC @ arg0 20226 mov r1, rFP @ arg1 20227 mov r2, rSELF @ arg2 20228 b dvmCheckBefore @ (dPC,dFP,self) tail call 20229 20230 /* ------------------------------ */ 20231 .balign 64 20232 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 20233 /* File: armv5te/alt_stub.S */ 20234 /* 20235 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20236 * any interesting requests and then jump to the real instruction 20237 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20238 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20239 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20240 * bail to the real handler if breakFlags==0. 20241 */ 20242 ldrb r3, [rSELF, #offThread_breakFlags] 20243 adrl lr, dvmAsmInstructionStart + (251 * 64) 20244 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20245 cmp r3, #0 20246 bxeq lr @ nothing to do - jump to real handler 20247 EXPORT_PC() 20248 mov r0, rPC @ arg0 20249 mov r1, rFP @ arg1 20250 mov r2, rSELF @ arg2 20251 b dvmCheckBefore @ (dPC,dFP,self) tail call 20252 20253 /* ------------------------------ */ 20254 .balign 64 20255 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 20256 /* File: armv5te/alt_stub.S */ 20257 /* 20258 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20259 * any interesting requests and then jump to the real instruction 20260 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20261 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20262 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20263 * bail to the real handler if breakFlags==0. 20264 */ 20265 ldrb r3, [rSELF, #offThread_breakFlags] 20266 adrl lr, dvmAsmInstructionStart + (252 * 64) 20267 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20268 cmp r3, #0 20269 bxeq lr @ nothing to do - jump to real handler 20270 EXPORT_PC() 20271 mov r0, rPC @ arg0 20272 mov r1, rFP @ arg1 20273 mov r2, rSELF @ arg2 20274 b dvmCheckBefore @ (dPC,dFP,self) tail call 20275 20276 /* ------------------------------ */ 20277 .balign 64 20278 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 20279 /* File: armv5te/alt_stub.S */ 20280 /* 20281 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20282 * any interesting requests and then jump to the real instruction 20283 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20284 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20285 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20286 * bail to the real handler if breakFlags==0. 20287 */ 20288 ldrb r3, [rSELF, #offThread_breakFlags] 20289 adrl lr, dvmAsmInstructionStart + (253 * 64) 20290 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20291 cmp r3, #0 20292 bxeq lr @ nothing to do - jump to real handler 20293 EXPORT_PC() 20294 mov r0, rPC @ arg0 20295 mov r1, rFP @ arg1 20296 mov r2, rSELF @ arg2 20297 b dvmCheckBefore @ (dPC,dFP,self) tail call 20298 20299 /* ------------------------------ */ 20300 .balign 64 20301 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 20302 /* File: armv5te/alt_stub.S */ 20303 /* 20304 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20305 * any interesting requests and then jump to the real instruction 20306 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20307 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20308 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20309 * bail to the real handler if breakFlags==0. 20310 */ 20311 ldrb r3, [rSELF, #offThread_breakFlags] 20312 adrl lr, dvmAsmInstructionStart + (254 * 64) 20313 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20314 cmp r3, #0 20315 bxeq lr @ nothing to do - jump to real handler 20316 EXPORT_PC() 20317 mov r0, rPC @ arg0 20318 mov r1, rFP @ arg1 20319 mov r2, rSELF @ arg2 20320 b dvmCheckBefore @ (dPC,dFP,self) tail call 20321 20322 /* ------------------------------ */ 20323 .balign 64 20324 .L_ALT_OP_DISPATCH_FF: /* 0xff */ 20325 /* File: armv5te/ALT_OP_DISPATCH_FF.S */ 20326 /* 20327 * Unlike other alt stubs, we don't want to call dvmCheckBefore() here. 20328 * Instead, just treat this as a trampoline to reach the real alt 20329 * handler (which will do the dvmCheckBefore() call. 20330 */ 20331 mov ip, rINST, lsr #8 @ ip<- extended opcode 20332 add ip, ip, #256 @ add offset for extended opcodes 20333 GOTO_OPCODE(ip) @ go to proper extended handler 20334 20335 20336 /* ------------------------------ */ 20337 .balign 64 20338 .L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */ 20339 /* File: armv5te/alt_stub.S */ 20340 /* 20341 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20342 * any interesting requests and then jump to the real instruction 20343 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20344 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20345 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20346 * bail to the real handler if breakFlags==0. 20347 */ 20348 ldrb r3, [rSELF, #offThread_breakFlags] 20349 adrl lr, dvmAsmInstructionStart + (256 * 64) 20350 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20351 cmp r3, #0 20352 bxeq lr @ nothing to do - jump to real handler 20353 EXPORT_PC() 20354 mov r0, rPC @ arg0 20355 mov r1, rFP @ arg1 20356 mov r2, rSELF @ arg2 20357 b dvmCheckBefore @ (dPC,dFP,self) tail call 20358 20359 /* ------------------------------ */ 20360 .balign 64 20361 .L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */ 20362 /* File: armv5te/alt_stub.S */ 20363 /* 20364 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20365 * any interesting requests and then jump to the real instruction 20366 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20367 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20368 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20369 * bail to the real handler if breakFlags==0. 20370 */ 20371 ldrb r3, [rSELF, #offThread_breakFlags] 20372 adrl lr, dvmAsmInstructionStart + (257 * 64) 20373 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20374 cmp r3, #0 20375 bxeq lr @ nothing to do - jump to real handler 20376 EXPORT_PC() 20377 mov r0, rPC @ arg0 20378 mov r1, rFP @ arg1 20379 mov r2, rSELF @ arg2 20380 b dvmCheckBefore @ (dPC,dFP,self) tail call 20381 20382 /* ------------------------------ */ 20383 .balign 64 20384 .L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */ 20385 /* File: armv5te/alt_stub.S */ 20386 /* 20387 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20388 * any interesting requests and then jump to the real instruction 20389 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20390 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20391 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20392 * bail to the real handler if breakFlags==0. 20393 */ 20394 ldrb r3, [rSELF, #offThread_breakFlags] 20395 adrl lr, dvmAsmInstructionStart + (258 * 64) 20396 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20397 cmp r3, #0 20398 bxeq lr @ nothing to do - jump to real handler 20399 EXPORT_PC() 20400 mov r0, rPC @ arg0 20401 mov r1, rFP @ arg1 20402 mov r2, rSELF @ arg2 20403 b dvmCheckBefore @ (dPC,dFP,self) tail call 20404 20405 /* ------------------------------ */ 20406 .balign 64 20407 .L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */ 20408 /* File: armv5te/alt_stub.S */ 20409 /* 20410 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20411 * any interesting requests and then jump to the real instruction 20412 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20413 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20414 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20415 * bail to the real handler if breakFlags==0. 20416 */ 20417 ldrb r3, [rSELF, #offThread_breakFlags] 20418 adrl lr, dvmAsmInstructionStart + (259 * 64) 20419 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20420 cmp r3, #0 20421 bxeq lr @ nothing to do - jump to real handler 20422 EXPORT_PC() 20423 mov r0, rPC @ arg0 20424 mov r1, rFP @ arg1 20425 mov r2, rSELF @ arg2 20426 b dvmCheckBefore @ (dPC,dFP,self) tail call 20427 20428 /* ------------------------------ */ 20429 .balign 64 20430 .L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */ 20431 /* File: armv5te/alt_stub.S */ 20432 /* 20433 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20434 * any interesting requests and then jump to the real instruction 20435 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20436 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20437 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20438 * bail to the real handler if breakFlags==0. 20439 */ 20440 ldrb r3, [rSELF, #offThread_breakFlags] 20441 adrl lr, dvmAsmInstructionStart + (260 * 64) 20442 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20443 cmp r3, #0 20444 bxeq lr @ nothing to do - jump to real handler 20445 EXPORT_PC() 20446 mov r0, rPC @ arg0 20447 mov r1, rFP @ arg1 20448 mov r2, rSELF @ arg2 20449 b dvmCheckBefore @ (dPC,dFP,self) tail call 20450 20451 /* ------------------------------ */ 20452 .balign 64 20453 .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */ 20454 /* File: armv5te/alt_stub.S */ 20455 /* 20456 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20457 * any interesting requests and then jump to the real instruction 20458 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20459 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20460 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20461 * bail to the real handler if breakFlags==0. 20462 */ 20463 ldrb r3, [rSELF, #offThread_breakFlags] 20464 adrl lr, dvmAsmInstructionStart + (261 * 64) 20465 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20466 cmp r3, #0 20467 bxeq lr @ nothing to do - jump to real handler 20468 EXPORT_PC() 20469 mov r0, rPC @ arg0 20470 mov r1, rFP @ arg1 20471 mov r2, rSELF @ arg2 20472 b dvmCheckBefore @ (dPC,dFP,self) tail call 20473 20474 /* ------------------------------ */ 20475 .balign 64 20476 .L_ALT_OP_IGET_JUMBO: /* 0x106 */ 20477 /* File: armv5te/alt_stub.S */ 20478 /* 20479 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20480 * any interesting requests and then jump to the real instruction 20481 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20482 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20483 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20484 * bail to the real handler if breakFlags==0. 20485 */ 20486 ldrb r3, [rSELF, #offThread_breakFlags] 20487 adrl lr, dvmAsmInstructionStart + (262 * 64) 20488 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20489 cmp r3, #0 20490 bxeq lr @ nothing to do - jump to real handler 20491 EXPORT_PC() 20492 mov r0, rPC @ arg0 20493 mov r1, rFP @ arg1 20494 mov r2, rSELF @ arg2 20495 b dvmCheckBefore @ (dPC,dFP,self) tail call 20496 20497 /* ------------------------------ */ 20498 .balign 64 20499 .L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */ 20500 /* File: armv5te/alt_stub.S */ 20501 /* 20502 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20503 * any interesting requests and then jump to the real instruction 20504 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20505 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20506 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20507 * bail to the real handler if breakFlags==0. 20508 */ 20509 ldrb r3, [rSELF, #offThread_breakFlags] 20510 adrl lr, dvmAsmInstructionStart + (263 * 64) 20511 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20512 cmp r3, #0 20513 bxeq lr @ nothing to do - jump to real handler 20514 EXPORT_PC() 20515 mov r0, rPC @ arg0 20516 mov r1, rFP @ arg1 20517 mov r2, rSELF @ arg2 20518 b dvmCheckBefore @ (dPC,dFP,self) tail call 20519 20520 /* ------------------------------ */ 20521 .balign 64 20522 .L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */ 20523 /* File: armv5te/alt_stub.S */ 20524 /* 20525 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20526 * any interesting requests and then jump to the real instruction 20527 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20528 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20529 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20530 * bail to the real handler if breakFlags==0. 20531 */ 20532 ldrb r3, [rSELF, #offThread_breakFlags] 20533 adrl lr, dvmAsmInstructionStart + (264 * 64) 20534 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20535 cmp r3, #0 20536 bxeq lr @ nothing to do - jump to real handler 20537 EXPORT_PC() 20538 mov r0, rPC @ arg0 20539 mov r1, rFP @ arg1 20540 mov r2, rSELF @ arg2 20541 b dvmCheckBefore @ (dPC,dFP,self) tail call 20542 20543 /* ------------------------------ */ 20544 .balign 64 20545 .L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */ 20546 /* File: armv5te/alt_stub.S */ 20547 /* 20548 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20549 * any interesting requests and then jump to the real instruction 20550 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20551 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20552 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20553 * bail to the real handler if breakFlags==0. 20554 */ 20555 ldrb r3, [rSELF, #offThread_breakFlags] 20556 adrl lr, dvmAsmInstructionStart + (265 * 64) 20557 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20558 cmp r3, #0 20559 bxeq lr @ nothing to do - jump to real handler 20560 EXPORT_PC() 20561 mov r0, rPC @ arg0 20562 mov r1, rFP @ arg1 20563 mov r2, rSELF @ arg2 20564 b dvmCheckBefore @ (dPC,dFP,self) tail call 20565 20566 /* ------------------------------ */ 20567 .balign 64 20568 .L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */ 20569 /* File: armv5te/alt_stub.S */ 20570 /* 20571 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20572 * any interesting requests and then jump to the real instruction 20573 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20574 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20575 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20576 * bail to the real handler if breakFlags==0. 20577 */ 20578 ldrb r3, [rSELF, #offThread_breakFlags] 20579 adrl lr, dvmAsmInstructionStart + (266 * 64) 20580 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20581 cmp r3, #0 20582 bxeq lr @ nothing to do - jump to real handler 20583 EXPORT_PC() 20584 mov r0, rPC @ arg0 20585 mov r1, rFP @ arg1 20586 mov r2, rSELF @ arg2 20587 b dvmCheckBefore @ (dPC,dFP,self) tail call 20588 20589 /* ------------------------------ */ 20590 .balign 64 20591 .L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */ 20592 /* File: armv5te/alt_stub.S */ 20593 /* 20594 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20595 * any interesting requests and then jump to the real instruction 20596 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20597 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20598 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20599 * bail to the real handler if breakFlags==0. 20600 */ 20601 ldrb r3, [rSELF, #offThread_breakFlags] 20602 adrl lr, dvmAsmInstructionStart + (267 * 64) 20603 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20604 cmp r3, #0 20605 bxeq lr @ nothing to do - jump to real handler 20606 EXPORT_PC() 20607 mov r0, rPC @ arg0 20608 mov r1, rFP @ arg1 20609 mov r2, rSELF @ arg2 20610 b dvmCheckBefore @ (dPC,dFP,self) tail call 20611 20612 /* ------------------------------ */ 20613 .balign 64 20614 .L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */ 20615 /* File: armv5te/alt_stub.S */ 20616 /* 20617 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20618 * any interesting requests and then jump to the real instruction 20619 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20620 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20621 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20622 * bail to the real handler if breakFlags==0. 20623 */ 20624 ldrb r3, [rSELF, #offThread_breakFlags] 20625 adrl lr, dvmAsmInstructionStart + (268 * 64) 20626 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20627 cmp r3, #0 20628 bxeq lr @ nothing to do - jump to real handler 20629 EXPORT_PC() 20630 mov r0, rPC @ arg0 20631 mov r1, rFP @ arg1 20632 mov r2, rSELF @ arg2 20633 b dvmCheckBefore @ (dPC,dFP,self) tail call 20634 20635 /* ------------------------------ */ 20636 .balign 64 20637 .L_ALT_OP_IPUT_JUMBO: /* 0x10d */ 20638 /* File: armv5te/alt_stub.S */ 20639 /* 20640 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20641 * any interesting requests and then jump to the real instruction 20642 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20643 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20644 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20645 * bail to the real handler if breakFlags==0. 20646 */ 20647 ldrb r3, [rSELF, #offThread_breakFlags] 20648 adrl lr, dvmAsmInstructionStart + (269 * 64) 20649 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20650 cmp r3, #0 20651 bxeq lr @ nothing to do - jump to real handler 20652 EXPORT_PC() 20653 mov r0, rPC @ arg0 20654 mov r1, rFP @ arg1 20655 mov r2, rSELF @ arg2 20656 b dvmCheckBefore @ (dPC,dFP,self) tail call 20657 20658 /* ------------------------------ */ 20659 .balign 64 20660 .L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */ 20661 /* File: armv5te/alt_stub.S */ 20662 /* 20663 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20664 * any interesting requests and then jump to the real instruction 20665 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20666 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20667 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20668 * bail to the real handler if breakFlags==0. 20669 */ 20670 ldrb r3, [rSELF, #offThread_breakFlags] 20671 adrl lr, dvmAsmInstructionStart + (270 * 64) 20672 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20673 cmp r3, #0 20674 bxeq lr @ nothing to do - jump to real handler 20675 EXPORT_PC() 20676 mov r0, rPC @ arg0 20677 mov r1, rFP @ arg1 20678 mov r2, rSELF @ arg2 20679 b dvmCheckBefore @ (dPC,dFP,self) tail call 20680 20681 /* ------------------------------ */ 20682 .balign 64 20683 .L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */ 20684 /* File: armv5te/alt_stub.S */ 20685 /* 20686 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20687 * any interesting requests and then jump to the real instruction 20688 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20689 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20690 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20691 * bail to the real handler if breakFlags==0. 20692 */ 20693 ldrb r3, [rSELF, #offThread_breakFlags] 20694 adrl lr, dvmAsmInstructionStart + (271 * 64) 20695 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20696 cmp r3, #0 20697 bxeq lr @ nothing to do - jump to real handler 20698 EXPORT_PC() 20699 mov r0, rPC @ arg0 20700 mov r1, rFP @ arg1 20701 mov r2, rSELF @ arg2 20702 b dvmCheckBefore @ (dPC,dFP,self) tail call 20703 20704 /* ------------------------------ */ 20705 .balign 64 20706 .L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */ 20707 /* File: armv5te/alt_stub.S */ 20708 /* 20709 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20710 * any interesting requests and then jump to the real instruction 20711 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20712 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20713 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20714 * bail to the real handler if breakFlags==0. 20715 */ 20716 ldrb r3, [rSELF, #offThread_breakFlags] 20717 adrl lr, dvmAsmInstructionStart + (272 * 64) 20718 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20719 cmp r3, #0 20720 bxeq lr @ nothing to do - jump to real handler 20721 EXPORT_PC() 20722 mov r0, rPC @ arg0 20723 mov r1, rFP @ arg1 20724 mov r2, rSELF @ arg2 20725 b dvmCheckBefore @ (dPC,dFP,self) tail call 20726 20727 /* ------------------------------ */ 20728 .balign 64 20729 .L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */ 20730 /* File: armv5te/alt_stub.S */ 20731 /* 20732 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20733 * any interesting requests and then jump to the real instruction 20734 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20735 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20736 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20737 * bail to the real handler if breakFlags==0. 20738 */ 20739 ldrb r3, [rSELF, #offThread_breakFlags] 20740 adrl lr, dvmAsmInstructionStart + (273 * 64) 20741 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20742 cmp r3, #0 20743 bxeq lr @ nothing to do - jump to real handler 20744 EXPORT_PC() 20745 mov r0, rPC @ arg0 20746 mov r1, rFP @ arg1 20747 mov r2, rSELF @ arg2 20748 b dvmCheckBefore @ (dPC,dFP,self) tail call 20749 20750 /* ------------------------------ */ 20751 .balign 64 20752 .L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */ 20753 /* File: armv5te/alt_stub.S */ 20754 /* 20755 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20756 * any interesting requests and then jump to the real instruction 20757 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20758 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20759 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20760 * bail to the real handler if breakFlags==0. 20761 */ 20762 ldrb r3, [rSELF, #offThread_breakFlags] 20763 adrl lr, dvmAsmInstructionStart + (274 * 64) 20764 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20765 cmp r3, #0 20766 bxeq lr @ nothing to do - jump to real handler 20767 EXPORT_PC() 20768 mov r0, rPC @ arg0 20769 mov r1, rFP @ arg1 20770 mov r2, rSELF @ arg2 20771 b dvmCheckBefore @ (dPC,dFP,self) tail call 20772 20773 /* ------------------------------ */ 20774 .balign 64 20775 .L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */ 20776 /* File: armv5te/alt_stub.S */ 20777 /* 20778 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20779 * any interesting requests and then jump to the real instruction 20780 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20781 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20782 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20783 * bail to the real handler if breakFlags==0. 20784 */ 20785 ldrb r3, [rSELF, #offThread_breakFlags] 20786 adrl lr, dvmAsmInstructionStart + (275 * 64) 20787 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20788 cmp r3, #0 20789 bxeq lr @ nothing to do - jump to real handler 20790 EXPORT_PC() 20791 mov r0, rPC @ arg0 20792 mov r1, rFP @ arg1 20793 mov r2, rSELF @ arg2 20794 b dvmCheckBefore @ (dPC,dFP,self) tail call 20795 20796 /* ------------------------------ */ 20797 .balign 64 20798 .L_ALT_OP_SGET_JUMBO: /* 0x114 */ 20799 /* File: armv5te/alt_stub.S */ 20800 /* 20801 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20802 * any interesting requests and then jump to the real instruction 20803 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20804 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20805 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20806 * bail to the real handler if breakFlags==0. 20807 */ 20808 ldrb r3, [rSELF, #offThread_breakFlags] 20809 adrl lr, dvmAsmInstructionStart + (276 * 64) 20810 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20811 cmp r3, #0 20812 bxeq lr @ nothing to do - jump to real handler 20813 EXPORT_PC() 20814 mov r0, rPC @ arg0 20815 mov r1, rFP @ arg1 20816 mov r2, rSELF @ arg2 20817 b dvmCheckBefore @ (dPC,dFP,self) tail call 20818 20819 /* ------------------------------ */ 20820 .balign 64 20821 .L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */ 20822 /* File: armv5te/alt_stub.S */ 20823 /* 20824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20825 * any interesting requests and then jump to the real instruction 20826 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20827 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20829 * bail to the real handler if breakFlags==0. 20830 */ 20831 ldrb r3, [rSELF, #offThread_breakFlags] 20832 adrl lr, dvmAsmInstructionStart + (277 * 64) 20833 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20834 cmp r3, #0 20835 bxeq lr @ nothing to do - jump to real handler 20836 EXPORT_PC() 20837 mov r0, rPC @ arg0 20838 mov r1, rFP @ arg1 20839 mov r2, rSELF @ arg2 20840 b dvmCheckBefore @ (dPC,dFP,self) tail call 20841 20842 /* ------------------------------ */ 20843 .balign 64 20844 .L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */ 20845 /* File: armv5te/alt_stub.S */ 20846 /* 20847 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20848 * any interesting requests and then jump to the real instruction 20849 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20850 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20851 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20852 * bail to the real handler if breakFlags==0. 20853 */ 20854 ldrb r3, [rSELF, #offThread_breakFlags] 20855 adrl lr, dvmAsmInstructionStart + (278 * 64) 20856 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20857 cmp r3, #0 20858 bxeq lr @ nothing to do - jump to real handler 20859 EXPORT_PC() 20860 mov r0, rPC @ arg0 20861 mov r1, rFP @ arg1 20862 mov r2, rSELF @ arg2 20863 b dvmCheckBefore @ (dPC,dFP,self) tail call 20864 20865 /* ------------------------------ */ 20866 .balign 64 20867 .L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */ 20868 /* File: armv5te/alt_stub.S */ 20869 /* 20870 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20871 * any interesting requests and then jump to the real instruction 20872 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20873 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20874 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20875 * bail to the real handler if breakFlags==0. 20876 */ 20877 ldrb r3, [rSELF, #offThread_breakFlags] 20878 adrl lr, dvmAsmInstructionStart + (279 * 64) 20879 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20880 cmp r3, #0 20881 bxeq lr @ nothing to do - jump to real handler 20882 EXPORT_PC() 20883 mov r0, rPC @ arg0 20884 mov r1, rFP @ arg1 20885 mov r2, rSELF @ arg2 20886 b dvmCheckBefore @ (dPC,dFP,self) tail call 20887 20888 /* ------------------------------ */ 20889 .balign 64 20890 .L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */ 20891 /* File: armv5te/alt_stub.S */ 20892 /* 20893 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20894 * any interesting requests and then jump to the real instruction 20895 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20896 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20897 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20898 * bail to the real handler if breakFlags==0. 20899 */ 20900 ldrb r3, [rSELF, #offThread_breakFlags] 20901 adrl lr, dvmAsmInstructionStart + (280 * 64) 20902 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20903 cmp r3, #0 20904 bxeq lr @ nothing to do - jump to real handler 20905 EXPORT_PC() 20906 mov r0, rPC @ arg0 20907 mov r1, rFP @ arg1 20908 mov r2, rSELF @ arg2 20909 b dvmCheckBefore @ (dPC,dFP,self) tail call 20910 20911 /* ------------------------------ */ 20912 .balign 64 20913 .L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */ 20914 /* File: armv5te/alt_stub.S */ 20915 /* 20916 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20917 * any interesting requests and then jump to the real instruction 20918 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20919 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20920 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20921 * bail to the real handler if breakFlags==0. 20922 */ 20923 ldrb r3, [rSELF, #offThread_breakFlags] 20924 adrl lr, dvmAsmInstructionStart + (281 * 64) 20925 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20926 cmp r3, #0 20927 bxeq lr @ nothing to do - jump to real handler 20928 EXPORT_PC() 20929 mov r0, rPC @ arg0 20930 mov r1, rFP @ arg1 20931 mov r2, rSELF @ arg2 20932 b dvmCheckBefore @ (dPC,dFP,self) tail call 20933 20934 /* ------------------------------ */ 20935 .balign 64 20936 .L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */ 20937 /* File: armv5te/alt_stub.S */ 20938 /* 20939 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20940 * any interesting requests and then jump to the real instruction 20941 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20942 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20943 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20944 * bail to the real handler if breakFlags==0. 20945 */ 20946 ldrb r3, [rSELF, #offThread_breakFlags] 20947 adrl lr, dvmAsmInstructionStart + (282 * 64) 20948 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20949 cmp r3, #0 20950 bxeq lr @ nothing to do - jump to real handler 20951 EXPORT_PC() 20952 mov r0, rPC @ arg0 20953 mov r1, rFP @ arg1 20954 mov r2, rSELF @ arg2 20955 b dvmCheckBefore @ (dPC,dFP,self) tail call 20956 20957 /* ------------------------------ */ 20958 .balign 64 20959 .L_ALT_OP_SPUT_JUMBO: /* 0x11b */ 20960 /* File: armv5te/alt_stub.S */ 20961 /* 20962 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20963 * any interesting requests and then jump to the real instruction 20964 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20965 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20966 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20967 * bail to the real handler if breakFlags==0. 20968 */ 20969 ldrb r3, [rSELF, #offThread_breakFlags] 20970 adrl lr, dvmAsmInstructionStart + (283 * 64) 20971 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20972 cmp r3, #0 20973 bxeq lr @ nothing to do - jump to real handler 20974 EXPORT_PC() 20975 mov r0, rPC @ arg0 20976 mov r1, rFP @ arg1 20977 mov r2, rSELF @ arg2 20978 b dvmCheckBefore @ (dPC,dFP,self) tail call 20979 20980 /* ------------------------------ */ 20981 .balign 64 20982 .L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */ 20983 /* File: armv5te/alt_stub.S */ 20984 /* 20985 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 20986 * any interesting requests and then jump to the real instruction 20987 * handler. Note that the call to dvmCheckBefore is done as a tail call. 20988 * rIBASE updates won't be seen until a refresh, and we can tell we have a 20989 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 20990 * bail to the real handler if breakFlags==0. 20991 */ 20992 ldrb r3, [rSELF, #offThread_breakFlags] 20993 adrl lr, dvmAsmInstructionStart + (284 * 64) 20994 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 20995 cmp r3, #0 20996 bxeq lr @ nothing to do - jump to real handler 20997 EXPORT_PC() 20998 mov r0, rPC @ arg0 20999 mov r1, rFP @ arg1 21000 mov r2, rSELF @ arg2 21001 b dvmCheckBefore @ (dPC,dFP,self) tail call 21002 21003 /* ------------------------------ */ 21004 .balign 64 21005 .L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */ 21006 /* File: armv5te/alt_stub.S */ 21007 /* 21008 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21009 * any interesting requests and then jump to the real instruction 21010 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21011 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21012 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21013 * bail to the real handler if breakFlags==0. 21014 */ 21015 ldrb r3, [rSELF, #offThread_breakFlags] 21016 adrl lr, dvmAsmInstructionStart + (285 * 64) 21017 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21018 cmp r3, #0 21019 bxeq lr @ nothing to do - jump to real handler 21020 EXPORT_PC() 21021 mov r0, rPC @ arg0 21022 mov r1, rFP @ arg1 21023 mov r2, rSELF @ arg2 21024 b dvmCheckBefore @ (dPC,dFP,self) tail call 21025 21026 /* ------------------------------ */ 21027 .balign 64 21028 .L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */ 21029 /* File: armv5te/alt_stub.S */ 21030 /* 21031 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21032 * any interesting requests and then jump to the real instruction 21033 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21034 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21035 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21036 * bail to the real handler if breakFlags==0. 21037 */ 21038 ldrb r3, [rSELF, #offThread_breakFlags] 21039 adrl lr, dvmAsmInstructionStart + (286 * 64) 21040 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21041 cmp r3, #0 21042 bxeq lr @ nothing to do - jump to real handler 21043 EXPORT_PC() 21044 mov r0, rPC @ arg0 21045 mov r1, rFP @ arg1 21046 mov r2, rSELF @ arg2 21047 b dvmCheckBefore @ (dPC,dFP,self) tail call 21048 21049 /* ------------------------------ */ 21050 .balign 64 21051 .L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */ 21052 /* File: armv5te/alt_stub.S */ 21053 /* 21054 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21055 * any interesting requests and then jump to the real instruction 21056 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21057 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21058 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21059 * bail to the real handler if breakFlags==0. 21060 */ 21061 ldrb r3, [rSELF, #offThread_breakFlags] 21062 adrl lr, dvmAsmInstructionStart + (287 * 64) 21063 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21064 cmp r3, #0 21065 bxeq lr @ nothing to do - jump to real handler 21066 EXPORT_PC() 21067 mov r0, rPC @ arg0 21068 mov r1, rFP @ arg1 21069 mov r2, rSELF @ arg2 21070 b dvmCheckBefore @ (dPC,dFP,self) tail call 21071 21072 /* ------------------------------ */ 21073 .balign 64 21074 .L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */ 21075 /* File: armv5te/alt_stub.S */ 21076 /* 21077 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21078 * any interesting requests and then jump to the real instruction 21079 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21080 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21081 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21082 * bail to the real handler if breakFlags==0. 21083 */ 21084 ldrb r3, [rSELF, #offThread_breakFlags] 21085 adrl lr, dvmAsmInstructionStart + (288 * 64) 21086 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21087 cmp r3, #0 21088 bxeq lr @ nothing to do - jump to real handler 21089 EXPORT_PC() 21090 mov r0, rPC @ arg0 21091 mov r1, rFP @ arg1 21092 mov r2, rSELF @ arg2 21093 b dvmCheckBefore @ (dPC,dFP,self) tail call 21094 21095 /* ------------------------------ */ 21096 .balign 64 21097 .L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */ 21098 /* File: armv5te/alt_stub.S */ 21099 /* 21100 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21101 * any interesting requests and then jump to the real instruction 21102 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21103 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21104 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21105 * bail to the real handler if breakFlags==0. 21106 */ 21107 ldrb r3, [rSELF, #offThread_breakFlags] 21108 adrl lr, dvmAsmInstructionStart + (289 * 64) 21109 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21110 cmp r3, #0 21111 bxeq lr @ nothing to do - jump to real handler 21112 EXPORT_PC() 21113 mov r0, rPC @ arg0 21114 mov r1, rFP @ arg1 21115 mov r2, rSELF @ arg2 21116 b dvmCheckBefore @ (dPC,dFP,self) tail call 21117 21118 /* ------------------------------ */ 21119 .balign 64 21120 .L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */ 21121 /* File: armv5te/alt_stub.S */ 21122 /* 21123 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21124 * any interesting requests and then jump to the real instruction 21125 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21126 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21127 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21128 * bail to the real handler if breakFlags==0. 21129 */ 21130 ldrb r3, [rSELF, #offThread_breakFlags] 21131 adrl lr, dvmAsmInstructionStart + (290 * 64) 21132 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21133 cmp r3, #0 21134 bxeq lr @ nothing to do - jump to real handler 21135 EXPORT_PC() 21136 mov r0, rPC @ arg0 21137 mov r1, rFP @ arg1 21138 mov r2, rSELF @ arg2 21139 b dvmCheckBefore @ (dPC,dFP,self) tail call 21140 21141 /* ------------------------------ */ 21142 .balign 64 21143 .L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */ 21144 /* File: armv5te/alt_stub.S */ 21145 /* 21146 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21147 * any interesting requests and then jump to the real instruction 21148 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21149 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21150 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21151 * bail to the real handler if breakFlags==0. 21152 */ 21153 ldrb r3, [rSELF, #offThread_breakFlags] 21154 adrl lr, dvmAsmInstructionStart + (291 * 64) 21155 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21156 cmp r3, #0 21157 bxeq lr @ nothing to do - jump to real handler 21158 EXPORT_PC() 21159 mov r0, rPC @ arg0 21160 mov r1, rFP @ arg1 21161 mov r2, rSELF @ arg2 21162 b dvmCheckBefore @ (dPC,dFP,self) tail call 21163 21164 /* ------------------------------ */ 21165 .balign 64 21166 .L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */ 21167 /* File: armv5te/alt_stub.S */ 21168 /* 21169 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21170 * any interesting requests and then jump to the real instruction 21171 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21172 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21173 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21174 * bail to the real handler if breakFlags==0. 21175 */ 21176 ldrb r3, [rSELF, #offThread_breakFlags] 21177 adrl lr, dvmAsmInstructionStart + (292 * 64) 21178 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21179 cmp r3, #0 21180 bxeq lr @ nothing to do - jump to real handler 21181 EXPORT_PC() 21182 mov r0, rPC @ arg0 21183 mov r1, rFP @ arg1 21184 mov r2, rSELF @ arg2 21185 b dvmCheckBefore @ (dPC,dFP,self) tail call 21186 21187 /* ------------------------------ */ 21188 .balign 64 21189 .L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */ 21190 /* File: armv5te/alt_stub.S */ 21191 /* 21192 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21193 * any interesting requests and then jump to the real instruction 21194 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21195 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21196 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21197 * bail to the real handler if breakFlags==0. 21198 */ 21199 ldrb r3, [rSELF, #offThread_breakFlags] 21200 adrl lr, dvmAsmInstructionStart + (293 * 64) 21201 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21202 cmp r3, #0 21203 bxeq lr @ nothing to do - jump to real handler 21204 EXPORT_PC() 21205 mov r0, rPC @ arg0 21206 mov r1, rFP @ arg1 21207 mov r2, rSELF @ arg2 21208 b dvmCheckBefore @ (dPC,dFP,self) tail call 21209 21210 /* ------------------------------ */ 21211 .balign 64 21212 .L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */ 21213 /* File: armv5te/alt_stub.S */ 21214 /* 21215 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21216 * any interesting requests and then jump to the real instruction 21217 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21218 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21219 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21220 * bail to the real handler if breakFlags==0. 21221 */ 21222 ldrb r3, [rSELF, #offThread_breakFlags] 21223 adrl lr, dvmAsmInstructionStart + (294 * 64) 21224 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21225 cmp r3, #0 21226 bxeq lr @ nothing to do - jump to real handler 21227 EXPORT_PC() 21228 mov r0, rPC @ arg0 21229 mov r1, rFP @ arg1 21230 mov r2, rSELF @ arg2 21231 b dvmCheckBefore @ (dPC,dFP,self) tail call 21232 21233 /* ------------------------------ */ 21234 .balign 64 21235 .L_ALT_OP_UNUSED_27FF: /* 0x127 */ 21236 /* File: armv5te/alt_stub.S */ 21237 /* 21238 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21239 * any interesting requests and then jump to the real instruction 21240 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21241 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21242 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21243 * bail to the real handler if breakFlags==0. 21244 */ 21245 ldrb r3, [rSELF, #offThread_breakFlags] 21246 adrl lr, dvmAsmInstructionStart + (295 * 64) 21247 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21248 cmp r3, #0 21249 bxeq lr @ nothing to do - jump to real handler 21250 EXPORT_PC() 21251 mov r0, rPC @ arg0 21252 mov r1, rFP @ arg1 21253 mov r2, rSELF @ arg2 21254 b dvmCheckBefore @ (dPC,dFP,self) tail call 21255 21256 /* ------------------------------ */ 21257 .balign 64 21258 .L_ALT_OP_UNUSED_28FF: /* 0x128 */ 21259 /* File: armv5te/alt_stub.S */ 21260 /* 21261 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21262 * any interesting requests and then jump to the real instruction 21263 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21264 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21265 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21266 * bail to the real handler if breakFlags==0. 21267 */ 21268 ldrb r3, [rSELF, #offThread_breakFlags] 21269 adrl lr, dvmAsmInstructionStart + (296 * 64) 21270 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21271 cmp r3, #0 21272 bxeq lr @ nothing to do - jump to real handler 21273 EXPORT_PC() 21274 mov r0, rPC @ arg0 21275 mov r1, rFP @ arg1 21276 mov r2, rSELF @ arg2 21277 b dvmCheckBefore @ (dPC,dFP,self) tail call 21278 21279 /* ------------------------------ */ 21280 .balign 64 21281 .L_ALT_OP_UNUSED_29FF: /* 0x129 */ 21282 /* File: armv5te/alt_stub.S */ 21283 /* 21284 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21285 * any interesting requests and then jump to the real instruction 21286 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21287 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21288 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21289 * bail to the real handler if breakFlags==0. 21290 */ 21291 ldrb r3, [rSELF, #offThread_breakFlags] 21292 adrl lr, dvmAsmInstructionStart + (297 * 64) 21293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21294 cmp r3, #0 21295 bxeq lr @ nothing to do - jump to real handler 21296 EXPORT_PC() 21297 mov r0, rPC @ arg0 21298 mov r1, rFP @ arg1 21299 mov r2, rSELF @ arg2 21300 b dvmCheckBefore @ (dPC,dFP,self) tail call 21301 21302 /* ------------------------------ */ 21303 .balign 64 21304 .L_ALT_OP_UNUSED_2AFF: /* 0x12a */ 21305 /* File: armv5te/alt_stub.S */ 21306 /* 21307 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21308 * any interesting requests and then jump to the real instruction 21309 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21310 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21311 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21312 * bail to the real handler if breakFlags==0. 21313 */ 21314 ldrb r3, [rSELF, #offThread_breakFlags] 21315 adrl lr, dvmAsmInstructionStart + (298 * 64) 21316 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21317 cmp r3, #0 21318 bxeq lr @ nothing to do - jump to real handler 21319 EXPORT_PC() 21320 mov r0, rPC @ arg0 21321 mov r1, rFP @ arg1 21322 mov r2, rSELF @ arg2 21323 b dvmCheckBefore @ (dPC,dFP,self) tail call 21324 21325 /* ------------------------------ */ 21326 .balign 64 21327 .L_ALT_OP_UNUSED_2BFF: /* 0x12b */ 21328 /* File: armv5te/alt_stub.S */ 21329 /* 21330 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21331 * any interesting requests and then jump to the real instruction 21332 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21333 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21334 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21335 * bail to the real handler if breakFlags==0. 21336 */ 21337 ldrb r3, [rSELF, #offThread_breakFlags] 21338 adrl lr, dvmAsmInstructionStart + (299 * 64) 21339 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21340 cmp r3, #0 21341 bxeq lr @ nothing to do - jump to real handler 21342 EXPORT_PC() 21343 mov r0, rPC @ arg0 21344 mov r1, rFP @ arg1 21345 mov r2, rSELF @ arg2 21346 b dvmCheckBefore @ (dPC,dFP,self) tail call 21347 21348 /* ------------------------------ */ 21349 .balign 64 21350 .L_ALT_OP_UNUSED_2CFF: /* 0x12c */ 21351 /* File: armv5te/alt_stub.S */ 21352 /* 21353 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21354 * any interesting requests and then jump to the real instruction 21355 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21356 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21357 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21358 * bail to the real handler if breakFlags==0. 21359 */ 21360 ldrb r3, [rSELF, #offThread_breakFlags] 21361 adrl lr, dvmAsmInstructionStart + (300 * 64) 21362 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21363 cmp r3, #0 21364 bxeq lr @ nothing to do - jump to real handler 21365 EXPORT_PC() 21366 mov r0, rPC @ arg0 21367 mov r1, rFP @ arg1 21368 mov r2, rSELF @ arg2 21369 b dvmCheckBefore @ (dPC,dFP,self) tail call 21370 21371 /* ------------------------------ */ 21372 .balign 64 21373 .L_ALT_OP_UNUSED_2DFF: /* 0x12d */ 21374 /* File: armv5te/alt_stub.S */ 21375 /* 21376 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21377 * any interesting requests and then jump to the real instruction 21378 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21379 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21380 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21381 * bail to the real handler if breakFlags==0. 21382 */ 21383 ldrb r3, [rSELF, #offThread_breakFlags] 21384 adrl lr, dvmAsmInstructionStart + (301 * 64) 21385 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21386 cmp r3, #0 21387 bxeq lr @ nothing to do - jump to real handler 21388 EXPORT_PC() 21389 mov r0, rPC @ arg0 21390 mov r1, rFP @ arg1 21391 mov r2, rSELF @ arg2 21392 b dvmCheckBefore @ (dPC,dFP,self) tail call 21393 21394 /* ------------------------------ */ 21395 .balign 64 21396 .L_ALT_OP_UNUSED_2EFF: /* 0x12e */ 21397 /* File: armv5te/alt_stub.S */ 21398 /* 21399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21400 * any interesting requests and then jump to the real instruction 21401 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21402 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21404 * bail to the real handler if breakFlags==0. 21405 */ 21406 ldrb r3, [rSELF, #offThread_breakFlags] 21407 adrl lr, dvmAsmInstructionStart + (302 * 64) 21408 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21409 cmp r3, #0 21410 bxeq lr @ nothing to do - jump to real handler 21411 EXPORT_PC() 21412 mov r0, rPC @ arg0 21413 mov r1, rFP @ arg1 21414 mov r2, rSELF @ arg2 21415 b dvmCheckBefore @ (dPC,dFP,self) tail call 21416 21417 /* ------------------------------ */ 21418 .balign 64 21419 .L_ALT_OP_UNUSED_2FFF: /* 0x12f */ 21420 /* File: armv5te/alt_stub.S */ 21421 /* 21422 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21423 * any interesting requests and then jump to the real instruction 21424 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21425 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21426 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21427 * bail to the real handler if breakFlags==0. 21428 */ 21429 ldrb r3, [rSELF, #offThread_breakFlags] 21430 adrl lr, dvmAsmInstructionStart + (303 * 64) 21431 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21432 cmp r3, #0 21433 bxeq lr @ nothing to do - jump to real handler 21434 EXPORT_PC() 21435 mov r0, rPC @ arg0 21436 mov r1, rFP @ arg1 21437 mov r2, rSELF @ arg2 21438 b dvmCheckBefore @ (dPC,dFP,self) tail call 21439 21440 /* ------------------------------ */ 21441 .balign 64 21442 .L_ALT_OP_UNUSED_30FF: /* 0x130 */ 21443 /* File: armv5te/alt_stub.S */ 21444 /* 21445 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21446 * any interesting requests and then jump to the real instruction 21447 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21448 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21449 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21450 * bail to the real handler if breakFlags==0. 21451 */ 21452 ldrb r3, [rSELF, #offThread_breakFlags] 21453 adrl lr, dvmAsmInstructionStart + (304 * 64) 21454 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21455 cmp r3, #0 21456 bxeq lr @ nothing to do - jump to real handler 21457 EXPORT_PC() 21458 mov r0, rPC @ arg0 21459 mov r1, rFP @ arg1 21460 mov r2, rSELF @ arg2 21461 b dvmCheckBefore @ (dPC,dFP,self) tail call 21462 21463 /* ------------------------------ */ 21464 .balign 64 21465 .L_ALT_OP_UNUSED_31FF: /* 0x131 */ 21466 /* File: armv5te/alt_stub.S */ 21467 /* 21468 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21469 * any interesting requests and then jump to the real instruction 21470 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21471 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21472 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21473 * bail to the real handler if breakFlags==0. 21474 */ 21475 ldrb r3, [rSELF, #offThread_breakFlags] 21476 adrl lr, dvmAsmInstructionStart + (305 * 64) 21477 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21478 cmp r3, #0 21479 bxeq lr @ nothing to do - jump to real handler 21480 EXPORT_PC() 21481 mov r0, rPC @ arg0 21482 mov r1, rFP @ arg1 21483 mov r2, rSELF @ arg2 21484 b dvmCheckBefore @ (dPC,dFP,self) tail call 21485 21486 /* ------------------------------ */ 21487 .balign 64 21488 .L_ALT_OP_UNUSED_32FF: /* 0x132 */ 21489 /* File: armv5te/alt_stub.S */ 21490 /* 21491 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21492 * any interesting requests and then jump to the real instruction 21493 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21494 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21495 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21496 * bail to the real handler if breakFlags==0. 21497 */ 21498 ldrb r3, [rSELF, #offThread_breakFlags] 21499 adrl lr, dvmAsmInstructionStart + (306 * 64) 21500 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21501 cmp r3, #0 21502 bxeq lr @ nothing to do - jump to real handler 21503 EXPORT_PC() 21504 mov r0, rPC @ arg0 21505 mov r1, rFP @ arg1 21506 mov r2, rSELF @ arg2 21507 b dvmCheckBefore @ (dPC,dFP,self) tail call 21508 21509 /* ------------------------------ */ 21510 .balign 64 21511 .L_ALT_OP_UNUSED_33FF: /* 0x133 */ 21512 /* File: armv5te/alt_stub.S */ 21513 /* 21514 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21515 * any interesting requests and then jump to the real instruction 21516 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21517 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21518 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21519 * bail to the real handler if breakFlags==0. 21520 */ 21521 ldrb r3, [rSELF, #offThread_breakFlags] 21522 adrl lr, dvmAsmInstructionStart + (307 * 64) 21523 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21524 cmp r3, #0 21525 bxeq lr @ nothing to do - jump to real handler 21526 EXPORT_PC() 21527 mov r0, rPC @ arg0 21528 mov r1, rFP @ arg1 21529 mov r2, rSELF @ arg2 21530 b dvmCheckBefore @ (dPC,dFP,self) tail call 21531 21532 /* ------------------------------ */ 21533 .balign 64 21534 .L_ALT_OP_UNUSED_34FF: /* 0x134 */ 21535 /* File: armv5te/alt_stub.S */ 21536 /* 21537 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21538 * any interesting requests and then jump to the real instruction 21539 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21540 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21541 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21542 * bail to the real handler if breakFlags==0. 21543 */ 21544 ldrb r3, [rSELF, #offThread_breakFlags] 21545 adrl lr, dvmAsmInstructionStart + (308 * 64) 21546 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21547 cmp r3, #0 21548 bxeq lr @ nothing to do - jump to real handler 21549 EXPORT_PC() 21550 mov r0, rPC @ arg0 21551 mov r1, rFP @ arg1 21552 mov r2, rSELF @ arg2 21553 b dvmCheckBefore @ (dPC,dFP,self) tail call 21554 21555 /* ------------------------------ */ 21556 .balign 64 21557 .L_ALT_OP_UNUSED_35FF: /* 0x135 */ 21558 /* File: armv5te/alt_stub.S */ 21559 /* 21560 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21561 * any interesting requests and then jump to the real instruction 21562 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21563 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21564 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21565 * bail to the real handler if breakFlags==0. 21566 */ 21567 ldrb r3, [rSELF, #offThread_breakFlags] 21568 adrl lr, dvmAsmInstructionStart + (309 * 64) 21569 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21570 cmp r3, #0 21571 bxeq lr @ nothing to do - jump to real handler 21572 EXPORT_PC() 21573 mov r0, rPC @ arg0 21574 mov r1, rFP @ arg1 21575 mov r2, rSELF @ arg2 21576 b dvmCheckBefore @ (dPC,dFP,self) tail call 21577 21578 /* ------------------------------ */ 21579 .balign 64 21580 .L_ALT_OP_UNUSED_36FF: /* 0x136 */ 21581 /* File: armv5te/alt_stub.S */ 21582 /* 21583 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21584 * any interesting requests and then jump to the real instruction 21585 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21586 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21587 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21588 * bail to the real handler if breakFlags==0. 21589 */ 21590 ldrb r3, [rSELF, #offThread_breakFlags] 21591 adrl lr, dvmAsmInstructionStart + (310 * 64) 21592 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21593 cmp r3, #0 21594 bxeq lr @ nothing to do - jump to real handler 21595 EXPORT_PC() 21596 mov r0, rPC @ arg0 21597 mov r1, rFP @ arg1 21598 mov r2, rSELF @ arg2 21599 b dvmCheckBefore @ (dPC,dFP,self) tail call 21600 21601 /* ------------------------------ */ 21602 .balign 64 21603 .L_ALT_OP_UNUSED_37FF: /* 0x137 */ 21604 /* File: armv5te/alt_stub.S */ 21605 /* 21606 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21607 * any interesting requests and then jump to the real instruction 21608 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21609 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21610 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21611 * bail to the real handler if breakFlags==0. 21612 */ 21613 ldrb r3, [rSELF, #offThread_breakFlags] 21614 adrl lr, dvmAsmInstructionStart + (311 * 64) 21615 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21616 cmp r3, #0 21617 bxeq lr @ nothing to do - jump to real handler 21618 EXPORT_PC() 21619 mov r0, rPC @ arg0 21620 mov r1, rFP @ arg1 21621 mov r2, rSELF @ arg2 21622 b dvmCheckBefore @ (dPC,dFP,self) tail call 21623 21624 /* ------------------------------ */ 21625 .balign 64 21626 .L_ALT_OP_UNUSED_38FF: /* 0x138 */ 21627 /* File: armv5te/alt_stub.S */ 21628 /* 21629 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21630 * any interesting requests and then jump to the real instruction 21631 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21632 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21633 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21634 * bail to the real handler if breakFlags==0. 21635 */ 21636 ldrb r3, [rSELF, #offThread_breakFlags] 21637 adrl lr, dvmAsmInstructionStart + (312 * 64) 21638 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21639 cmp r3, #0 21640 bxeq lr @ nothing to do - jump to real handler 21641 EXPORT_PC() 21642 mov r0, rPC @ arg0 21643 mov r1, rFP @ arg1 21644 mov r2, rSELF @ arg2 21645 b dvmCheckBefore @ (dPC,dFP,self) tail call 21646 21647 /* ------------------------------ */ 21648 .balign 64 21649 .L_ALT_OP_UNUSED_39FF: /* 0x139 */ 21650 /* File: armv5te/alt_stub.S */ 21651 /* 21652 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21653 * any interesting requests and then jump to the real instruction 21654 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21655 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21656 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21657 * bail to the real handler if breakFlags==0. 21658 */ 21659 ldrb r3, [rSELF, #offThread_breakFlags] 21660 adrl lr, dvmAsmInstructionStart + (313 * 64) 21661 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21662 cmp r3, #0 21663 bxeq lr @ nothing to do - jump to real handler 21664 EXPORT_PC() 21665 mov r0, rPC @ arg0 21666 mov r1, rFP @ arg1 21667 mov r2, rSELF @ arg2 21668 b dvmCheckBefore @ (dPC,dFP,self) tail call 21669 21670 /* ------------------------------ */ 21671 .balign 64 21672 .L_ALT_OP_UNUSED_3AFF: /* 0x13a */ 21673 /* File: armv5te/alt_stub.S */ 21674 /* 21675 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21676 * any interesting requests and then jump to the real instruction 21677 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21678 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21679 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21680 * bail to the real handler if breakFlags==0. 21681 */ 21682 ldrb r3, [rSELF, #offThread_breakFlags] 21683 adrl lr, dvmAsmInstructionStart + (314 * 64) 21684 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21685 cmp r3, #0 21686 bxeq lr @ nothing to do - jump to real handler 21687 EXPORT_PC() 21688 mov r0, rPC @ arg0 21689 mov r1, rFP @ arg1 21690 mov r2, rSELF @ arg2 21691 b dvmCheckBefore @ (dPC,dFP,self) tail call 21692 21693 /* ------------------------------ */ 21694 .balign 64 21695 .L_ALT_OP_UNUSED_3BFF: /* 0x13b */ 21696 /* File: armv5te/alt_stub.S */ 21697 /* 21698 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21699 * any interesting requests and then jump to the real instruction 21700 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21701 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21702 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21703 * bail to the real handler if breakFlags==0. 21704 */ 21705 ldrb r3, [rSELF, #offThread_breakFlags] 21706 adrl lr, dvmAsmInstructionStart + (315 * 64) 21707 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21708 cmp r3, #0 21709 bxeq lr @ nothing to do - jump to real handler 21710 EXPORT_PC() 21711 mov r0, rPC @ arg0 21712 mov r1, rFP @ arg1 21713 mov r2, rSELF @ arg2 21714 b dvmCheckBefore @ (dPC,dFP,self) tail call 21715 21716 /* ------------------------------ */ 21717 .balign 64 21718 .L_ALT_OP_UNUSED_3CFF: /* 0x13c */ 21719 /* File: armv5te/alt_stub.S */ 21720 /* 21721 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21722 * any interesting requests and then jump to the real instruction 21723 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21724 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21725 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21726 * bail to the real handler if breakFlags==0. 21727 */ 21728 ldrb r3, [rSELF, #offThread_breakFlags] 21729 adrl lr, dvmAsmInstructionStart + (316 * 64) 21730 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21731 cmp r3, #0 21732 bxeq lr @ nothing to do - jump to real handler 21733 EXPORT_PC() 21734 mov r0, rPC @ arg0 21735 mov r1, rFP @ arg1 21736 mov r2, rSELF @ arg2 21737 b dvmCheckBefore @ (dPC,dFP,self) tail call 21738 21739 /* ------------------------------ */ 21740 .balign 64 21741 .L_ALT_OP_UNUSED_3DFF: /* 0x13d */ 21742 /* File: armv5te/alt_stub.S */ 21743 /* 21744 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21745 * any interesting requests and then jump to the real instruction 21746 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21747 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21748 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21749 * bail to the real handler if breakFlags==0. 21750 */ 21751 ldrb r3, [rSELF, #offThread_breakFlags] 21752 adrl lr, dvmAsmInstructionStart + (317 * 64) 21753 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21754 cmp r3, #0 21755 bxeq lr @ nothing to do - jump to real handler 21756 EXPORT_PC() 21757 mov r0, rPC @ arg0 21758 mov r1, rFP @ arg1 21759 mov r2, rSELF @ arg2 21760 b dvmCheckBefore @ (dPC,dFP,self) tail call 21761 21762 /* ------------------------------ */ 21763 .balign 64 21764 .L_ALT_OP_UNUSED_3EFF: /* 0x13e */ 21765 /* File: armv5te/alt_stub.S */ 21766 /* 21767 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21768 * any interesting requests and then jump to the real instruction 21769 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21770 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21771 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21772 * bail to the real handler if breakFlags==0. 21773 */ 21774 ldrb r3, [rSELF, #offThread_breakFlags] 21775 adrl lr, dvmAsmInstructionStart + (318 * 64) 21776 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21777 cmp r3, #0 21778 bxeq lr @ nothing to do - jump to real handler 21779 EXPORT_PC() 21780 mov r0, rPC @ arg0 21781 mov r1, rFP @ arg1 21782 mov r2, rSELF @ arg2 21783 b dvmCheckBefore @ (dPC,dFP,self) tail call 21784 21785 /* ------------------------------ */ 21786 .balign 64 21787 .L_ALT_OP_UNUSED_3FFF: /* 0x13f */ 21788 /* File: armv5te/alt_stub.S */ 21789 /* 21790 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21791 * any interesting requests and then jump to the real instruction 21792 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21793 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21794 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21795 * bail to the real handler if breakFlags==0. 21796 */ 21797 ldrb r3, [rSELF, #offThread_breakFlags] 21798 adrl lr, dvmAsmInstructionStart + (319 * 64) 21799 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21800 cmp r3, #0 21801 bxeq lr @ nothing to do - jump to real handler 21802 EXPORT_PC() 21803 mov r0, rPC @ arg0 21804 mov r1, rFP @ arg1 21805 mov r2, rSELF @ arg2 21806 b dvmCheckBefore @ (dPC,dFP,self) tail call 21807 21808 /* ------------------------------ */ 21809 .balign 64 21810 .L_ALT_OP_UNUSED_40FF: /* 0x140 */ 21811 /* File: armv5te/alt_stub.S */ 21812 /* 21813 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21814 * any interesting requests and then jump to the real instruction 21815 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21816 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21817 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21818 * bail to the real handler if breakFlags==0. 21819 */ 21820 ldrb r3, [rSELF, #offThread_breakFlags] 21821 adrl lr, dvmAsmInstructionStart + (320 * 64) 21822 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21823 cmp r3, #0 21824 bxeq lr @ nothing to do - jump to real handler 21825 EXPORT_PC() 21826 mov r0, rPC @ arg0 21827 mov r1, rFP @ arg1 21828 mov r2, rSELF @ arg2 21829 b dvmCheckBefore @ (dPC,dFP,self) tail call 21830 21831 /* ------------------------------ */ 21832 .balign 64 21833 .L_ALT_OP_UNUSED_41FF: /* 0x141 */ 21834 /* File: armv5te/alt_stub.S */ 21835 /* 21836 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21837 * any interesting requests and then jump to the real instruction 21838 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21839 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21840 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21841 * bail to the real handler if breakFlags==0. 21842 */ 21843 ldrb r3, [rSELF, #offThread_breakFlags] 21844 adrl lr, dvmAsmInstructionStart + (321 * 64) 21845 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21846 cmp r3, #0 21847 bxeq lr @ nothing to do - jump to real handler 21848 EXPORT_PC() 21849 mov r0, rPC @ arg0 21850 mov r1, rFP @ arg1 21851 mov r2, rSELF @ arg2 21852 b dvmCheckBefore @ (dPC,dFP,self) tail call 21853 21854 /* ------------------------------ */ 21855 .balign 64 21856 .L_ALT_OP_UNUSED_42FF: /* 0x142 */ 21857 /* File: armv5te/alt_stub.S */ 21858 /* 21859 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21860 * any interesting requests and then jump to the real instruction 21861 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21862 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21863 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21864 * bail to the real handler if breakFlags==0. 21865 */ 21866 ldrb r3, [rSELF, #offThread_breakFlags] 21867 adrl lr, dvmAsmInstructionStart + (322 * 64) 21868 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21869 cmp r3, #0 21870 bxeq lr @ nothing to do - jump to real handler 21871 EXPORT_PC() 21872 mov r0, rPC @ arg0 21873 mov r1, rFP @ arg1 21874 mov r2, rSELF @ arg2 21875 b dvmCheckBefore @ (dPC,dFP,self) tail call 21876 21877 /* ------------------------------ */ 21878 .balign 64 21879 .L_ALT_OP_UNUSED_43FF: /* 0x143 */ 21880 /* File: armv5te/alt_stub.S */ 21881 /* 21882 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21883 * any interesting requests and then jump to the real instruction 21884 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21885 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21886 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21887 * bail to the real handler if breakFlags==0. 21888 */ 21889 ldrb r3, [rSELF, #offThread_breakFlags] 21890 adrl lr, dvmAsmInstructionStart + (323 * 64) 21891 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21892 cmp r3, #0 21893 bxeq lr @ nothing to do - jump to real handler 21894 EXPORT_PC() 21895 mov r0, rPC @ arg0 21896 mov r1, rFP @ arg1 21897 mov r2, rSELF @ arg2 21898 b dvmCheckBefore @ (dPC,dFP,self) tail call 21899 21900 /* ------------------------------ */ 21901 .balign 64 21902 .L_ALT_OP_UNUSED_44FF: /* 0x144 */ 21903 /* File: armv5te/alt_stub.S */ 21904 /* 21905 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21906 * any interesting requests and then jump to the real instruction 21907 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21908 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21909 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21910 * bail to the real handler if breakFlags==0. 21911 */ 21912 ldrb r3, [rSELF, #offThread_breakFlags] 21913 adrl lr, dvmAsmInstructionStart + (324 * 64) 21914 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21915 cmp r3, #0 21916 bxeq lr @ nothing to do - jump to real handler 21917 EXPORT_PC() 21918 mov r0, rPC @ arg0 21919 mov r1, rFP @ arg1 21920 mov r2, rSELF @ arg2 21921 b dvmCheckBefore @ (dPC,dFP,self) tail call 21922 21923 /* ------------------------------ */ 21924 .balign 64 21925 .L_ALT_OP_UNUSED_45FF: /* 0x145 */ 21926 /* File: armv5te/alt_stub.S */ 21927 /* 21928 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21929 * any interesting requests and then jump to the real instruction 21930 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21931 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21932 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21933 * bail to the real handler if breakFlags==0. 21934 */ 21935 ldrb r3, [rSELF, #offThread_breakFlags] 21936 adrl lr, dvmAsmInstructionStart + (325 * 64) 21937 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21938 cmp r3, #0 21939 bxeq lr @ nothing to do - jump to real handler 21940 EXPORT_PC() 21941 mov r0, rPC @ arg0 21942 mov r1, rFP @ arg1 21943 mov r2, rSELF @ arg2 21944 b dvmCheckBefore @ (dPC,dFP,self) tail call 21945 21946 /* ------------------------------ */ 21947 .balign 64 21948 .L_ALT_OP_UNUSED_46FF: /* 0x146 */ 21949 /* File: armv5te/alt_stub.S */ 21950 /* 21951 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21952 * any interesting requests and then jump to the real instruction 21953 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21954 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21955 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21956 * bail to the real handler if breakFlags==0. 21957 */ 21958 ldrb r3, [rSELF, #offThread_breakFlags] 21959 adrl lr, dvmAsmInstructionStart + (326 * 64) 21960 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21961 cmp r3, #0 21962 bxeq lr @ nothing to do - jump to real handler 21963 EXPORT_PC() 21964 mov r0, rPC @ arg0 21965 mov r1, rFP @ arg1 21966 mov r2, rSELF @ arg2 21967 b dvmCheckBefore @ (dPC,dFP,self) tail call 21968 21969 /* ------------------------------ */ 21970 .balign 64 21971 .L_ALT_OP_UNUSED_47FF: /* 0x147 */ 21972 /* File: armv5te/alt_stub.S */ 21973 /* 21974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21975 * any interesting requests and then jump to the real instruction 21976 * handler. Note that the call to dvmCheckBefore is done as a tail call. 21977 * rIBASE updates won't be seen until a refresh, and we can tell we have a 21978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 21979 * bail to the real handler if breakFlags==0. 21980 */ 21981 ldrb r3, [rSELF, #offThread_breakFlags] 21982 adrl lr, dvmAsmInstructionStart + (327 * 64) 21983 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 21984 cmp r3, #0 21985 bxeq lr @ nothing to do - jump to real handler 21986 EXPORT_PC() 21987 mov r0, rPC @ arg0 21988 mov r1, rFP @ arg1 21989 mov r2, rSELF @ arg2 21990 b dvmCheckBefore @ (dPC,dFP,self) tail call 21991 21992 /* ------------------------------ */ 21993 .balign 64 21994 .L_ALT_OP_UNUSED_48FF: /* 0x148 */ 21995 /* File: armv5te/alt_stub.S */ 21996 /* 21997 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 21998 * any interesting requests and then jump to the real instruction 21999 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22000 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22001 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22002 * bail to the real handler if breakFlags==0. 22003 */ 22004 ldrb r3, [rSELF, #offThread_breakFlags] 22005 adrl lr, dvmAsmInstructionStart + (328 * 64) 22006 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22007 cmp r3, #0 22008 bxeq lr @ nothing to do - jump to real handler 22009 EXPORT_PC() 22010 mov r0, rPC @ arg0 22011 mov r1, rFP @ arg1 22012 mov r2, rSELF @ arg2 22013 b dvmCheckBefore @ (dPC,dFP,self) tail call 22014 22015 /* ------------------------------ */ 22016 .balign 64 22017 .L_ALT_OP_UNUSED_49FF: /* 0x149 */ 22018 /* File: armv5te/alt_stub.S */ 22019 /* 22020 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22021 * any interesting requests and then jump to the real instruction 22022 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22023 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22024 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22025 * bail to the real handler if breakFlags==0. 22026 */ 22027 ldrb r3, [rSELF, #offThread_breakFlags] 22028 adrl lr, dvmAsmInstructionStart + (329 * 64) 22029 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22030 cmp r3, #0 22031 bxeq lr @ nothing to do - jump to real handler 22032 EXPORT_PC() 22033 mov r0, rPC @ arg0 22034 mov r1, rFP @ arg1 22035 mov r2, rSELF @ arg2 22036 b dvmCheckBefore @ (dPC,dFP,self) tail call 22037 22038 /* ------------------------------ */ 22039 .balign 64 22040 .L_ALT_OP_UNUSED_4AFF: /* 0x14a */ 22041 /* File: armv5te/alt_stub.S */ 22042 /* 22043 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22044 * any interesting requests and then jump to the real instruction 22045 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22046 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22047 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22048 * bail to the real handler if breakFlags==0. 22049 */ 22050 ldrb r3, [rSELF, #offThread_breakFlags] 22051 adrl lr, dvmAsmInstructionStart + (330 * 64) 22052 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22053 cmp r3, #0 22054 bxeq lr @ nothing to do - jump to real handler 22055 EXPORT_PC() 22056 mov r0, rPC @ arg0 22057 mov r1, rFP @ arg1 22058 mov r2, rSELF @ arg2 22059 b dvmCheckBefore @ (dPC,dFP,self) tail call 22060 22061 /* ------------------------------ */ 22062 .balign 64 22063 .L_ALT_OP_UNUSED_4BFF: /* 0x14b */ 22064 /* File: armv5te/alt_stub.S */ 22065 /* 22066 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22067 * any interesting requests and then jump to the real instruction 22068 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22069 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22070 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22071 * bail to the real handler if breakFlags==0. 22072 */ 22073 ldrb r3, [rSELF, #offThread_breakFlags] 22074 adrl lr, dvmAsmInstructionStart + (331 * 64) 22075 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22076 cmp r3, #0 22077 bxeq lr @ nothing to do - jump to real handler 22078 EXPORT_PC() 22079 mov r0, rPC @ arg0 22080 mov r1, rFP @ arg1 22081 mov r2, rSELF @ arg2 22082 b dvmCheckBefore @ (dPC,dFP,self) tail call 22083 22084 /* ------------------------------ */ 22085 .balign 64 22086 .L_ALT_OP_UNUSED_4CFF: /* 0x14c */ 22087 /* File: armv5te/alt_stub.S */ 22088 /* 22089 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22090 * any interesting requests and then jump to the real instruction 22091 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22092 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22093 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22094 * bail to the real handler if breakFlags==0. 22095 */ 22096 ldrb r3, [rSELF, #offThread_breakFlags] 22097 adrl lr, dvmAsmInstructionStart + (332 * 64) 22098 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22099 cmp r3, #0 22100 bxeq lr @ nothing to do - jump to real handler 22101 EXPORT_PC() 22102 mov r0, rPC @ arg0 22103 mov r1, rFP @ arg1 22104 mov r2, rSELF @ arg2 22105 b dvmCheckBefore @ (dPC,dFP,self) tail call 22106 22107 /* ------------------------------ */ 22108 .balign 64 22109 .L_ALT_OP_UNUSED_4DFF: /* 0x14d */ 22110 /* File: armv5te/alt_stub.S */ 22111 /* 22112 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22113 * any interesting requests and then jump to the real instruction 22114 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22115 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22116 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22117 * bail to the real handler if breakFlags==0. 22118 */ 22119 ldrb r3, [rSELF, #offThread_breakFlags] 22120 adrl lr, dvmAsmInstructionStart + (333 * 64) 22121 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22122 cmp r3, #0 22123 bxeq lr @ nothing to do - jump to real handler 22124 EXPORT_PC() 22125 mov r0, rPC @ arg0 22126 mov r1, rFP @ arg1 22127 mov r2, rSELF @ arg2 22128 b dvmCheckBefore @ (dPC,dFP,self) tail call 22129 22130 /* ------------------------------ */ 22131 .balign 64 22132 .L_ALT_OP_UNUSED_4EFF: /* 0x14e */ 22133 /* File: armv5te/alt_stub.S */ 22134 /* 22135 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22136 * any interesting requests and then jump to the real instruction 22137 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22138 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22139 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22140 * bail to the real handler if breakFlags==0. 22141 */ 22142 ldrb r3, [rSELF, #offThread_breakFlags] 22143 adrl lr, dvmAsmInstructionStart + (334 * 64) 22144 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22145 cmp r3, #0 22146 bxeq lr @ nothing to do - jump to real handler 22147 EXPORT_PC() 22148 mov r0, rPC @ arg0 22149 mov r1, rFP @ arg1 22150 mov r2, rSELF @ arg2 22151 b dvmCheckBefore @ (dPC,dFP,self) tail call 22152 22153 /* ------------------------------ */ 22154 .balign 64 22155 .L_ALT_OP_UNUSED_4FFF: /* 0x14f */ 22156 /* File: armv5te/alt_stub.S */ 22157 /* 22158 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22159 * any interesting requests and then jump to the real instruction 22160 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22161 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22162 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22163 * bail to the real handler if breakFlags==0. 22164 */ 22165 ldrb r3, [rSELF, #offThread_breakFlags] 22166 adrl lr, dvmAsmInstructionStart + (335 * 64) 22167 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22168 cmp r3, #0 22169 bxeq lr @ nothing to do - jump to real handler 22170 EXPORT_PC() 22171 mov r0, rPC @ arg0 22172 mov r1, rFP @ arg1 22173 mov r2, rSELF @ arg2 22174 b dvmCheckBefore @ (dPC,dFP,self) tail call 22175 22176 /* ------------------------------ */ 22177 .balign 64 22178 .L_ALT_OP_UNUSED_50FF: /* 0x150 */ 22179 /* File: armv5te/alt_stub.S */ 22180 /* 22181 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22182 * any interesting requests and then jump to the real instruction 22183 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22184 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22185 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22186 * bail to the real handler if breakFlags==0. 22187 */ 22188 ldrb r3, [rSELF, #offThread_breakFlags] 22189 adrl lr, dvmAsmInstructionStart + (336 * 64) 22190 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22191 cmp r3, #0 22192 bxeq lr @ nothing to do - jump to real handler 22193 EXPORT_PC() 22194 mov r0, rPC @ arg0 22195 mov r1, rFP @ arg1 22196 mov r2, rSELF @ arg2 22197 b dvmCheckBefore @ (dPC,dFP,self) tail call 22198 22199 /* ------------------------------ */ 22200 .balign 64 22201 .L_ALT_OP_UNUSED_51FF: /* 0x151 */ 22202 /* File: armv5te/alt_stub.S */ 22203 /* 22204 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22205 * any interesting requests and then jump to the real instruction 22206 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22207 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22208 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22209 * bail to the real handler if breakFlags==0. 22210 */ 22211 ldrb r3, [rSELF, #offThread_breakFlags] 22212 adrl lr, dvmAsmInstructionStart + (337 * 64) 22213 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22214 cmp r3, #0 22215 bxeq lr @ nothing to do - jump to real handler 22216 EXPORT_PC() 22217 mov r0, rPC @ arg0 22218 mov r1, rFP @ arg1 22219 mov r2, rSELF @ arg2 22220 b dvmCheckBefore @ (dPC,dFP,self) tail call 22221 22222 /* ------------------------------ */ 22223 .balign 64 22224 .L_ALT_OP_UNUSED_52FF: /* 0x152 */ 22225 /* File: armv5te/alt_stub.S */ 22226 /* 22227 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22228 * any interesting requests and then jump to the real instruction 22229 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22230 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22231 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22232 * bail to the real handler if breakFlags==0. 22233 */ 22234 ldrb r3, [rSELF, #offThread_breakFlags] 22235 adrl lr, dvmAsmInstructionStart + (338 * 64) 22236 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22237 cmp r3, #0 22238 bxeq lr @ nothing to do - jump to real handler 22239 EXPORT_PC() 22240 mov r0, rPC @ arg0 22241 mov r1, rFP @ arg1 22242 mov r2, rSELF @ arg2 22243 b dvmCheckBefore @ (dPC,dFP,self) tail call 22244 22245 /* ------------------------------ */ 22246 .balign 64 22247 .L_ALT_OP_UNUSED_53FF: /* 0x153 */ 22248 /* File: armv5te/alt_stub.S */ 22249 /* 22250 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22251 * any interesting requests and then jump to the real instruction 22252 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22253 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22254 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22255 * bail to the real handler if breakFlags==0. 22256 */ 22257 ldrb r3, [rSELF, #offThread_breakFlags] 22258 adrl lr, dvmAsmInstructionStart + (339 * 64) 22259 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22260 cmp r3, #0 22261 bxeq lr @ nothing to do - jump to real handler 22262 EXPORT_PC() 22263 mov r0, rPC @ arg0 22264 mov r1, rFP @ arg1 22265 mov r2, rSELF @ arg2 22266 b dvmCheckBefore @ (dPC,dFP,self) tail call 22267 22268 /* ------------------------------ */ 22269 .balign 64 22270 .L_ALT_OP_UNUSED_54FF: /* 0x154 */ 22271 /* File: armv5te/alt_stub.S */ 22272 /* 22273 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22274 * any interesting requests and then jump to the real instruction 22275 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22276 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22277 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22278 * bail to the real handler if breakFlags==0. 22279 */ 22280 ldrb r3, [rSELF, #offThread_breakFlags] 22281 adrl lr, dvmAsmInstructionStart + (340 * 64) 22282 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22283 cmp r3, #0 22284 bxeq lr @ nothing to do - jump to real handler 22285 EXPORT_PC() 22286 mov r0, rPC @ arg0 22287 mov r1, rFP @ arg1 22288 mov r2, rSELF @ arg2 22289 b dvmCheckBefore @ (dPC,dFP,self) tail call 22290 22291 /* ------------------------------ */ 22292 .balign 64 22293 .L_ALT_OP_UNUSED_55FF: /* 0x155 */ 22294 /* File: armv5te/alt_stub.S */ 22295 /* 22296 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22297 * any interesting requests and then jump to the real instruction 22298 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22299 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22300 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22301 * bail to the real handler if breakFlags==0. 22302 */ 22303 ldrb r3, [rSELF, #offThread_breakFlags] 22304 adrl lr, dvmAsmInstructionStart + (341 * 64) 22305 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22306 cmp r3, #0 22307 bxeq lr @ nothing to do - jump to real handler 22308 EXPORT_PC() 22309 mov r0, rPC @ arg0 22310 mov r1, rFP @ arg1 22311 mov r2, rSELF @ arg2 22312 b dvmCheckBefore @ (dPC,dFP,self) tail call 22313 22314 /* ------------------------------ */ 22315 .balign 64 22316 .L_ALT_OP_UNUSED_56FF: /* 0x156 */ 22317 /* File: armv5te/alt_stub.S */ 22318 /* 22319 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22320 * any interesting requests and then jump to the real instruction 22321 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22322 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22323 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22324 * bail to the real handler if breakFlags==0. 22325 */ 22326 ldrb r3, [rSELF, #offThread_breakFlags] 22327 adrl lr, dvmAsmInstructionStart + (342 * 64) 22328 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22329 cmp r3, #0 22330 bxeq lr @ nothing to do - jump to real handler 22331 EXPORT_PC() 22332 mov r0, rPC @ arg0 22333 mov r1, rFP @ arg1 22334 mov r2, rSELF @ arg2 22335 b dvmCheckBefore @ (dPC,dFP,self) tail call 22336 22337 /* ------------------------------ */ 22338 .balign 64 22339 .L_ALT_OP_UNUSED_57FF: /* 0x157 */ 22340 /* File: armv5te/alt_stub.S */ 22341 /* 22342 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22343 * any interesting requests and then jump to the real instruction 22344 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22345 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22346 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22347 * bail to the real handler if breakFlags==0. 22348 */ 22349 ldrb r3, [rSELF, #offThread_breakFlags] 22350 adrl lr, dvmAsmInstructionStart + (343 * 64) 22351 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22352 cmp r3, #0 22353 bxeq lr @ nothing to do - jump to real handler 22354 EXPORT_PC() 22355 mov r0, rPC @ arg0 22356 mov r1, rFP @ arg1 22357 mov r2, rSELF @ arg2 22358 b dvmCheckBefore @ (dPC,dFP,self) tail call 22359 22360 /* ------------------------------ */ 22361 .balign 64 22362 .L_ALT_OP_UNUSED_58FF: /* 0x158 */ 22363 /* File: armv5te/alt_stub.S */ 22364 /* 22365 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22366 * any interesting requests and then jump to the real instruction 22367 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22368 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22369 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22370 * bail to the real handler if breakFlags==0. 22371 */ 22372 ldrb r3, [rSELF, #offThread_breakFlags] 22373 adrl lr, dvmAsmInstructionStart + (344 * 64) 22374 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22375 cmp r3, #0 22376 bxeq lr @ nothing to do - jump to real handler 22377 EXPORT_PC() 22378 mov r0, rPC @ arg0 22379 mov r1, rFP @ arg1 22380 mov r2, rSELF @ arg2 22381 b dvmCheckBefore @ (dPC,dFP,self) tail call 22382 22383 /* ------------------------------ */ 22384 .balign 64 22385 .L_ALT_OP_UNUSED_59FF: /* 0x159 */ 22386 /* File: armv5te/alt_stub.S */ 22387 /* 22388 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22389 * any interesting requests and then jump to the real instruction 22390 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22391 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22392 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22393 * bail to the real handler if breakFlags==0. 22394 */ 22395 ldrb r3, [rSELF, #offThread_breakFlags] 22396 adrl lr, dvmAsmInstructionStart + (345 * 64) 22397 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22398 cmp r3, #0 22399 bxeq lr @ nothing to do - jump to real handler 22400 EXPORT_PC() 22401 mov r0, rPC @ arg0 22402 mov r1, rFP @ arg1 22403 mov r2, rSELF @ arg2 22404 b dvmCheckBefore @ (dPC,dFP,self) tail call 22405 22406 /* ------------------------------ */ 22407 .balign 64 22408 .L_ALT_OP_UNUSED_5AFF: /* 0x15a */ 22409 /* File: armv5te/alt_stub.S */ 22410 /* 22411 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22412 * any interesting requests and then jump to the real instruction 22413 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22414 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22415 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22416 * bail to the real handler if breakFlags==0. 22417 */ 22418 ldrb r3, [rSELF, #offThread_breakFlags] 22419 adrl lr, dvmAsmInstructionStart + (346 * 64) 22420 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22421 cmp r3, #0 22422 bxeq lr @ nothing to do - jump to real handler 22423 EXPORT_PC() 22424 mov r0, rPC @ arg0 22425 mov r1, rFP @ arg1 22426 mov r2, rSELF @ arg2 22427 b dvmCheckBefore @ (dPC,dFP,self) tail call 22428 22429 /* ------------------------------ */ 22430 .balign 64 22431 .L_ALT_OP_UNUSED_5BFF: /* 0x15b */ 22432 /* File: armv5te/alt_stub.S */ 22433 /* 22434 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22435 * any interesting requests and then jump to the real instruction 22436 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22437 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22438 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22439 * bail to the real handler if breakFlags==0. 22440 */ 22441 ldrb r3, [rSELF, #offThread_breakFlags] 22442 adrl lr, dvmAsmInstructionStart + (347 * 64) 22443 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22444 cmp r3, #0 22445 bxeq lr @ nothing to do - jump to real handler 22446 EXPORT_PC() 22447 mov r0, rPC @ arg0 22448 mov r1, rFP @ arg1 22449 mov r2, rSELF @ arg2 22450 b dvmCheckBefore @ (dPC,dFP,self) tail call 22451 22452 /* ------------------------------ */ 22453 .balign 64 22454 .L_ALT_OP_UNUSED_5CFF: /* 0x15c */ 22455 /* File: armv5te/alt_stub.S */ 22456 /* 22457 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22458 * any interesting requests and then jump to the real instruction 22459 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22460 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22461 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22462 * bail to the real handler if breakFlags==0. 22463 */ 22464 ldrb r3, [rSELF, #offThread_breakFlags] 22465 adrl lr, dvmAsmInstructionStart + (348 * 64) 22466 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22467 cmp r3, #0 22468 bxeq lr @ nothing to do - jump to real handler 22469 EXPORT_PC() 22470 mov r0, rPC @ arg0 22471 mov r1, rFP @ arg1 22472 mov r2, rSELF @ arg2 22473 b dvmCheckBefore @ (dPC,dFP,self) tail call 22474 22475 /* ------------------------------ */ 22476 .balign 64 22477 .L_ALT_OP_UNUSED_5DFF: /* 0x15d */ 22478 /* File: armv5te/alt_stub.S */ 22479 /* 22480 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22481 * any interesting requests and then jump to the real instruction 22482 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22483 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22484 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22485 * bail to the real handler if breakFlags==0. 22486 */ 22487 ldrb r3, [rSELF, #offThread_breakFlags] 22488 adrl lr, dvmAsmInstructionStart + (349 * 64) 22489 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22490 cmp r3, #0 22491 bxeq lr @ nothing to do - jump to real handler 22492 EXPORT_PC() 22493 mov r0, rPC @ arg0 22494 mov r1, rFP @ arg1 22495 mov r2, rSELF @ arg2 22496 b dvmCheckBefore @ (dPC,dFP,self) tail call 22497 22498 /* ------------------------------ */ 22499 .balign 64 22500 .L_ALT_OP_UNUSED_5EFF: /* 0x15e */ 22501 /* File: armv5te/alt_stub.S */ 22502 /* 22503 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22504 * any interesting requests and then jump to the real instruction 22505 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22506 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22507 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22508 * bail to the real handler if breakFlags==0. 22509 */ 22510 ldrb r3, [rSELF, #offThread_breakFlags] 22511 adrl lr, dvmAsmInstructionStart + (350 * 64) 22512 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22513 cmp r3, #0 22514 bxeq lr @ nothing to do - jump to real handler 22515 EXPORT_PC() 22516 mov r0, rPC @ arg0 22517 mov r1, rFP @ arg1 22518 mov r2, rSELF @ arg2 22519 b dvmCheckBefore @ (dPC,dFP,self) tail call 22520 22521 /* ------------------------------ */ 22522 .balign 64 22523 .L_ALT_OP_UNUSED_5FFF: /* 0x15f */ 22524 /* File: armv5te/alt_stub.S */ 22525 /* 22526 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22527 * any interesting requests and then jump to the real instruction 22528 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22529 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22530 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22531 * bail to the real handler if breakFlags==0. 22532 */ 22533 ldrb r3, [rSELF, #offThread_breakFlags] 22534 adrl lr, dvmAsmInstructionStart + (351 * 64) 22535 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22536 cmp r3, #0 22537 bxeq lr @ nothing to do - jump to real handler 22538 EXPORT_PC() 22539 mov r0, rPC @ arg0 22540 mov r1, rFP @ arg1 22541 mov r2, rSELF @ arg2 22542 b dvmCheckBefore @ (dPC,dFP,self) tail call 22543 22544 /* ------------------------------ */ 22545 .balign 64 22546 .L_ALT_OP_UNUSED_60FF: /* 0x160 */ 22547 /* File: armv5te/alt_stub.S */ 22548 /* 22549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22550 * any interesting requests and then jump to the real instruction 22551 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22552 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22554 * bail to the real handler if breakFlags==0. 22555 */ 22556 ldrb r3, [rSELF, #offThread_breakFlags] 22557 adrl lr, dvmAsmInstructionStart + (352 * 64) 22558 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22559 cmp r3, #0 22560 bxeq lr @ nothing to do - jump to real handler 22561 EXPORT_PC() 22562 mov r0, rPC @ arg0 22563 mov r1, rFP @ arg1 22564 mov r2, rSELF @ arg2 22565 b dvmCheckBefore @ (dPC,dFP,self) tail call 22566 22567 /* ------------------------------ */ 22568 .balign 64 22569 .L_ALT_OP_UNUSED_61FF: /* 0x161 */ 22570 /* File: armv5te/alt_stub.S */ 22571 /* 22572 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22573 * any interesting requests and then jump to the real instruction 22574 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22575 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22576 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22577 * bail to the real handler if breakFlags==0. 22578 */ 22579 ldrb r3, [rSELF, #offThread_breakFlags] 22580 adrl lr, dvmAsmInstructionStart + (353 * 64) 22581 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22582 cmp r3, #0 22583 bxeq lr @ nothing to do - jump to real handler 22584 EXPORT_PC() 22585 mov r0, rPC @ arg0 22586 mov r1, rFP @ arg1 22587 mov r2, rSELF @ arg2 22588 b dvmCheckBefore @ (dPC,dFP,self) tail call 22589 22590 /* ------------------------------ */ 22591 .balign 64 22592 .L_ALT_OP_UNUSED_62FF: /* 0x162 */ 22593 /* File: armv5te/alt_stub.S */ 22594 /* 22595 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22596 * any interesting requests and then jump to the real instruction 22597 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22598 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22599 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22600 * bail to the real handler if breakFlags==0. 22601 */ 22602 ldrb r3, [rSELF, #offThread_breakFlags] 22603 adrl lr, dvmAsmInstructionStart + (354 * 64) 22604 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22605 cmp r3, #0 22606 bxeq lr @ nothing to do - jump to real handler 22607 EXPORT_PC() 22608 mov r0, rPC @ arg0 22609 mov r1, rFP @ arg1 22610 mov r2, rSELF @ arg2 22611 b dvmCheckBefore @ (dPC,dFP,self) tail call 22612 22613 /* ------------------------------ */ 22614 .balign 64 22615 .L_ALT_OP_UNUSED_63FF: /* 0x163 */ 22616 /* File: armv5te/alt_stub.S */ 22617 /* 22618 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22619 * any interesting requests and then jump to the real instruction 22620 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22621 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22622 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22623 * bail to the real handler if breakFlags==0. 22624 */ 22625 ldrb r3, [rSELF, #offThread_breakFlags] 22626 adrl lr, dvmAsmInstructionStart + (355 * 64) 22627 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22628 cmp r3, #0 22629 bxeq lr @ nothing to do - jump to real handler 22630 EXPORT_PC() 22631 mov r0, rPC @ arg0 22632 mov r1, rFP @ arg1 22633 mov r2, rSELF @ arg2 22634 b dvmCheckBefore @ (dPC,dFP,self) tail call 22635 22636 /* ------------------------------ */ 22637 .balign 64 22638 .L_ALT_OP_UNUSED_64FF: /* 0x164 */ 22639 /* File: armv5te/alt_stub.S */ 22640 /* 22641 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22642 * any interesting requests and then jump to the real instruction 22643 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22644 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22645 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22646 * bail to the real handler if breakFlags==0. 22647 */ 22648 ldrb r3, [rSELF, #offThread_breakFlags] 22649 adrl lr, dvmAsmInstructionStart + (356 * 64) 22650 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22651 cmp r3, #0 22652 bxeq lr @ nothing to do - jump to real handler 22653 EXPORT_PC() 22654 mov r0, rPC @ arg0 22655 mov r1, rFP @ arg1 22656 mov r2, rSELF @ arg2 22657 b dvmCheckBefore @ (dPC,dFP,self) tail call 22658 22659 /* ------------------------------ */ 22660 .balign 64 22661 .L_ALT_OP_UNUSED_65FF: /* 0x165 */ 22662 /* File: armv5te/alt_stub.S */ 22663 /* 22664 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22665 * any interesting requests and then jump to the real instruction 22666 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22667 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22668 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22669 * bail to the real handler if breakFlags==0. 22670 */ 22671 ldrb r3, [rSELF, #offThread_breakFlags] 22672 adrl lr, dvmAsmInstructionStart + (357 * 64) 22673 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22674 cmp r3, #0 22675 bxeq lr @ nothing to do - jump to real handler 22676 EXPORT_PC() 22677 mov r0, rPC @ arg0 22678 mov r1, rFP @ arg1 22679 mov r2, rSELF @ arg2 22680 b dvmCheckBefore @ (dPC,dFP,self) tail call 22681 22682 /* ------------------------------ */ 22683 .balign 64 22684 .L_ALT_OP_UNUSED_66FF: /* 0x166 */ 22685 /* File: armv5te/alt_stub.S */ 22686 /* 22687 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22688 * any interesting requests and then jump to the real instruction 22689 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22690 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22691 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22692 * bail to the real handler if breakFlags==0. 22693 */ 22694 ldrb r3, [rSELF, #offThread_breakFlags] 22695 adrl lr, dvmAsmInstructionStart + (358 * 64) 22696 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22697 cmp r3, #0 22698 bxeq lr @ nothing to do - jump to real handler 22699 EXPORT_PC() 22700 mov r0, rPC @ arg0 22701 mov r1, rFP @ arg1 22702 mov r2, rSELF @ arg2 22703 b dvmCheckBefore @ (dPC,dFP,self) tail call 22704 22705 /* ------------------------------ */ 22706 .balign 64 22707 .L_ALT_OP_UNUSED_67FF: /* 0x167 */ 22708 /* File: armv5te/alt_stub.S */ 22709 /* 22710 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22711 * any interesting requests and then jump to the real instruction 22712 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22713 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22714 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22715 * bail to the real handler if breakFlags==0. 22716 */ 22717 ldrb r3, [rSELF, #offThread_breakFlags] 22718 adrl lr, dvmAsmInstructionStart + (359 * 64) 22719 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22720 cmp r3, #0 22721 bxeq lr @ nothing to do - jump to real handler 22722 EXPORT_PC() 22723 mov r0, rPC @ arg0 22724 mov r1, rFP @ arg1 22725 mov r2, rSELF @ arg2 22726 b dvmCheckBefore @ (dPC,dFP,self) tail call 22727 22728 /* ------------------------------ */ 22729 .balign 64 22730 .L_ALT_OP_UNUSED_68FF: /* 0x168 */ 22731 /* File: armv5te/alt_stub.S */ 22732 /* 22733 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22734 * any interesting requests and then jump to the real instruction 22735 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22736 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22737 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22738 * bail to the real handler if breakFlags==0. 22739 */ 22740 ldrb r3, [rSELF, #offThread_breakFlags] 22741 adrl lr, dvmAsmInstructionStart + (360 * 64) 22742 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22743 cmp r3, #0 22744 bxeq lr @ nothing to do - jump to real handler 22745 EXPORT_PC() 22746 mov r0, rPC @ arg0 22747 mov r1, rFP @ arg1 22748 mov r2, rSELF @ arg2 22749 b dvmCheckBefore @ (dPC,dFP,self) tail call 22750 22751 /* ------------------------------ */ 22752 .balign 64 22753 .L_ALT_OP_UNUSED_69FF: /* 0x169 */ 22754 /* File: armv5te/alt_stub.S */ 22755 /* 22756 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22757 * any interesting requests and then jump to the real instruction 22758 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22759 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22760 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22761 * bail to the real handler if breakFlags==0. 22762 */ 22763 ldrb r3, [rSELF, #offThread_breakFlags] 22764 adrl lr, dvmAsmInstructionStart + (361 * 64) 22765 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22766 cmp r3, #0 22767 bxeq lr @ nothing to do - jump to real handler 22768 EXPORT_PC() 22769 mov r0, rPC @ arg0 22770 mov r1, rFP @ arg1 22771 mov r2, rSELF @ arg2 22772 b dvmCheckBefore @ (dPC,dFP,self) tail call 22773 22774 /* ------------------------------ */ 22775 .balign 64 22776 .L_ALT_OP_UNUSED_6AFF: /* 0x16a */ 22777 /* File: armv5te/alt_stub.S */ 22778 /* 22779 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22780 * any interesting requests and then jump to the real instruction 22781 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22782 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22783 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22784 * bail to the real handler if breakFlags==0. 22785 */ 22786 ldrb r3, [rSELF, #offThread_breakFlags] 22787 adrl lr, dvmAsmInstructionStart + (362 * 64) 22788 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22789 cmp r3, #0 22790 bxeq lr @ nothing to do - jump to real handler 22791 EXPORT_PC() 22792 mov r0, rPC @ arg0 22793 mov r1, rFP @ arg1 22794 mov r2, rSELF @ arg2 22795 b dvmCheckBefore @ (dPC,dFP,self) tail call 22796 22797 /* ------------------------------ */ 22798 .balign 64 22799 .L_ALT_OP_UNUSED_6BFF: /* 0x16b */ 22800 /* File: armv5te/alt_stub.S */ 22801 /* 22802 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22803 * any interesting requests and then jump to the real instruction 22804 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22805 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22806 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22807 * bail to the real handler if breakFlags==0. 22808 */ 22809 ldrb r3, [rSELF, #offThread_breakFlags] 22810 adrl lr, dvmAsmInstructionStart + (363 * 64) 22811 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22812 cmp r3, #0 22813 bxeq lr @ nothing to do - jump to real handler 22814 EXPORT_PC() 22815 mov r0, rPC @ arg0 22816 mov r1, rFP @ arg1 22817 mov r2, rSELF @ arg2 22818 b dvmCheckBefore @ (dPC,dFP,self) tail call 22819 22820 /* ------------------------------ */ 22821 .balign 64 22822 .L_ALT_OP_UNUSED_6CFF: /* 0x16c */ 22823 /* File: armv5te/alt_stub.S */ 22824 /* 22825 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22826 * any interesting requests and then jump to the real instruction 22827 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22828 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22829 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22830 * bail to the real handler if breakFlags==0. 22831 */ 22832 ldrb r3, [rSELF, #offThread_breakFlags] 22833 adrl lr, dvmAsmInstructionStart + (364 * 64) 22834 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22835 cmp r3, #0 22836 bxeq lr @ nothing to do - jump to real handler 22837 EXPORT_PC() 22838 mov r0, rPC @ arg0 22839 mov r1, rFP @ arg1 22840 mov r2, rSELF @ arg2 22841 b dvmCheckBefore @ (dPC,dFP,self) tail call 22842 22843 /* ------------------------------ */ 22844 .balign 64 22845 .L_ALT_OP_UNUSED_6DFF: /* 0x16d */ 22846 /* File: armv5te/alt_stub.S */ 22847 /* 22848 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22849 * any interesting requests and then jump to the real instruction 22850 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22851 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22852 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22853 * bail to the real handler if breakFlags==0. 22854 */ 22855 ldrb r3, [rSELF, #offThread_breakFlags] 22856 adrl lr, dvmAsmInstructionStart + (365 * 64) 22857 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22858 cmp r3, #0 22859 bxeq lr @ nothing to do - jump to real handler 22860 EXPORT_PC() 22861 mov r0, rPC @ arg0 22862 mov r1, rFP @ arg1 22863 mov r2, rSELF @ arg2 22864 b dvmCheckBefore @ (dPC,dFP,self) tail call 22865 22866 /* ------------------------------ */ 22867 .balign 64 22868 .L_ALT_OP_UNUSED_6EFF: /* 0x16e */ 22869 /* File: armv5te/alt_stub.S */ 22870 /* 22871 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22872 * any interesting requests and then jump to the real instruction 22873 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22874 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22875 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22876 * bail to the real handler if breakFlags==0. 22877 */ 22878 ldrb r3, [rSELF, #offThread_breakFlags] 22879 adrl lr, dvmAsmInstructionStart + (366 * 64) 22880 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22881 cmp r3, #0 22882 bxeq lr @ nothing to do - jump to real handler 22883 EXPORT_PC() 22884 mov r0, rPC @ arg0 22885 mov r1, rFP @ arg1 22886 mov r2, rSELF @ arg2 22887 b dvmCheckBefore @ (dPC,dFP,self) tail call 22888 22889 /* ------------------------------ */ 22890 .balign 64 22891 .L_ALT_OP_UNUSED_6FFF: /* 0x16f */ 22892 /* File: armv5te/alt_stub.S */ 22893 /* 22894 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22895 * any interesting requests and then jump to the real instruction 22896 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22897 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22898 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22899 * bail to the real handler if breakFlags==0. 22900 */ 22901 ldrb r3, [rSELF, #offThread_breakFlags] 22902 adrl lr, dvmAsmInstructionStart + (367 * 64) 22903 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22904 cmp r3, #0 22905 bxeq lr @ nothing to do - jump to real handler 22906 EXPORT_PC() 22907 mov r0, rPC @ arg0 22908 mov r1, rFP @ arg1 22909 mov r2, rSELF @ arg2 22910 b dvmCheckBefore @ (dPC,dFP,self) tail call 22911 22912 /* ------------------------------ */ 22913 .balign 64 22914 .L_ALT_OP_UNUSED_70FF: /* 0x170 */ 22915 /* File: armv5te/alt_stub.S */ 22916 /* 22917 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22918 * any interesting requests and then jump to the real instruction 22919 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22920 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22921 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22922 * bail to the real handler if breakFlags==0. 22923 */ 22924 ldrb r3, [rSELF, #offThread_breakFlags] 22925 adrl lr, dvmAsmInstructionStart + (368 * 64) 22926 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22927 cmp r3, #0 22928 bxeq lr @ nothing to do - jump to real handler 22929 EXPORT_PC() 22930 mov r0, rPC @ arg0 22931 mov r1, rFP @ arg1 22932 mov r2, rSELF @ arg2 22933 b dvmCheckBefore @ (dPC,dFP,self) tail call 22934 22935 /* ------------------------------ */ 22936 .balign 64 22937 .L_ALT_OP_UNUSED_71FF: /* 0x171 */ 22938 /* File: armv5te/alt_stub.S */ 22939 /* 22940 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22941 * any interesting requests and then jump to the real instruction 22942 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22943 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22944 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22945 * bail to the real handler if breakFlags==0. 22946 */ 22947 ldrb r3, [rSELF, #offThread_breakFlags] 22948 adrl lr, dvmAsmInstructionStart + (369 * 64) 22949 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22950 cmp r3, #0 22951 bxeq lr @ nothing to do - jump to real handler 22952 EXPORT_PC() 22953 mov r0, rPC @ arg0 22954 mov r1, rFP @ arg1 22955 mov r2, rSELF @ arg2 22956 b dvmCheckBefore @ (dPC,dFP,self) tail call 22957 22958 /* ------------------------------ */ 22959 .balign 64 22960 .L_ALT_OP_UNUSED_72FF: /* 0x172 */ 22961 /* File: armv5te/alt_stub.S */ 22962 /* 22963 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22964 * any interesting requests and then jump to the real instruction 22965 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22966 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22967 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22968 * bail to the real handler if breakFlags==0. 22969 */ 22970 ldrb r3, [rSELF, #offThread_breakFlags] 22971 adrl lr, dvmAsmInstructionStart + (370 * 64) 22972 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22973 cmp r3, #0 22974 bxeq lr @ nothing to do - jump to real handler 22975 EXPORT_PC() 22976 mov r0, rPC @ arg0 22977 mov r1, rFP @ arg1 22978 mov r2, rSELF @ arg2 22979 b dvmCheckBefore @ (dPC,dFP,self) tail call 22980 22981 /* ------------------------------ */ 22982 .balign 64 22983 .L_ALT_OP_UNUSED_73FF: /* 0x173 */ 22984 /* File: armv5te/alt_stub.S */ 22985 /* 22986 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 22987 * any interesting requests and then jump to the real instruction 22988 * handler. Note that the call to dvmCheckBefore is done as a tail call. 22989 * rIBASE updates won't be seen until a refresh, and we can tell we have a 22990 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 22991 * bail to the real handler if breakFlags==0. 22992 */ 22993 ldrb r3, [rSELF, #offThread_breakFlags] 22994 adrl lr, dvmAsmInstructionStart + (371 * 64) 22995 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 22996 cmp r3, #0 22997 bxeq lr @ nothing to do - jump to real handler 22998 EXPORT_PC() 22999 mov r0, rPC @ arg0 23000 mov r1, rFP @ arg1 23001 mov r2, rSELF @ arg2 23002 b dvmCheckBefore @ (dPC,dFP,self) tail call 23003 23004 /* ------------------------------ */ 23005 .balign 64 23006 .L_ALT_OP_UNUSED_74FF: /* 0x174 */ 23007 /* File: armv5te/alt_stub.S */ 23008 /* 23009 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23010 * any interesting requests and then jump to the real instruction 23011 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23012 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23013 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23014 * bail to the real handler if breakFlags==0. 23015 */ 23016 ldrb r3, [rSELF, #offThread_breakFlags] 23017 adrl lr, dvmAsmInstructionStart + (372 * 64) 23018 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23019 cmp r3, #0 23020 bxeq lr @ nothing to do - jump to real handler 23021 EXPORT_PC() 23022 mov r0, rPC @ arg0 23023 mov r1, rFP @ arg1 23024 mov r2, rSELF @ arg2 23025 b dvmCheckBefore @ (dPC,dFP,self) tail call 23026 23027 /* ------------------------------ */ 23028 .balign 64 23029 .L_ALT_OP_UNUSED_75FF: /* 0x175 */ 23030 /* File: armv5te/alt_stub.S */ 23031 /* 23032 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23033 * any interesting requests and then jump to the real instruction 23034 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23035 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23036 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23037 * bail to the real handler if breakFlags==0. 23038 */ 23039 ldrb r3, [rSELF, #offThread_breakFlags] 23040 adrl lr, dvmAsmInstructionStart + (373 * 64) 23041 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23042 cmp r3, #0 23043 bxeq lr @ nothing to do - jump to real handler 23044 EXPORT_PC() 23045 mov r0, rPC @ arg0 23046 mov r1, rFP @ arg1 23047 mov r2, rSELF @ arg2 23048 b dvmCheckBefore @ (dPC,dFP,self) tail call 23049 23050 /* ------------------------------ */ 23051 .balign 64 23052 .L_ALT_OP_UNUSED_76FF: /* 0x176 */ 23053 /* File: armv5te/alt_stub.S */ 23054 /* 23055 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23056 * any interesting requests and then jump to the real instruction 23057 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23058 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23059 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23060 * bail to the real handler if breakFlags==0. 23061 */ 23062 ldrb r3, [rSELF, #offThread_breakFlags] 23063 adrl lr, dvmAsmInstructionStart + (374 * 64) 23064 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23065 cmp r3, #0 23066 bxeq lr @ nothing to do - jump to real handler 23067 EXPORT_PC() 23068 mov r0, rPC @ arg0 23069 mov r1, rFP @ arg1 23070 mov r2, rSELF @ arg2 23071 b dvmCheckBefore @ (dPC,dFP,self) tail call 23072 23073 /* ------------------------------ */ 23074 .balign 64 23075 .L_ALT_OP_UNUSED_77FF: /* 0x177 */ 23076 /* File: armv5te/alt_stub.S */ 23077 /* 23078 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23079 * any interesting requests and then jump to the real instruction 23080 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23081 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23082 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23083 * bail to the real handler if breakFlags==0. 23084 */ 23085 ldrb r3, [rSELF, #offThread_breakFlags] 23086 adrl lr, dvmAsmInstructionStart + (375 * 64) 23087 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23088 cmp r3, #0 23089 bxeq lr @ nothing to do - jump to real handler 23090 EXPORT_PC() 23091 mov r0, rPC @ arg0 23092 mov r1, rFP @ arg1 23093 mov r2, rSELF @ arg2 23094 b dvmCheckBefore @ (dPC,dFP,self) tail call 23095 23096 /* ------------------------------ */ 23097 .balign 64 23098 .L_ALT_OP_UNUSED_78FF: /* 0x178 */ 23099 /* File: armv5te/alt_stub.S */ 23100 /* 23101 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23102 * any interesting requests and then jump to the real instruction 23103 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23104 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23105 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23106 * bail to the real handler if breakFlags==0. 23107 */ 23108 ldrb r3, [rSELF, #offThread_breakFlags] 23109 adrl lr, dvmAsmInstructionStart + (376 * 64) 23110 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23111 cmp r3, #0 23112 bxeq lr @ nothing to do - jump to real handler 23113 EXPORT_PC() 23114 mov r0, rPC @ arg0 23115 mov r1, rFP @ arg1 23116 mov r2, rSELF @ arg2 23117 b dvmCheckBefore @ (dPC,dFP,self) tail call 23118 23119 /* ------------------------------ */ 23120 .balign 64 23121 .L_ALT_OP_UNUSED_79FF: /* 0x179 */ 23122 /* File: armv5te/alt_stub.S */ 23123 /* 23124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23125 * any interesting requests and then jump to the real instruction 23126 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23127 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23129 * bail to the real handler if breakFlags==0. 23130 */ 23131 ldrb r3, [rSELF, #offThread_breakFlags] 23132 adrl lr, dvmAsmInstructionStart + (377 * 64) 23133 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23134 cmp r3, #0 23135 bxeq lr @ nothing to do - jump to real handler 23136 EXPORT_PC() 23137 mov r0, rPC @ arg0 23138 mov r1, rFP @ arg1 23139 mov r2, rSELF @ arg2 23140 b dvmCheckBefore @ (dPC,dFP,self) tail call 23141 23142 /* ------------------------------ */ 23143 .balign 64 23144 .L_ALT_OP_UNUSED_7AFF: /* 0x17a */ 23145 /* File: armv5te/alt_stub.S */ 23146 /* 23147 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23148 * any interesting requests and then jump to the real instruction 23149 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23150 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23151 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23152 * bail to the real handler if breakFlags==0. 23153 */ 23154 ldrb r3, [rSELF, #offThread_breakFlags] 23155 adrl lr, dvmAsmInstructionStart + (378 * 64) 23156 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23157 cmp r3, #0 23158 bxeq lr @ nothing to do - jump to real handler 23159 EXPORT_PC() 23160 mov r0, rPC @ arg0 23161 mov r1, rFP @ arg1 23162 mov r2, rSELF @ arg2 23163 b dvmCheckBefore @ (dPC,dFP,self) tail call 23164 23165 /* ------------------------------ */ 23166 .balign 64 23167 .L_ALT_OP_UNUSED_7BFF: /* 0x17b */ 23168 /* File: armv5te/alt_stub.S */ 23169 /* 23170 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23171 * any interesting requests and then jump to the real instruction 23172 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23173 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23174 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23175 * bail to the real handler if breakFlags==0. 23176 */ 23177 ldrb r3, [rSELF, #offThread_breakFlags] 23178 adrl lr, dvmAsmInstructionStart + (379 * 64) 23179 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23180 cmp r3, #0 23181 bxeq lr @ nothing to do - jump to real handler 23182 EXPORT_PC() 23183 mov r0, rPC @ arg0 23184 mov r1, rFP @ arg1 23185 mov r2, rSELF @ arg2 23186 b dvmCheckBefore @ (dPC,dFP,self) tail call 23187 23188 /* ------------------------------ */ 23189 .balign 64 23190 .L_ALT_OP_UNUSED_7CFF: /* 0x17c */ 23191 /* File: armv5te/alt_stub.S */ 23192 /* 23193 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23194 * any interesting requests and then jump to the real instruction 23195 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23196 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23197 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23198 * bail to the real handler if breakFlags==0. 23199 */ 23200 ldrb r3, [rSELF, #offThread_breakFlags] 23201 adrl lr, dvmAsmInstructionStart + (380 * 64) 23202 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23203 cmp r3, #0 23204 bxeq lr @ nothing to do - jump to real handler 23205 EXPORT_PC() 23206 mov r0, rPC @ arg0 23207 mov r1, rFP @ arg1 23208 mov r2, rSELF @ arg2 23209 b dvmCheckBefore @ (dPC,dFP,self) tail call 23210 23211 /* ------------------------------ */ 23212 .balign 64 23213 .L_ALT_OP_UNUSED_7DFF: /* 0x17d */ 23214 /* File: armv5te/alt_stub.S */ 23215 /* 23216 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23217 * any interesting requests and then jump to the real instruction 23218 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23219 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23220 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23221 * bail to the real handler if breakFlags==0. 23222 */ 23223 ldrb r3, [rSELF, #offThread_breakFlags] 23224 adrl lr, dvmAsmInstructionStart + (381 * 64) 23225 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23226 cmp r3, #0 23227 bxeq lr @ nothing to do - jump to real handler 23228 EXPORT_PC() 23229 mov r0, rPC @ arg0 23230 mov r1, rFP @ arg1 23231 mov r2, rSELF @ arg2 23232 b dvmCheckBefore @ (dPC,dFP,self) tail call 23233 23234 /* ------------------------------ */ 23235 .balign 64 23236 .L_ALT_OP_UNUSED_7EFF: /* 0x17e */ 23237 /* File: armv5te/alt_stub.S */ 23238 /* 23239 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23240 * any interesting requests and then jump to the real instruction 23241 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23242 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23243 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23244 * bail to the real handler if breakFlags==0. 23245 */ 23246 ldrb r3, [rSELF, #offThread_breakFlags] 23247 adrl lr, dvmAsmInstructionStart + (382 * 64) 23248 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23249 cmp r3, #0 23250 bxeq lr @ nothing to do - jump to real handler 23251 EXPORT_PC() 23252 mov r0, rPC @ arg0 23253 mov r1, rFP @ arg1 23254 mov r2, rSELF @ arg2 23255 b dvmCheckBefore @ (dPC,dFP,self) tail call 23256 23257 /* ------------------------------ */ 23258 .balign 64 23259 .L_ALT_OP_UNUSED_7FFF: /* 0x17f */ 23260 /* File: armv5te/alt_stub.S */ 23261 /* 23262 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23263 * any interesting requests and then jump to the real instruction 23264 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23265 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23266 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23267 * bail to the real handler if breakFlags==0. 23268 */ 23269 ldrb r3, [rSELF, #offThread_breakFlags] 23270 adrl lr, dvmAsmInstructionStart + (383 * 64) 23271 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23272 cmp r3, #0 23273 bxeq lr @ nothing to do - jump to real handler 23274 EXPORT_PC() 23275 mov r0, rPC @ arg0 23276 mov r1, rFP @ arg1 23277 mov r2, rSELF @ arg2 23278 b dvmCheckBefore @ (dPC,dFP,self) tail call 23279 23280 /* ------------------------------ */ 23281 .balign 64 23282 .L_ALT_OP_UNUSED_80FF: /* 0x180 */ 23283 /* File: armv5te/alt_stub.S */ 23284 /* 23285 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23286 * any interesting requests and then jump to the real instruction 23287 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23288 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23289 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23290 * bail to the real handler if breakFlags==0. 23291 */ 23292 ldrb r3, [rSELF, #offThread_breakFlags] 23293 adrl lr, dvmAsmInstructionStart + (384 * 64) 23294 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23295 cmp r3, #0 23296 bxeq lr @ nothing to do - jump to real handler 23297 EXPORT_PC() 23298 mov r0, rPC @ arg0 23299 mov r1, rFP @ arg1 23300 mov r2, rSELF @ arg2 23301 b dvmCheckBefore @ (dPC,dFP,self) tail call 23302 23303 /* ------------------------------ */ 23304 .balign 64 23305 .L_ALT_OP_UNUSED_81FF: /* 0x181 */ 23306 /* File: armv5te/alt_stub.S */ 23307 /* 23308 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23309 * any interesting requests and then jump to the real instruction 23310 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23311 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23312 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23313 * bail to the real handler if breakFlags==0. 23314 */ 23315 ldrb r3, [rSELF, #offThread_breakFlags] 23316 adrl lr, dvmAsmInstructionStart + (385 * 64) 23317 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23318 cmp r3, #0 23319 bxeq lr @ nothing to do - jump to real handler 23320 EXPORT_PC() 23321 mov r0, rPC @ arg0 23322 mov r1, rFP @ arg1 23323 mov r2, rSELF @ arg2 23324 b dvmCheckBefore @ (dPC,dFP,self) tail call 23325 23326 /* ------------------------------ */ 23327 .balign 64 23328 .L_ALT_OP_UNUSED_82FF: /* 0x182 */ 23329 /* File: armv5te/alt_stub.S */ 23330 /* 23331 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23332 * any interesting requests and then jump to the real instruction 23333 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23334 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23335 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23336 * bail to the real handler if breakFlags==0. 23337 */ 23338 ldrb r3, [rSELF, #offThread_breakFlags] 23339 adrl lr, dvmAsmInstructionStart + (386 * 64) 23340 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23341 cmp r3, #0 23342 bxeq lr @ nothing to do - jump to real handler 23343 EXPORT_PC() 23344 mov r0, rPC @ arg0 23345 mov r1, rFP @ arg1 23346 mov r2, rSELF @ arg2 23347 b dvmCheckBefore @ (dPC,dFP,self) tail call 23348 23349 /* ------------------------------ */ 23350 .balign 64 23351 .L_ALT_OP_UNUSED_83FF: /* 0x183 */ 23352 /* File: armv5te/alt_stub.S */ 23353 /* 23354 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23355 * any interesting requests and then jump to the real instruction 23356 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23357 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23358 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23359 * bail to the real handler if breakFlags==0. 23360 */ 23361 ldrb r3, [rSELF, #offThread_breakFlags] 23362 adrl lr, dvmAsmInstructionStart + (387 * 64) 23363 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23364 cmp r3, #0 23365 bxeq lr @ nothing to do - jump to real handler 23366 EXPORT_PC() 23367 mov r0, rPC @ arg0 23368 mov r1, rFP @ arg1 23369 mov r2, rSELF @ arg2 23370 b dvmCheckBefore @ (dPC,dFP,self) tail call 23371 23372 /* ------------------------------ */ 23373 .balign 64 23374 .L_ALT_OP_UNUSED_84FF: /* 0x184 */ 23375 /* File: armv5te/alt_stub.S */ 23376 /* 23377 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23378 * any interesting requests and then jump to the real instruction 23379 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23380 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23381 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23382 * bail to the real handler if breakFlags==0. 23383 */ 23384 ldrb r3, [rSELF, #offThread_breakFlags] 23385 adrl lr, dvmAsmInstructionStart + (388 * 64) 23386 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23387 cmp r3, #0 23388 bxeq lr @ nothing to do - jump to real handler 23389 EXPORT_PC() 23390 mov r0, rPC @ arg0 23391 mov r1, rFP @ arg1 23392 mov r2, rSELF @ arg2 23393 b dvmCheckBefore @ (dPC,dFP,self) tail call 23394 23395 /* ------------------------------ */ 23396 .balign 64 23397 .L_ALT_OP_UNUSED_85FF: /* 0x185 */ 23398 /* File: armv5te/alt_stub.S */ 23399 /* 23400 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23401 * any interesting requests and then jump to the real instruction 23402 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23403 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23404 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23405 * bail to the real handler if breakFlags==0. 23406 */ 23407 ldrb r3, [rSELF, #offThread_breakFlags] 23408 adrl lr, dvmAsmInstructionStart + (389 * 64) 23409 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23410 cmp r3, #0 23411 bxeq lr @ nothing to do - jump to real handler 23412 EXPORT_PC() 23413 mov r0, rPC @ arg0 23414 mov r1, rFP @ arg1 23415 mov r2, rSELF @ arg2 23416 b dvmCheckBefore @ (dPC,dFP,self) tail call 23417 23418 /* ------------------------------ */ 23419 .balign 64 23420 .L_ALT_OP_UNUSED_86FF: /* 0x186 */ 23421 /* File: armv5te/alt_stub.S */ 23422 /* 23423 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23424 * any interesting requests and then jump to the real instruction 23425 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23426 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23427 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23428 * bail to the real handler if breakFlags==0. 23429 */ 23430 ldrb r3, [rSELF, #offThread_breakFlags] 23431 adrl lr, dvmAsmInstructionStart + (390 * 64) 23432 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23433 cmp r3, #0 23434 bxeq lr @ nothing to do - jump to real handler 23435 EXPORT_PC() 23436 mov r0, rPC @ arg0 23437 mov r1, rFP @ arg1 23438 mov r2, rSELF @ arg2 23439 b dvmCheckBefore @ (dPC,dFP,self) tail call 23440 23441 /* ------------------------------ */ 23442 .balign 64 23443 .L_ALT_OP_UNUSED_87FF: /* 0x187 */ 23444 /* File: armv5te/alt_stub.S */ 23445 /* 23446 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23447 * any interesting requests and then jump to the real instruction 23448 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23449 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23450 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23451 * bail to the real handler if breakFlags==0. 23452 */ 23453 ldrb r3, [rSELF, #offThread_breakFlags] 23454 adrl lr, dvmAsmInstructionStart + (391 * 64) 23455 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23456 cmp r3, #0 23457 bxeq lr @ nothing to do - jump to real handler 23458 EXPORT_PC() 23459 mov r0, rPC @ arg0 23460 mov r1, rFP @ arg1 23461 mov r2, rSELF @ arg2 23462 b dvmCheckBefore @ (dPC,dFP,self) tail call 23463 23464 /* ------------------------------ */ 23465 .balign 64 23466 .L_ALT_OP_UNUSED_88FF: /* 0x188 */ 23467 /* File: armv5te/alt_stub.S */ 23468 /* 23469 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23470 * any interesting requests and then jump to the real instruction 23471 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23472 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23473 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23474 * bail to the real handler if breakFlags==0. 23475 */ 23476 ldrb r3, [rSELF, #offThread_breakFlags] 23477 adrl lr, dvmAsmInstructionStart + (392 * 64) 23478 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23479 cmp r3, #0 23480 bxeq lr @ nothing to do - jump to real handler 23481 EXPORT_PC() 23482 mov r0, rPC @ arg0 23483 mov r1, rFP @ arg1 23484 mov r2, rSELF @ arg2 23485 b dvmCheckBefore @ (dPC,dFP,self) tail call 23486 23487 /* ------------------------------ */ 23488 .balign 64 23489 .L_ALT_OP_UNUSED_89FF: /* 0x189 */ 23490 /* File: armv5te/alt_stub.S */ 23491 /* 23492 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23493 * any interesting requests and then jump to the real instruction 23494 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23495 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23496 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23497 * bail to the real handler if breakFlags==0. 23498 */ 23499 ldrb r3, [rSELF, #offThread_breakFlags] 23500 adrl lr, dvmAsmInstructionStart + (393 * 64) 23501 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23502 cmp r3, #0 23503 bxeq lr @ nothing to do - jump to real handler 23504 EXPORT_PC() 23505 mov r0, rPC @ arg0 23506 mov r1, rFP @ arg1 23507 mov r2, rSELF @ arg2 23508 b dvmCheckBefore @ (dPC,dFP,self) tail call 23509 23510 /* ------------------------------ */ 23511 .balign 64 23512 .L_ALT_OP_UNUSED_8AFF: /* 0x18a */ 23513 /* File: armv5te/alt_stub.S */ 23514 /* 23515 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23516 * any interesting requests and then jump to the real instruction 23517 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23518 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23519 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23520 * bail to the real handler if breakFlags==0. 23521 */ 23522 ldrb r3, [rSELF, #offThread_breakFlags] 23523 adrl lr, dvmAsmInstructionStart + (394 * 64) 23524 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23525 cmp r3, #0 23526 bxeq lr @ nothing to do - jump to real handler 23527 EXPORT_PC() 23528 mov r0, rPC @ arg0 23529 mov r1, rFP @ arg1 23530 mov r2, rSELF @ arg2 23531 b dvmCheckBefore @ (dPC,dFP,self) tail call 23532 23533 /* ------------------------------ */ 23534 .balign 64 23535 .L_ALT_OP_UNUSED_8BFF: /* 0x18b */ 23536 /* File: armv5te/alt_stub.S */ 23537 /* 23538 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23539 * any interesting requests and then jump to the real instruction 23540 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23541 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23542 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23543 * bail to the real handler if breakFlags==0. 23544 */ 23545 ldrb r3, [rSELF, #offThread_breakFlags] 23546 adrl lr, dvmAsmInstructionStart + (395 * 64) 23547 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23548 cmp r3, #0 23549 bxeq lr @ nothing to do - jump to real handler 23550 EXPORT_PC() 23551 mov r0, rPC @ arg0 23552 mov r1, rFP @ arg1 23553 mov r2, rSELF @ arg2 23554 b dvmCheckBefore @ (dPC,dFP,self) tail call 23555 23556 /* ------------------------------ */ 23557 .balign 64 23558 .L_ALT_OP_UNUSED_8CFF: /* 0x18c */ 23559 /* File: armv5te/alt_stub.S */ 23560 /* 23561 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23562 * any interesting requests and then jump to the real instruction 23563 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23564 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23565 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23566 * bail to the real handler if breakFlags==0. 23567 */ 23568 ldrb r3, [rSELF, #offThread_breakFlags] 23569 adrl lr, dvmAsmInstructionStart + (396 * 64) 23570 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23571 cmp r3, #0 23572 bxeq lr @ nothing to do - jump to real handler 23573 EXPORT_PC() 23574 mov r0, rPC @ arg0 23575 mov r1, rFP @ arg1 23576 mov r2, rSELF @ arg2 23577 b dvmCheckBefore @ (dPC,dFP,self) tail call 23578 23579 /* ------------------------------ */ 23580 .balign 64 23581 .L_ALT_OP_UNUSED_8DFF: /* 0x18d */ 23582 /* File: armv5te/alt_stub.S */ 23583 /* 23584 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23585 * any interesting requests and then jump to the real instruction 23586 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23587 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23588 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23589 * bail to the real handler if breakFlags==0. 23590 */ 23591 ldrb r3, [rSELF, #offThread_breakFlags] 23592 adrl lr, dvmAsmInstructionStart + (397 * 64) 23593 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23594 cmp r3, #0 23595 bxeq lr @ nothing to do - jump to real handler 23596 EXPORT_PC() 23597 mov r0, rPC @ arg0 23598 mov r1, rFP @ arg1 23599 mov r2, rSELF @ arg2 23600 b dvmCheckBefore @ (dPC,dFP,self) tail call 23601 23602 /* ------------------------------ */ 23603 .balign 64 23604 .L_ALT_OP_UNUSED_8EFF: /* 0x18e */ 23605 /* File: armv5te/alt_stub.S */ 23606 /* 23607 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23608 * any interesting requests and then jump to the real instruction 23609 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23610 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23611 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23612 * bail to the real handler if breakFlags==0. 23613 */ 23614 ldrb r3, [rSELF, #offThread_breakFlags] 23615 adrl lr, dvmAsmInstructionStart + (398 * 64) 23616 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23617 cmp r3, #0 23618 bxeq lr @ nothing to do - jump to real handler 23619 EXPORT_PC() 23620 mov r0, rPC @ arg0 23621 mov r1, rFP @ arg1 23622 mov r2, rSELF @ arg2 23623 b dvmCheckBefore @ (dPC,dFP,self) tail call 23624 23625 /* ------------------------------ */ 23626 .balign 64 23627 .L_ALT_OP_UNUSED_8FFF: /* 0x18f */ 23628 /* File: armv5te/alt_stub.S */ 23629 /* 23630 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23631 * any interesting requests and then jump to the real instruction 23632 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23633 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23634 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23635 * bail to the real handler if breakFlags==0. 23636 */ 23637 ldrb r3, [rSELF, #offThread_breakFlags] 23638 adrl lr, dvmAsmInstructionStart + (399 * 64) 23639 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23640 cmp r3, #0 23641 bxeq lr @ nothing to do - jump to real handler 23642 EXPORT_PC() 23643 mov r0, rPC @ arg0 23644 mov r1, rFP @ arg1 23645 mov r2, rSELF @ arg2 23646 b dvmCheckBefore @ (dPC,dFP,self) tail call 23647 23648 /* ------------------------------ */ 23649 .balign 64 23650 .L_ALT_OP_UNUSED_90FF: /* 0x190 */ 23651 /* File: armv5te/alt_stub.S */ 23652 /* 23653 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23654 * any interesting requests and then jump to the real instruction 23655 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23656 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23657 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23658 * bail to the real handler if breakFlags==0. 23659 */ 23660 ldrb r3, [rSELF, #offThread_breakFlags] 23661 adrl lr, dvmAsmInstructionStart + (400 * 64) 23662 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23663 cmp r3, #0 23664 bxeq lr @ nothing to do - jump to real handler 23665 EXPORT_PC() 23666 mov r0, rPC @ arg0 23667 mov r1, rFP @ arg1 23668 mov r2, rSELF @ arg2 23669 b dvmCheckBefore @ (dPC,dFP,self) tail call 23670 23671 /* ------------------------------ */ 23672 .balign 64 23673 .L_ALT_OP_UNUSED_91FF: /* 0x191 */ 23674 /* File: armv5te/alt_stub.S */ 23675 /* 23676 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23677 * any interesting requests and then jump to the real instruction 23678 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23679 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23680 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23681 * bail to the real handler if breakFlags==0. 23682 */ 23683 ldrb r3, [rSELF, #offThread_breakFlags] 23684 adrl lr, dvmAsmInstructionStart + (401 * 64) 23685 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23686 cmp r3, #0 23687 bxeq lr @ nothing to do - jump to real handler 23688 EXPORT_PC() 23689 mov r0, rPC @ arg0 23690 mov r1, rFP @ arg1 23691 mov r2, rSELF @ arg2 23692 b dvmCheckBefore @ (dPC,dFP,self) tail call 23693 23694 /* ------------------------------ */ 23695 .balign 64 23696 .L_ALT_OP_UNUSED_92FF: /* 0x192 */ 23697 /* File: armv5te/alt_stub.S */ 23698 /* 23699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23700 * any interesting requests and then jump to the real instruction 23701 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23702 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23704 * bail to the real handler if breakFlags==0. 23705 */ 23706 ldrb r3, [rSELF, #offThread_breakFlags] 23707 adrl lr, dvmAsmInstructionStart + (402 * 64) 23708 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23709 cmp r3, #0 23710 bxeq lr @ nothing to do - jump to real handler 23711 EXPORT_PC() 23712 mov r0, rPC @ arg0 23713 mov r1, rFP @ arg1 23714 mov r2, rSELF @ arg2 23715 b dvmCheckBefore @ (dPC,dFP,self) tail call 23716 23717 /* ------------------------------ */ 23718 .balign 64 23719 .L_ALT_OP_UNUSED_93FF: /* 0x193 */ 23720 /* File: armv5te/alt_stub.S */ 23721 /* 23722 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23723 * any interesting requests and then jump to the real instruction 23724 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23725 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23726 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23727 * bail to the real handler if breakFlags==0. 23728 */ 23729 ldrb r3, [rSELF, #offThread_breakFlags] 23730 adrl lr, dvmAsmInstructionStart + (403 * 64) 23731 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23732 cmp r3, #0 23733 bxeq lr @ nothing to do - jump to real handler 23734 EXPORT_PC() 23735 mov r0, rPC @ arg0 23736 mov r1, rFP @ arg1 23737 mov r2, rSELF @ arg2 23738 b dvmCheckBefore @ (dPC,dFP,self) tail call 23739 23740 /* ------------------------------ */ 23741 .balign 64 23742 .L_ALT_OP_UNUSED_94FF: /* 0x194 */ 23743 /* File: armv5te/alt_stub.S */ 23744 /* 23745 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23746 * any interesting requests and then jump to the real instruction 23747 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23748 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23749 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23750 * bail to the real handler if breakFlags==0. 23751 */ 23752 ldrb r3, [rSELF, #offThread_breakFlags] 23753 adrl lr, dvmAsmInstructionStart + (404 * 64) 23754 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23755 cmp r3, #0 23756 bxeq lr @ nothing to do - jump to real handler 23757 EXPORT_PC() 23758 mov r0, rPC @ arg0 23759 mov r1, rFP @ arg1 23760 mov r2, rSELF @ arg2 23761 b dvmCheckBefore @ (dPC,dFP,self) tail call 23762 23763 /* ------------------------------ */ 23764 .balign 64 23765 .L_ALT_OP_UNUSED_95FF: /* 0x195 */ 23766 /* File: armv5te/alt_stub.S */ 23767 /* 23768 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23769 * any interesting requests and then jump to the real instruction 23770 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23771 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23772 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23773 * bail to the real handler if breakFlags==0. 23774 */ 23775 ldrb r3, [rSELF, #offThread_breakFlags] 23776 adrl lr, dvmAsmInstructionStart + (405 * 64) 23777 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23778 cmp r3, #0 23779 bxeq lr @ nothing to do - jump to real handler 23780 EXPORT_PC() 23781 mov r0, rPC @ arg0 23782 mov r1, rFP @ arg1 23783 mov r2, rSELF @ arg2 23784 b dvmCheckBefore @ (dPC,dFP,self) tail call 23785 23786 /* ------------------------------ */ 23787 .balign 64 23788 .L_ALT_OP_UNUSED_96FF: /* 0x196 */ 23789 /* File: armv5te/alt_stub.S */ 23790 /* 23791 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23792 * any interesting requests and then jump to the real instruction 23793 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23794 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23795 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23796 * bail to the real handler if breakFlags==0. 23797 */ 23798 ldrb r3, [rSELF, #offThread_breakFlags] 23799 adrl lr, dvmAsmInstructionStart + (406 * 64) 23800 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23801 cmp r3, #0 23802 bxeq lr @ nothing to do - jump to real handler 23803 EXPORT_PC() 23804 mov r0, rPC @ arg0 23805 mov r1, rFP @ arg1 23806 mov r2, rSELF @ arg2 23807 b dvmCheckBefore @ (dPC,dFP,self) tail call 23808 23809 /* ------------------------------ */ 23810 .balign 64 23811 .L_ALT_OP_UNUSED_97FF: /* 0x197 */ 23812 /* File: armv5te/alt_stub.S */ 23813 /* 23814 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23815 * any interesting requests and then jump to the real instruction 23816 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23817 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23818 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23819 * bail to the real handler if breakFlags==0. 23820 */ 23821 ldrb r3, [rSELF, #offThread_breakFlags] 23822 adrl lr, dvmAsmInstructionStart + (407 * 64) 23823 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23824 cmp r3, #0 23825 bxeq lr @ nothing to do - jump to real handler 23826 EXPORT_PC() 23827 mov r0, rPC @ arg0 23828 mov r1, rFP @ arg1 23829 mov r2, rSELF @ arg2 23830 b dvmCheckBefore @ (dPC,dFP,self) tail call 23831 23832 /* ------------------------------ */ 23833 .balign 64 23834 .L_ALT_OP_UNUSED_98FF: /* 0x198 */ 23835 /* File: armv5te/alt_stub.S */ 23836 /* 23837 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23838 * any interesting requests and then jump to the real instruction 23839 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23840 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23841 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23842 * bail to the real handler if breakFlags==0. 23843 */ 23844 ldrb r3, [rSELF, #offThread_breakFlags] 23845 adrl lr, dvmAsmInstructionStart + (408 * 64) 23846 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23847 cmp r3, #0 23848 bxeq lr @ nothing to do - jump to real handler 23849 EXPORT_PC() 23850 mov r0, rPC @ arg0 23851 mov r1, rFP @ arg1 23852 mov r2, rSELF @ arg2 23853 b dvmCheckBefore @ (dPC,dFP,self) tail call 23854 23855 /* ------------------------------ */ 23856 .balign 64 23857 .L_ALT_OP_UNUSED_99FF: /* 0x199 */ 23858 /* File: armv5te/alt_stub.S */ 23859 /* 23860 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23861 * any interesting requests and then jump to the real instruction 23862 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23863 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23864 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23865 * bail to the real handler if breakFlags==0. 23866 */ 23867 ldrb r3, [rSELF, #offThread_breakFlags] 23868 adrl lr, dvmAsmInstructionStart + (409 * 64) 23869 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23870 cmp r3, #0 23871 bxeq lr @ nothing to do - jump to real handler 23872 EXPORT_PC() 23873 mov r0, rPC @ arg0 23874 mov r1, rFP @ arg1 23875 mov r2, rSELF @ arg2 23876 b dvmCheckBefore @ (dPC,dFP,self) tail call 23877 23878 /* ------------------------------ */ 23879 .balign 64 23880 .L_ALT_OP_UNUSED_9AFF: /* 0x19a */ 23881 /* File: armv5te/alt_stub.S */ 23882 /* 23883 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23884 * any interesting requests and then jump to the real instruction 23885 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23886 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23887 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23888 * bail to the real handler if breakFlags==0. 23889 */ 23890 ldrb r3, [rSELF, #offThread_breakFlags] 23891 adrl lr, dvmAsmInstructionStart + (410 * 64) 23892 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23893 cmp r3, #0 23894 bxeq lr @ nothing to do - jump to real handler 23895 EXPORT_PC() 23896 mov r0, rPC @ arg0 23897 mov r1, rFP @ arg1 23898 mov r2, rSELF @ arg2 23899 b dvmCheckBefore @ (dPC,dFP,self) tail call 23900 23901 /* ------------------------------ */ 23902 .balign 64 23903 .L_ALT_OP_UNUSED_9BFF: /* 0x19b */ 23904 /* File: armv5te/alt_stub.S */ 23905 /* 23906 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23907 * any interesting requests and then jump to the real instruction 23908 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23909 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23910 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23911 * bail to the real handler if breakFlags==0. 23912 */ 23913 ldrb r3, [rSELF, #offThread_breakFlags] 23914 adrl lr, dvmAsmInstructionStart + (411 * 64) 23915 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23916 cmp r3, #0 23917 bxeq lr @ nothing to do - jump to real handler 23918 EXPORT_PC() 23919 mov r0, rPC @ arg0 23920 mov r1, rFP @ arg1 23921 mov r2, rSELF @ arg2 23922 b dvmCheckBefore @ (dPC,dFP,self) tail call 23923 23924 /* ------------------------------ */ 23925 .balign 64 23926 .L_ALT_OP_UNUSED_9CFF: /* 0x19c */ 23927 /* File: armv5te/alt_stub.S */ 23928 /* 23929 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23930 * any interesting requests and then jump to the real instruction 23931 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23932 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23933 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23934 * bail to the real handler if breakFlags==0. 23935 */ 23936 ldrb r3, [rSELF, #offThread_breakFlags] 23937 adrl lr, dvmAsmInstructionStart + (412 * 64) 23938 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23939 cmp r3, #0 23940 bxeq lr @ nothing to do - jump to real handler 23941 EXPORT_PC() 23942 mov r0, rPC @ arg0 23943 mov r1, rFP @ arg1 23944 mov r2, rSELF @ arg2 23945 b dvmCheckBefore @ (dPC,dFP,self) tail call 23946 23947 /* ------------------------------ */ 23948 .balign 64 23949 .L_ALT_OP_UNUSED_9DFF: /* 0x19d */ 23950 /* File: armv5te/alt_stub.S */ 23951 /* 23952 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23953 * any interesting requests and then jump to the real instruction 23954 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23955 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23956 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23957 * bail to the real handler if breakFlags==0. 23958 */ 23959 ldrb r3, [rSELF, #offThread_breakFlags] 23960 adrl lr, dvmAsmInstructionStart + (413 * 64) 23961 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23962 cmp r3, #0 23963 bxeq lr @ nothing to do - jump to real handler 23964 EXPORT_PC() 23965 mov r0, rPC @ arg0 23966 mov r1, rFP @ arg1 23967 mov r2, rSELF @ arg2 23968 b dvmCheckBefore @ (dPC,dFP,self) tail call 23969 23970 /* ------------------------------ */ 23971 .balign 64 23972 .L_ALT_OP_UNUSED_9EFF: /* 0x19e */ 23973 /* File: armv5te/alt_stub.S */ 23974 /* 23975 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23976 * any interesting requests and then jump to the real instruction 23977 * handler. Note that the call to dvmCheckBefore is done as a tail call. 23978 * rIBASE updates won't be seen until a refresh, and we can tell we have a 23979 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 23980 * bail to the real handler if breakFlags==0. 23981 */ 23982 ldrb r3, [rSELF, #offThread_breakFlags] 23983 adrl lr, dvmAsmInstructionStart + (414 * 64) 23984 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 23985 cmp r3, #0 23986 bxeq lr @ nothing to do - jump to real handler 23987 EXPORT_PC() 23988 mov r0, rPC @ arg0 23989 mov r1, rFP @ arg1 23990 mov r2, rSELF @ arg2 23991 b dvmCheckBefore @ (dPC,dFP,self) tail call 23992 23993 /* ------------------------------ */ 23994 .balign 64 23995 .L_ALT_OP_UNUSED_9FFF: /* 0x19f */ 23996 /* File: armv5te/alt_stub.S */ 23997 /* 23998 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 23999 * any interesting requests and then jump to the real instruction 24000 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24001 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24002 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24003 * bail to the real handler if breakFlags==0. 24004 */ 24005 ldrb r3, [rSELF, #offThread_breakFlags] 24006 adrl lr, dvmAsmInstructionStart + (415 * 64) 24007 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24008 cmp r3, #0 24009 bxeq lr @ nothing to do - jump to real handler 24010 EXPORT_PC() 24011 mov r0, rPC @ arg0 24012 mov r1, rFP @ arg1 24013 mov r2, rSELF @ arg2 24014 b dvmCheckBefore @ (dPC,dFP,self) tail call 24015 24016 /* ------------------------------ */ 24017 .balign 64 24018 .L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */ 24019 /* File: armv5te/alt_stub.S */ 24020 /* 24021 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24022 * any interesting requests and then jump to the real instruction 24023 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24024 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24025 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24026 * bail to the real handler if breakFlags==0. 24027 */ 24028 ldrb r3, [rSELF, #offThread_breakFlags] 24029 adrl lr, dvmAsmInstructionStart + (416 * 64) 24030 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24031 cmp r3, #0 24032 bxeq lr @ nothing to do - jump to real handler 24033 EXPORT_PC() 24034 mov r0, rPC @ arg0 24035 mov r1, rFP @ arg1 24036 mov r2, rSELF @ arg2 24037 b dvmCheckBefore @ (dPC,dFP,self) tail call 24038 24039 /* ------------------------------ */ 24040 .balign 64 24041 .L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */ 24042 /* File: armv5te/alt_stub.S */ 24043 /* 24044 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24045 * any interesting requests and then jump to the real instruction 24046 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24047 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24048 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24049 * bail to the real handler if breakFlags==0. 24050 */ 24051 ldrb r3, [rSELF, #offThread_breakFlags] 24052 adrl lr, dvmAsmInstructionStart + (417 * 64) 24053 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24054 cmp r3, #0 24055 bxeq lr @ nothing to do - jump to real handler 24056 EXPORT_PC() 24057 mov r0, rPC @ arg0 24058 mov r1, rFP @ arg1 24059 mov r2, rSELF @ arg2 24060 b dvmCheckBefore @ (dPC,dFP,self) tail call 24061 24062 /* ------------------------------ */ 24063 .balign 64 24064 .L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */ 24065 /* File: armv5te/alt_stub.S */ 24066 /* 24067 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24068 * any interesting requests and then jump to the real instruction 24069 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24070 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24071 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24072 * bail to the real handler if breakFlags==0. 24073 */ 24074 ldrb r3, [rSELF, #offThread_breakFlags] 24075 adrl lr, dvmAsmInstructionStart + (418 * 64) 24076 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24077 cmp r3, #0 24078 bxeq lr @ nothing to do - jump to real handler 24079 EXPORT_PC() 24080 mov r0, rPC @ arg0 24081 mov r1, rFP @ arg1 24082 mov r2, rSELF @ arg2 24083 b dvmCheckBefore @ (dPC,dFP,self) tail call 24084 24085 /* ------------------------------ */ 24086 .balign 64 24087 .L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */ 24088 /* File: armv5te/alt_stub.S */ 24089 /* 24090 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24091 * any interesting requests and then jump to the real instruction 24092 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24093 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24094 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24095 * bail to the real handler if breakFlags==0. 24096 */ 24097 ldrb r3, [rSELF, #offThread_breakFlags] 24098 adrl lr, dvmAsmInstructionStart + (419 * 64) 24099 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24100 cmp r3, #0 24101 bxeq lr @ nothing to do - jump to real handler 24102 EXPORT_PC() 24103 mov r0, rPC @ arg0 24104 mov r1, rFP @ arg1 24105 mov r2, rSELF @ arg2 24106 b dvmCheckBefore @ (dPC,dFP,self) tail call 24107 24108 /* ------------------------------ */ 24109 .balign 64 24110 .L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */ 24111 /* File: armv5te/alt_stub.S */ 24112 /* 24113 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24114 * any interesting requests and then jump to the real instruction 24115 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24116 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24117 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24118 * bail to the real handler if breakFlags==0. 24119 */ 24120 ldrb r3, [rSELF, #offThread_breakFlags] 24121 adrl lr, dvmAsmInstructionStart + (420 * 64) 24122 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24123 cmp r3, #0 24124 bxeq lr @ nothing to do - jump to real handler 24125 EXPORT_PC() 24126 mov r0, rPC @ arg0 24127 mov r1, rFP @ arg1 24128 mov r2, rSELF @ arg2 24129 b dvmCheckBefore @ (dPC,dFP,self) tail call 24130 24131 /* ------------------------------ */ 24132 .balign 64 24133 .L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */ 24134 /* File: armv5te/alt_stub.S */ 24135 /* 24136 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24137 * any interesting requests and then jump to the real instruction 24138 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24139 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24140 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24141 * bail to the real handler if breakFlags==0. 24142 */ 24143 ldrb r3, [rSELF, #offThread_breakFlags] 24144 adrl lr, dvmAsmInstructionStart + (421 * 64) 24145 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24146 cmp r3, #0 24147 bxeq lr @ nothing to do - jump to real handler 24148 EXPORT_PC() 24149 mov r0, rPC @ arg0 24150 mov r1, rFP @ arg1 24151 mov r2, rSELF @ arg2 24152 b dvmCheckBefore @ (dPC,dFP,self) tail call 24153 24154 /* ------------------------------ */ 24155 .balign 64 24156 .L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */ 24157 /* File: armv5te/alt_stub.S */ 24158 /* 24159 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24160 * any interesting requests and then jump to the real instruction 24161 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24162 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24163 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24164 * bail to the real handler if breakFlags==0. 24165 */ 24166 ldrb r3, [rSELF, #offThread_breakFlags] 24167 adrl lr, dvmAsmInstructionStart + (422 * 64) 24168 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24169 cmp r3, #0 24170 bxeq lr @ nothing to do - jump to real handler 24171 EXPORT_PC() 24172 mov r0, rPC @ arg0 24173 mov r1, rFP @ arg1 24174 mov r2, rSELF @ arg2 24175 b dvmCheckBefore @ (dPC,dFP,self) tail call 24176 24177 /* ------------------------------ */ 24178 .balign 64 24179 .L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */ 24180 /* File: armv5te/alt_stub.S */ 24181 /* 24182 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24183 * any interesting requests and then jump to the real instruction 24184 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24185 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24186 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24187 * bail to the real handler if breakFlags==0. 24188 */ 24189 ldrb r3, [rSELF, #offThread_breakFlags] 24190 adrl lr, dvmAsmInstructionStart + (423 * 64) 24191 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24192 cmp r3, #0 24193 bxeq lr @ nothing to do - jump to real handler 24194 EXPORT_PC() 24195 mov r0, rPC @ arg0 24196 mov r1, rFP @ arg1 24197 mov r2, rSELF @ arg2 24198 b dvmCheckBefore @ (dPC,dFP,self) tail call 24199 24200 /* ------------------------------ */ 24201 .balign 64 24202 .L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */ 24203 /* File: armv5te/alt_stub.S */ 24204 /* 24205 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24206 * any interesting requests and then jump to the real instruction 24207 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24208 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24209 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24210 * bail to the real handler if breakFlags==0. 24211 */ 24212 ldrb r3, [rSELF, #offThread_breakFlags] 24213 adrl lr, dvmAsmInstructionStart + (424 * 64) 24214 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24215 cmp r3, #0 24216 bxeq lr @ nothing to do - jump to real handler 24217 EXPORT_PC() 24218 mov r0, rPC @ arg0 24219 mov r1, rFP @ arg1 24220 mov r2, rSELF @ arg2 24221 b dvmCheckBefore @ (dPC,dFP,self) tail call 24222 24223 /* ------------------------------ */ 24224 .balign 64 24225 .L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */ 24226 /* File: armv5te/alt_stub.S */ 24227 /* 24228 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24229 * any interesting requests and then jump to the real instruction 24230 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24231 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24232 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24233 * bail to the real handler if breakFlags==0. 24234 */ 24235 ldrb r3, [rSELF, #offThread_breakFlags] 24236 adrl lr, dvmAsmInstructionStart + (425 * 64) 24237 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24238 cmp r3, #0 24239 bxeq lr @ nothing to do - jump to real handler 24240 EXPORT_PC() 24241 mov r0, rPC @ arg0 24242 mov r1, rFP @ arg1 24243 mov r2, rSELF @ arg2 24244 b dvmCheckBefore @ (dPC,dFP,self) tail call 24245 24246 /* ------------------------------ */ 24247 .balign 64 24248 .L_ALT_OP_UNUSED_AAFF: /* 0x1aa */ 24249 /* File: armv5te/alt_stub.S */ 24250 /* 24251 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24252 * any interesting requests and then jump to the real instruction 24253 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24254 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24255 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24256 * bail to the real handler if breakFlags==0. 24257 */ 24258 ldrb r3, [rSELF, #offThread_breakFlags] 24259 adrl lr, dvmAsmInstructionStart + (426 * 64) 24260 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24261 cmp r3, #0 24262 bxeq lr @ nothing to do - jump to real handler 24263 EXPORT_PC() 24264 mov r0, rPC @ arg0 24265 mov r1, rFP @ arg1 24266 mov r2, rSELF @ arg2 24267 b dvmCheckBefore @ (dPC,dFP,self) tail call 24268 24269 /* ------------------------------ */ 24270 .balign 64 24271 .L_ALT_OP_UNUSED_ABFF: /* 0x1ab */ 24272 /* File: armv5te/alt_stub.S */ 24273 /* 24274 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24275 * any interesting requests and then jump to the real instruction 24276 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24277 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24278 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24279 * bail to the real handler if breakFlags==0. 24280 */ 24281 ldrb r3, [rSELF, #offThread_breakFlags] 24282 adrl lr, dvmAsmInstructionStart + (427 * 64) 24283 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24284 cmp r3, #0 24285 bxeq lr @ nothing to do - jump to real handler 24286 EXPORT_PC() 24287 mov r0, rPC @ arg0 24288 mov r1, rFP @ arg1 24289 mov r2, rSELF @ arg2 24290 b dvmCheckBefore @ (dPC,dFP,self) tail call 24291 24292 /* ------------------------------ */ 24293 .balign 64 24294 .L_ALT_OP_UNUSED_ACFF: /* 0x1ac */ 24295 /* File: armv5te/alt_stub.S */ 24296 /* 24297 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24298 * any interesting requests and then jump to the real instruction 24299 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24300 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24301 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24302 * bail to the real handler if breakFlags==0. 24303 */ 24304 ldrb r3, [rSELF, #offThread_breakFlags] 24305 adrl lr, dvmAsmInstructionStart + (428 * 64) 24306 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24307 cmp r3, #0 24308 bxeq lr @ nothing to do - jump to real handler 24309 EXPORT_PC() 24310 mov r0, rPC @ arg0 24311 mov r1, rFP @ arg1 24312 mov r2, rSELF @ arg2 24313 b dvmCheckBefore @ (dPC,dFP,self) tail call 24314 24315 /* ------------------------------ */ 24316 .balign 64 24317 .L_ALT_OP_UNUSED_ADFF: /* 0x1ad */ 24318 /* File: armv5te/alt_stub.S */ 24319 /* 24320 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24321 * any interesting requests and then jump to the real instruction 24322 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24323 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24324 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24325 * bail to the real handler if breakFlags==0. 24326 */ 24327 ldrb r3, [rSELF, #offThread_breakFlags] 24328 adrl lr, dvmAsmInstructionStart + (429 * 64) 24329 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24330 cmp r3, #0 24331 bxeq lr @ nothing to do - jump to real handler 24332 EXPORT_PC() 24333 mov r0, rPC @ arg0 24334 mov r1, rFP @ arg1 24335 mov r2, rSELF @ arg2 24336 b dvmCheckBefore @ (dPC,dFP,self) tail call 24337 24338 /* ------------------------------ */ 24339 .balign 64 24340 .L_ALT_OP_UNUSED_AEFF: /* 0x1ae */ 24341 /* File: armv5te/alt_stub.S */ 24342 /* 24343 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24344 * any interesting requests and then jump to the real instruction 24345 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24346 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24347 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24348 * bail to the real handler if breakFlags==0. 24349 */ 24350 ldrb r3, [rSELF, #offThread_breakFlags] 24351 adrl lr, dvmAsmInstructionStart + (430 * 64) 24352 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24353 cmp r3, #0 24354 bxeq lr @ nothing to do - jump to real handler 24355 EXPORT_PC() 24356 mov r0, rPC @ arg0 24357 mov r1, rFP @ arg1 24358 mov r2, rSELF @ arg2 24359 b dvmCheckBefore @ (dPC,dFP,self) tail call 24360 24361 /* ------------------------------ */ 24362 .balign 64 24363 .L_ALT_OP_UNUSED_AFFF: /* 0x1af */ 24364 /* File: armv5te/alt_stub.S */ 24365 /* 24366 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24367 * any interesting requests and then jump to the real instruction 24368 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24369 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24370 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24371 * bail to the real handler if breakFlags==0. 24372 */ 24373 ldrb r3, [rSELF, #offThread_breakFlags] 24374 adrl lr, dvmAsmInstructionStart + (431 * 64) 24375 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24376 cmp r3, #0 24377 bxeq lr @ nothing to do - jump to real handler 24378 EXPORT_PC() 24379 mov r0, rPC @ arg0 24380 mov r1, rFP @ arg1 24381 mov r2, rSELF @ arg2 24382 b dvmCheckBefore @ (dPC,dFP,self) tail call 24383 24384 /* ------------------------------ */ 24385 .balign 64 24386 .L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */ 24387 /* File: armv5te/alt_stub.S */ 24388 /* 24389 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24390 * any interesting requests and then jump to the real instruction 24391 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24392 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24393 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24394 * bail to the real handler if breakFlags==0. 24395 */ 24396 ldrb r3, [rSELF, #offThread_breakFlags] 24397 adrl lr, dvmAsmInstructionStart + (432 * 64) 24398 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24399 cmp r3, #0 24400 bxeq lr @ nothing to do - jump to real handler 24401 EXPORT_PC() 24402 mov r0, rPC @ arg0 24403 mov r1, rFP @ arg1 24404 mov r2, rSELF @ arg2 24405 b dvmCheckBefore @ (dPC,dFP,self) tail call 24406 24407 /* ------------------------------ */ 24408 .balign 64 24409 .L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */ 24410 /* File: armv5te/alt_stub.S */ 24411 /* 24412 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24413 * any interesting requests and then jump to the real instruction 24414 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24415 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24416 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24417 * bail to the real handler if breakFlags==0. 24418 */ 24419 ldrb r3, [rSELF, #offThread_breakFlags] 24420 adrl lr, dvmAsmInstructionStart + (433 * 64) 24421 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24422 cmp r3, #0 24423 bxeq lr @ nothing to do - jump to real handler 24424 EXPORT_PC() 24425 mov r0, rPC @ arg0 24426 mov r1, rFP @ arg1 24427 mov r2, rSELF @ arg2 24428 b dvmCheckBefore @ (dPC,dFP,self) tail call 24429 24430 /* ------------------------------ */ 24431 .balign 64 24432 .L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */ 24433 /* File: armv5te/alt_stub.S */ 24434 /* 24435 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24436 * any interesting requests and then jump to the real instruction 24437 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24438 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24439 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24440 * bail to the real handler if breakFlags==0. 24441 */ 24442 ldrb r3, [rSELF, #offThread_breakFlags] 24443 adrl lr, dvmAsmInstructionStart + (434 * 64) 24444 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24445 cmp r3, #0 24446 bxeq lr @ nothing to do - jump to real handler 24447 EXPORT_PC() 24448 mov r0, rPC @ arg0 24449 mov r1, rFP @ arg1 24450 mov r2, rSELF @ arg2 24451 b dvmCheckBefore @ (dPC,dFP,self) tail call 24452 24453 /* ------------------------------ */ 24454 .balign 64 24455 .L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */ 24456 /* File: armv5te/alt_stub.S */ 24457 /* 24458 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24459 * any interesting requests and then jump to the real instruction 24460 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24461 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24462 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24463 * bail to the real handler if breakFlags==0. 24464 */ 24465 ldrb r3, [rSELF, #offThread_breakFlags] 24466 adrl lr, dvmAsmInstructionStart + (435 * 64) 24467 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24468 cmp r3, #0 24469 bxeq lr @ nothing to do - jump to real handler 24470 EXPORT_PC() 24471 mov r0, rPC @ arg0 24472 mov r1, rFP @ arg1 24473 mov r2, rSELF @ arg2 24474 b dvmCheckBefore @ (dPC,dFP,self) tail call 24475 24476 /* ------------------------------ */ 24477 .balign 64 24478 .L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */ 24479 /* File: armv5te/alt_stub.S */ 24480 /* 24481 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24482 * any interesting requests and then jump to the real instruction 24483 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24484 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24485 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24486 * bail to the real handler if breakFlags==0. 24487 */ 24488 ldrb r3, [rSELF, #offThread_breakFlags] 24489 adrl lr, dvmAsmInstructionStart + (436 * 64) 24490 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24491 cmp r3, #0 24492 bxeq lr @ nothing to do - jump to real handler 24493 EXPORT_PC() 24494 mov r0, rPC @ arg0 24495 mov r1, rFP @ arg1 24496 mov r2, rSELF @ arg2 24497 b dvmCheckBefore @ (dPC,dFP,self) tail call 24498 24499 /* ------------------------------ */ 24500 .balign 64 24501 .L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */ 24502 /* File: armv5te/alt_stub.S */ 24503 /* 24504 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24505 * any interesting requests and then jump to the real instruction 24506 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24507 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24508 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24509 * bail to the real handler if breakFlags==0. 24510 */ 24511 ldrb r3, [rSELF, #offThread_breakFlags] 24512 adrl lr, dvmAsmInstructionStart + (437 * 64) 24513 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24514 cmp r3, #0 24515 bxeq lr @ nothing to do - jump to real handler 24516 EXPORT_PC() 24517 mov r0, rPC @ arg0 24518 mov r1, rFP @ arg1 24519 mov r2, rSELF @ arg2 24520 b dvmCheckBefore @ (dPC,dFP,self) tail call 24521 24522 /* ------------------------------ */ 24523 .balign 64 24524 .L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */ 24525 /* File: armv5te/alt_stub.S */ 24526 /* 24527 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24528 * any interesting requests and then jump to the real instruction 24529 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24530 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24531 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24532 * bail to the real handler if breakFlags==0. 24533 */ 24534 ldrb r3, [rSELF, #offThread_breakFlags] 24535 adrl lr, dvmAsmInstructionStart + (438 * 64) 24536 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24537 cmp r3, #0 24538 bxeq lr @ nothing to do - jump to real handler 24539 EXPORT_PC() 24540 mov r0, rPC @ arg0 24541 mov r1, rFP @ arg1 24542 mov r2, rSELF @ arg2 24543 b dvmCheckBefore @ (dPC,dFP,self) tail call 24544 24545 /* ------------------------------ */ 24546 .balign 64 24547 .L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */ 24548 /* File: armv5te/alt_stub.S */ 24549 /* 24550 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24551 * any interesting requests and then jump to the real instruction 24552 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24553 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24554 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24555 * bail to the real handler if breakFlags==0. 24556 */ 24557 ldrb r3, [rSELF, #offThread_breakFlags] 24558 adrl lr, dvmAsmInstructionStart + (439 * 64) 24559 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24560 cmp r3, #0 24561 bxeq lr @ nothing to do - jump to real handler 24562 EXPORT_PC() 24563 mov r0, rPC @ arg0 24564 mov r1, rFP @ arg1 24565 mov r2, rSELF @ arg2 24566 b dvmCheckBefore @ (dPC,dFP,self) tail call 24567 24568 /* ------------------------------ */ 24569 .balign 64 24570 .L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */ 24571 /* File: armv5te/alt_stub.S */ 24572 /* 24573 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24574 * any interesting requests and then jump to the real instruction 24575 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24576 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24577 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24578 * bail to the real handler if breakFlags==0. 24579 */ 24580 ldrb r3, [rSELF, #offThread_breakFlags] 24581 adrl lr, dvmAsmInstructionStart + (440 * 64) 24582 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24583 cmp r3, #0 24584 bxeq lr @ nothing to do - jump to real handler 24585 EXPORT_PC() 24586 mov r0, rPC @ arg0 24587 mov r1, rFP @ arg1 24588 mov r2, rSELF @ arg2 24589 b dvmCheckBefore @ (dPC,dFP,self) tail call 24590 24591 /* ------------------------------ */ 24592 .balign 64 24593 .L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */ 24594 /* File: armv5te/alt_stub.S */ 24595 /* 24596 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24597 * any interesting requests and then jump to the real instruction 24598 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24599 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24600 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24601 * bail to the real handler if breakFlags==0. 24602 */ 24603 ldrb r3, [rSELF, #offThread_breakFlags] 24604 adrl lr, dvmAsmInstructionStart + (441 * 64) 24605 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24606 cmp r3, #0 24607 bxeq lr @ nothing to do - jump to real handler 24608 EXPORT_PC() 24609 mov r0, rPC @ arg0 24610 mov r1, rFP @ arg1 24611 mov r2, rSELF @ arg2 24612 b dvmCheckBefore @ (dPC,dFP,self) tail call 24613 24614 /* ------------------------------ */ 24615 .balign 64 24616 .L_ALT_OP_UNUSED_BAFF: /* 0x1ba */ 24617 /* File: armv5te/alt_stub.S */ 24618 /* 24619 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24620 * any interesting requests and then jump to the real instruction 24621 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24622 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24623 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24624 * bail to the real handler if breakFlags==0. 24625 */ 24626 ldrb r3, [rSELF, #offThread_breakFlags] 24627 adrl lr, dvmAsmInstructionStart + (442 * 64) 24628 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24629 cmp r3, #0 24630 bxeq lr @ nothing to do - jump to real handler 24631 EXPORT_PC() 24632 mov r0, rPC @ arg0 24633 mov r1, rFP @ arg1 24634 mov r2, rSELF @ arg2 24635 b dvmCheckBefore @ (dPC,dFP,self) tail call 24636 24637 /* ------------------------------ */ 24638 .balign 64 24639 .L_ALT_OP_UNUSED_BBFF: /* 0x1bb */ 24640 /* File: armv5te/alt_stub.S */ 24641 /* 24642 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24643 * any interesting requests and then jump to the real instruction 24644 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24645 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24646 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24647 * bail to the real handler if breakFlags==0. 24648 */ 24649 ldrb r3, [rSELF, #offThread_breakFlags] 24650 adrl lr, dvmAsmInstructionStart + (443 * 64) 24651 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24652 cmp r3, #0 24653 bxeq lr @ nothing to do - jump to real handler 24654 EXPORT_PC() 24655 mov r0, rPC @ arg0 24656 mov r1, rFP @ arg1 24657 mov r2, rSELF @ arg2 24658 b dvmCheckBefore @ (dPC,dFP,self) tail call 24659 24660 /* ------------------------------ */ 24661 .balign 64 24662 .L_ALT_OP_UNUSED_BCFF: /* 0x1bc */ 24663 /* File: armv5te/alt_stub.S */ 24664 /* 24665 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24666 * any interesting requests and then jump to the real instruction 24667 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24668 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24669 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24670 * bail to the real handler if breakFlags==0. 24671 */ 24672 ldrb r3, [rSELF, #offThread_breakFlags] 24673 adrl lr, dvmAsmInstructionStart + (444 * 64) 24674 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24675 cmp r3, #0 24676 bxeq lr @ nothing to do - jump to real handler 24677 EXPORT_PC() 24678 mov r0, rPC @ arg0 24679 mov r1, rFP @ arg1 24680 mov r2, rSELF @ arg2 24681 b dvmCheckBefore @ (dPC,dFP,self) tail call 24682 24683 /* ------------------------------ */ 24684 .balign 64 24685 .L_ALT_OP_UNUSED_BDFF: /* 0x1bd */ 24686 /* File: armv5te/alt_stub.S */ 24687 /* 24688 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24689 * any interesting requests and then jump to the real instruction 24690 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24691 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24692 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24693 * bail to the real handler if breakFlags==0. 24694 */ 24695 ldrb r3, [rSELF, #offThread_breakFlags] 24696 adrl lr, dvmAsmInstructionStart + (445 * 64) 24697 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24698 cmp r3, #0 24699 bxeq lr @ nothing to do - jump to real handler 24700 EXPORT_PC() 24701 mov r0, rPC @ arg0 24702 mov r1, rFP @ arg1 24703 mov r2, rSELF @ arg2 24704 b dvmCheckBefore @ (dPC,dFP,self) tail call 24705 24706 /* ------------------------------ */ 24707 .balign 64 24708 .L_ALT_OP_UNUSED_BEFF: /* 0x1be */ 24709 /* File: armv5te/alt_stub.S */ 24710 /* 24711 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24712 * any interesting requests and then jump to the real instruction 24713 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24714 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24715 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24716 * bail to the real handler if breakFlags==0. 24717 */ 24718 ldrb r3, [rSELF, #offThread_breakFlags] 24719 adrl lr, dvmAsmInstructionStart + (446 * 64) 24720 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24721 cmp r3, #0 24722 bxeq lr @ nothing to do - jump to real handler 24723 EXPORT_PC() 24724 mov r0, rPC @ arg0 24725 mov r1, rFP @ arg1 24726 mov r2, rSELF @ arg2 24727 b dvmCheckBefore @ (dPC,dFP,self) tail call 24728 24729 /* ------------------------------ */ 24730 .balign 64 24731 .L_ALT_OP_UNUSED_BFFF: /* 0x1bf */ 24732 /* File: armv5te/alt_stub.S */ 24733 /* 24734 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24735 * any interesting requests and then jump to the real instruction 24736 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24737 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24738 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24739 * bail to the real handler if breakFlags==0. 24740 */ 24741 ldrb r3, [rSELF, #offThread_breakFlags] 24742 adrl lr, dvmAsmInstructionStart + (447 * 64) 24743 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24744 cmp r3, #0 24745 bxeq lr @ nothing to do - jump to real handler 24746 EXPORT_PC() 24747 mov r0, rPC @ arg0 24748 mov r1, rFP @ arg1 24749 mov r2, rSELF @ arg2 24750 b dvmCheckBefore @ (dPC,dFP,self) tail call 24751 24752 /* ------------------------------ */ 24753 .balign 64 24754 .L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */ 24755 /* File: armv5te/alt_stub.S */ 24756 /* 24757 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24758 * any interesting requests and then jump to the real instruction 24759 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24760 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24761 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24762 * bail to the real handler if breakFlags==0. 24763 */ 24764 ldrb r3, [rSELF, #offThread_breakFlags] 24765 adrl lr, dvmAsmInstructionStart + (448 * 64) 24766 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24767 cmp r3, #0 24768 bxeq lr @ nothing to do - jump to real handler 24769 EXPORT_PC() 24770 mov r0, rPC @ arg0 24771 mov r1, rFP @ arg1 24772 mov r2, rSELF @ arg2 24773 b dvmCheckBefore @ (dPC,dFP,self) tail call 24774 24775 /* ------------------------------ */ 24776 .balign 64 24777 .L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */ 24778 /* File: armv5te/alt_stub.S */ 24779 /* 24780 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24781 * any interesting requests and then jump to the real instruction 24782 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24783 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24784 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24785 * bail to the real handler if breakFlags==0. 24786 */ 24787 ldrb r3, [rSELF, #offThread_breakFlags] 24788 adrl lr, dvmAsmInstructionStart + (449 * 64) 24789 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24790 cmp r3, #0 24791 bxeq lr @ nothing to do - jump to real handler 24792 EXPORT_PC() 24793 mov r0, rPC @ arg0 24794 mov r1, rFP @ arg1 24795 mov r2, rSELF @ arg2 24796 b dvmCheckBefore @ (dPC,dFP,self) tail call 24797 24798 /* ------------------------------ */ 24799 .balign 64 24800 .L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */ 24801 /* File: armv5te/alt_stub.S */ 24802 /* 24803 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24804 * any interesting requests and then jump to the real instruction 24805 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24806 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24807 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24808 * bail to the real handler if breakFlags==0. 24809 */ 24810 ldrb r3, [rSELF, #offThread_breakFlags] 24811 adrl lr, dvmAsmInstructionStart + (450 * 64) 24812 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24813 cmp r3, #0 24814 bxeq lr @ nothing to do - jump to real handler 24815 EXPORT_PC() 24816 mov r0, rPC @ arg0 24817 mov r1, rFP @ arg1 24818 mov r2, rSELF @ arg2 24819 b dvmCheckBefore @ (dPC,dFP,self) tail call 24820 24821 /* ------------------------------ */ 24822 .balign 64 24823 .L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */ 24824 /* File: armv5te/alt_stub.S */ 24825 /* 24826 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24827 * any interesting requests and then jump to the real instruction 24828 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24829 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24830 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24831 * bail to the real handler if breakFlags==0. 24832 */ 24833 ldrb r3, [rSELF, #offThread_breakFlags] 24834 adrl lr, dvmAsmInstructionStart + (451 * 64) 24835 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24836 cmp r3, #0 24837 bxeq lr @ nothing to do - jump to real handler 24838 EXPORT_PC() 24839 mov r0, rPC @ arg0 24840 mov r1, rFP @ arg1 24841 mov r2, rSELF @ arg2 24842 b dvmCheckBefore @ (dPC,dFP,self) tail call 24843 24844 /* ------------------------------ */ 24845 .balign 64 24846 .L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */ 24847 /* File: armv5te/alt_stub.S */ 24848 /* 24849 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24850 * any interesting requests and then jump to the real instruction 24851 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24852 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24853 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24854 * bail to the real handler if breakFlags==0. 24855 */ 24856 ldrb r3, [rSELF, #offThread_breakFlags] 24857 adrl lr, dvmAsmInstructionStart + (452 * 64) 24858 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24859 cmp r3, #0 24860 bxeq lr @ nothing to do - jump to real handler 24861 EXPORT_PC() 24862 mov r0, rPC @ arg0 24863 mov r1, rFP @ arg1 24864 mov r2, rSELF @ arg2 24865 b dvmCheckBefore @ (dPC,dFP,self) tail call 24866 24867 /* ------------------------------ */ 24868 .balign 64 24869 .L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */ 24870 /* File: armv5te/alt_stub.S */ 24871 /* 24872 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24873 * any interesting requests and then jump to the real instruction 24874 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24875 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24876 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24877 * bail to the real handler if breakFlags==0. 24878 */ 24879 ldrb r3, [rSELF, #offThread_breakFlags] 24880 adrl lr, dvmAsmInstructionStart + (453 * 64) 24881 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24882 cmp r3, #0 24883 bxeq lr @ nothing to do - jump to real handler 24884 EXPORT_PC() 24885 mov r0, rPC @ arg0 24886 mov r1, rFP @ arg1 24887 mov r2, rSELF @ arg2 24888 b dvmCheckBefore @ (dPC,dFP,self) tail call 24889 24890 /* ------------------------------ */ 24891 .balign 64 24892 .L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */ 24893 /* File: armv5te/alt_stub.S */ 24894 /* 24895 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24896 * any interesting requests and then jump to the real instruction 24897 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24898 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24899 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24900 * bail to the real handler if breakFlags==0. 24901 */ 24902 ldrb r3, [rSELF, #offThread_breakFlags] 24903 adrl lr, dvmAsmInstructionStart + (454 * 64) 24904 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24905 cmp r3, #0 24906 bxeq lr @ nothing to do - jump to real handler 24907 EXPORT_PC() 24908 mov r0, rPC @ arg0 24909 mov r1, rFP @ arg1 24910 mov r2, rSELF @ arg2 24911 b dvmCheckBefore @ (dPC,dFP,self) tail call 24912 24913 /* ------------------------------ */ 24914 .balign 64 24915 .L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */ 24916 /* File: armv5te/alt_stub.S */ 24917 /* 24918 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24919 * any interesting requests and then jump to the real instruction 24920 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24921 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24922 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24923 * bail to the real handler if breakFlags==0. 24924 */ 24925 ldrb r3, [rSELF, #offThread_breakFlags] 24926 adrl lr, dvmAsmInstructionStart + (455 * 64) 24927 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24928 cmp r3, #0 24929 bxeq lr @ nothing to do - jump to real handler 24930 EXPORT_PC() 24931 mov r0, rPC @ arg0 24932 mov r1, rFP @ arg1 24933 mov r2, rSELF @ arg2 24934 b dvmCheckBefore @ (dPC,dFP,self) tail call 24935 24936 /* ------------------------------ */ 24937 .balign 64 24938 .L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */ 24939 /* File: armv5te/alt_stub.S */ 24940 /* 24941 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24942 * any interesting requests and then jump to the real instruction 24943 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24944 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24945 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24946 * bail to the real handler if breakFlags==0. 24947 */ 24948 ldrb r3, [rSELF, #offThread_breakFlags] 24949 adrl lr, dvmAsmInstructionStart + (456 * 64) 24950 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24951 cmp r3, #0 24952 bxeq lr @ nothing to do - jump to real handler 24953 EXPORT_PC() 24954 mov r0, rPC @ arg0 24955 mov r1, rFP @ arg1 24956 mov r2, rSELF @ arg2 24957 b dvmCheckBefore @ (dPC,dFP,self) tail call 24958 24959 /* ------------------------------ */ 24960 .balign 64 24961 .L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */ 24962 /* File: armv5te/alt_stub.S */ 24963 /* 24964 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24965 * any interesting requests and then jump to the real instruction 24966 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24967 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24968 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24969 * bail to the real handler if breakFlags==0. 24970 */ 24971 ldrb r3, [rSELF, #offThread_breakFlags] 24972 adrl lr, dvmAsmInstructionStart + (457 * 64) 24973 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24974 cmp r3, #0 24975 bxeq lr @ nothing to do - jump to real handler 24976 EXPORT_PC() 24977 mov r0, rPC @ arg0 24978 mov r1, rFP @ arg1 24979 mov r2, rSELF @ arg2 24980 b dvmCheckBefore @ (dPC,dFP,self) tail call 24981 24982 /* ------------------------------ */ 24983 .balign 64 24984 .L_ALT_OP_UNUSED_CAFF: /* 0x1ca */ 24985 /* File: armv5te/alt_stub.S */ 24986 /* 24987 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 24988 * any interesting requests and then jump to the real instruction 24989 * handler. Note that the call to dvmCheckBefore is done as a tail call. 24990 * rIBASE updates won't be seen until a refresh, and we can tell we have a 24991 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 24992 * bail to the real handler if breakFlags==0. 24993 */ 24994 ldrb r3, [rSELF, #offThread_breakFlags] 24995 adrl lr, dvmAsmInstructionStart + (458 * 64) 24996 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 24997 cmp r3, #0 24998 bxeq lr @ nothing to do - jump to real handler 24999 EXPORT_PC() 25000 mov r0, rPC @ arg0 25001 mov r1, rFP @ arg1 25002 mov r2, rSELF @ arg2 25003 b dvmCheckBefore @ (dPC,dFP,self) tail call 25004 25005 /* ------------------------------ */ 25006 .balign 64 25007 .L_ALT_OP_UNUSED_CBFF: /* 0x1cb */ 25008 /* File: armv5te/alt_stub.S */ 25009 /* 25010 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25011 * any interesting requests and then jump to the real instruction 25012 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25013 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25014 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25015 * bail to the real handler if breakFlags==0. 25016 */ 25017 ldrb r3, [rSELF, #offThread_breakFlags] 25018 adrl lr, dvmAsmInstructionStart + (459 * 64) 25019 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25020 cmp r3, #0 25021 bxeq lr @ nothing to do - jump to real handler 25022 EXPORT_PC() 25023 mov r0, rPC @ arg0 25024 mov r1, rFP @ arg1 25025 mov r2, rSELF @ arg2 25026 b dvmCheckBefore @ (dPC,dFP,self) tail call 25027 25028 /* ------------------------------ */ 25029 .balign 64 25030 .L_ALT_OP_UNUSED_CCFF: /* 0x1cc */ 25031 /* File: armv5te/alt_stub.S */ 25032 /* 25033 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25034 * any interesting requests and then jump to the real instruction 25035 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25036 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25037 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25038 * bail to the real handler if breakFlags==0. 25039 */ 25040 ldrb r3, [rSELF, #offThread_breakFlags] 25041 adrl lr, dvmAsmInstructionStart + (460 * 64) 25042 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25043 cmp r3, #0 25044 bxeq lr @ nothing to do - jump to real handler 25045 EXPORT_PC() 25046 mov r0, rPC @ arg0 25047 mov r1, rFP @ arg1 25048 mov r2, rSELF @ arg2 25049 b dvmCheckBefore @ (dPC,dFP,self) tail call 25050 25051 /* ------------------------------ */ 25052 .balign 64 25053 .L_ALT_OP_UNUSED_CDFF: /* 0x1cd */ 25054 /* File: armv5te/alt_stub.S */ 25055 /* 25056 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25057 * any interesting requests and then jump to the real instruction 25058 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25059 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25060 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25061 * bail to the real handler if breakFlags==0. 25062 */ 25063 ldrb r3, [rSELF, #offThread_breakFlags] 25064 adrl lr, dvmAsmInstructionStart + (461 * 64) 25065 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25066 cmp r3, #0 25067 bxeq lr @ nothing to do - jump to real handler 25068 EXPORT_PC() 25069 mov r0, rPC @ arg0 25070 mov r1, rFP @ arg1 25071 mov r2, rSELF @ arg2 25072 b dvmCheckBefore @ (dPC,dFP,self) tail call 25073 25074 /* ------------------------------ */ 25075 .balign 64 25076 .L_ALT_OP_UNUSED_CEFF: /* 0x1ce */ 25077 /* File: armv5te/alt_stub.S */ 25078 /* 25079 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25080 * any interesting requests and then jump to the real instruction 25081 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25082 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25083 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25084 * bail to the real handler if breakFlags==0. 25085 */ 25086 ldrb r3, [rSELF, #offThread_breakFlags] 25087 adrl lr, dvmAsmInstructionStart + (462 * 64) 25088 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25089 cmp r3, #0 25090 bxeq lr @ nothing to do - jump to real handler 25091 EXPORT_PC() 25092 mov r0, rPC @ arg0 25093 mov r1, rFP @ arg1 25094 mov r2, rSELF @ arg2 25095 b dvmCheckBefore @ (dPC,dFP,self) tail call 25096 25097 /* ------------------------------ */ 25098 .balign 64 25099 .L_ALT_OP_UNUSED_CFFF: /* 0x1cf */ 25100 /* File: armv5te/alt_stub.S */ 25101 /* 25102 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25103 * any interesting requests and then jump to the real instruction 25104 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25105 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25106 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25107 * bail to the real handler if breakFlags==0. 25108 */ 25109 ldrb r3, [rSELF, #offThread_breakFlags] 25110 adrl lr, dvmAsmInstructionStart + (463 * 64) 25111 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25112 cmp r3, #0 25113 bxeq lr @ nothing to do - jump to real handler 25114 EXPORT_PC() 25115 mov r0, rPC @ arg0 25116 mov r1, rFP @ arg1 25117 mov r2, rSELF @ arg2 25118 b dvmCheckBefore @ (dPC,dFP,self) tail call 25119 25120 /* ------------------------------ */ 25121 .balign 64 25122 .L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */ 25123 /* File: armv5te/alt_stub.S */ 25124 /* 25125 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25126 * any interesting requests and then jump to the real instruction 25127 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25128 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25129 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25130 * bail to the real handler if breakFlags==0. 25131 */ 25132 ldrb r3, [rSELF, #offThread_breakFlags] 25133 adrl lr, dvmAsmInstructionStart + (464 * 64) 25134 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25135 cmp r3, #0 25136 bxeq lr @ nothing to do - jump to real handler 25137 EXPORT_PC() 25138 mov r0, rPC @ arg0 25139 mov r1, rFP @ arg1 25140 mov r2, rSELF @ arg2 25141 b dvmCheckBefore @ (dPC,dFP,self) tail call 25142 25143 /* ------------------------------ */ 25144 .balign 64 25145 .L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */ 25146 /* File: armv5te/alt_stub.S */ 25147 /* 25148 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25149 * any interesting requests and then jump to the real instruction 25150 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25151 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25152 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25153 * bail to the real handler if breakFlags==0. 25154 */ 25155 ldrb r3, [rSELF, #offThread_breakFlags] 25156 adrl lr, dvmAsmInstructionStart + (465 * 64) 25157 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25158 cmp r3, #0 25159 bxeq lr @ nothing to do - jump to real handler 25160 EXPORT_PC() 25161 mov r0, rPC @ arg0 25162 mov r1, rFP @ arg1 25163 mov r2, rSELF @ arg2 25164 b dvmCheckBefore @ (dPC,dFP,self) tail call 25165 25166 /* ------------------------------ */ 25167 .balign 64 25168 .L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */ 25169 /* File: armv5te/alt_stub.S */ 25170 /* 25171 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25172 * any interesting requests and then jump to the real instruction 25173 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25174 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25175 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25176 * bail to the real handler if breakFlags==0. 25177 */ 25178 ldrb r3, [rSELF, #offThread_breakFlags] 25179 adrl lr, dvmAsmInstructionStart + (466 * 64) 25180 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25181 cmp r3, #0 25182 bxeq lr @ nothing to do - jump to real handler 25183 EXPORT_PC() 25184 mov r0, rPC @ arg0 25185 mov r1, rFP @ arg1 25186 mov r2, rSELF @ arg2 25187 b dvmCheckBefore @ (dPC,dFP,self) tail call 25188 25189 /* ------------------------------ */ 25190 .balign 64 25191 .L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */ 25192 /* File: armv5te/alt_stub.S */ 25193 /* 25194 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25195 * any interesting requests and then jump to the real instruction 25196 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25197 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25198 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25199 * bail to the real handler if breakFlags==0. 25200 */ 25201 ldrb r3, [rSELF, #offThread_breakFlags] 25202 adrl lr, dvmAsmInstructionStart + (467 * 64) 25203 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25204 cmp r3, #0 25205 bxeq lr @ nothing to do - jump to real handler 25206 EXPORT_PC() 25207 mov r0, rPC @ arg0 25208 mov r1, rFP @ arg1 25209 mov r2, rSELF @ arg2 25210 b dvmCheckBefore @ (dPC,dFP,self) tail call 25211 25212 /* ------------------------------ */ 25213 .balign 64 25214 .L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */ 25215 /* File: armv5te/alt_stub.S */ 25216 /* 25217 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25218 * any interesting requests and then jump to the real instruction 25219 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25220 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25221 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25222 * bail to the real handler if breakFlags==0. 25223 */ 25224 ldrb r3, [rSELF, #offThread_breakFlags] 25225 adrl lr, dvmAsmInstructionStart + (468 * 64) 25226 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25227 cmp r3, #0 25228 bxeq lr @ nothing to do - jump to real handler 25229 EXPORT_PC() 25230 mov r0, rPC @ arg0 25231 mov r1, rFP @ arg1 25232 mov r2, rSELF @ arg2 25233 b dvmCheckBefore @ (dPC,dFP,self) tail call 25234 25235 /* ------------------------------ */ 25236 .balign 64 25237 .L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */ 25238 /* File: armv5te/alt_stub.S */ 25239 /* 25240 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25241 * any interesting requests and then jump to the real instruction 25242 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25243 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25244 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25245 * bail to the real handler if breakFlags==0. 25246 */ 25247 ldrb r3, [rSELF, #offThread_breakFlags] 25248 adrl lr, dvmAsmInstructionStart + (469 * 64) 25249 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25250 cmp r3, #0 25251 bxeq lr @ nothing to do - jump to real handler 25252 EXPORT_PC() 25253 mov r0, rPC @ arg0 25254 mov r1, rFP @ arg1 25255 mov r2, rSELF @ arg2 25256 b dvmCheckBefore @ (dPC,dFP,self) tail call 25257 25258 /* ------------------------------ */ 25259 .balign 64 25260 .L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */ 25261 /* File: armv5te/alt_stub.S */ 25262 /* 25263 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25264 * any interesting requests and then jump to the real instruction 25265 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25266 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25267 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25268 * bail to the real handler if breakFlags==0. 25269 */ 25270 ldrb r3, [rSELF, #offThread_breakFlags] 25271 adrl lr, dvmAsmInstructionStart + (470 * 64) 25272 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25273 cmp r3, #0 25274 bxeq lr @ nothing to do - jump to real handler 25275 EXPORT_PC() 25276 mov r0, rPC @ arg0 25277 mov r1, rFP @ arg1 25278 mov r2, rSELF @ arg2 25279 b dvmCheckBefore @ (dPC,dFP,self) tail call 25280 25281 /* ------------------------------ */ 25282 .balign 64 25283 .L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */ 25284 /* File: armv5te/alt_stub.S */ 25285 /* 25286 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25287 * any interesting requests and then jump to the real instruction 25288 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25289 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25290 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25291 * bail to the real handler if breakFlags==0. 25292 */ 25293 ldrb r3, [rSELF, #offThread_breakFlags] 25294 adrl lr, dvmAsmInstructionStart + (471 * 64) 25295 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25296 cmp r3, #0 25297 bxeq lr @ nothing to do - jump to real handler 25298 EXPORT_PC() 25299 mov r0, rPC @ arg0 25300 mov r1, rFP @ arg1 25301 mov r2, rSELF @ arg2 25302 b dvmCheckBefore @ (dPC,dFP,self) tail call 25303 25304 /* ------------------------------ */ 25305 .balign 64 25306 .L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */ 25307 /* File: armv5te/alt_stub.S */ 25308 /* 25309 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25310 * any interesting requests and then jump to the real instruction 25311 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25312 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25313 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25314 * bail to the real handler if breakFlags==0. 25315 */ 25316 ldrb r3, [rSELF, #offThread_breakFlags] 25317 adrl lr, dvmAsmInstructionStart + (472 * 64) 25318 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25319 cmp r3, #0 25320 bxeq lr @ nothing to do - jump to real handler 25321 EXPORT_PC() 25322 mov r0, rPC @ arg0 25323 mov r1, rFP @ arg1 25324 mov r2, rSELF @ arg2 25325 b dvmCheckBefore @ (dPC,dFP,self) tail call 25326 25327 /* ------------------------------ */ 25328 .balign 64 25329 .L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */ 25330 /* File: armv5te/alt_stub.S */ 25331 /* 25332 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25333 * any interesting requests and then jump to the real instruction 25334 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25335 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25336 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25337 * bail to the real handler if breakFlags==0. 25338 */ 25339 ldrb r3, [rSELF, #offThread_breakFlags] 25340 adrl lr, dvmAsmInstructionStart + (473 * 64) 25341 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25342 cmp r3, #0 25343 bxeq lr @ nothing to do - jump to real handler 25344 EXPORT_PC() 25345 mov r0, rPC @ arg0 25346 mov r1, rFP @ arg1 25347 mov r2, rSELF @ arg2 25348 b dvmCheckBefore @ (dPC,dFP,self) tail call 25349 25350 /* ------------------------------ */ 25351 .balign 64 25352 .L_ALT_OP_UNUSED_DAFF: /* 0x1da */ 25353 /* File: armv5te/alt_stub.S */ 25354 /* 25355 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25356 * any interesting requests and then jump to the real instruction 25357 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25358 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25359 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25360 * bail to the real handler if breakFlags==0. 25361 */ 25362 ldrb r3, [rSELF, #offThread_breakFlags] 25363 adrl lr, dvmAsmInstructionStart + (474 * 64) 25364 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25365 cmp r3, #0 25366 bxeq lr @ nothing to do - jump to real handler 25367 EXPORT_PC() 25368 mov r0, rPC @ arg0 25369 mov r1, rFP @ arg1 25370 mov r2, rSELF @ arg2 25371 b dvmCheckBefore @ (dPC,dFP,self) tail call 25372 25373 /* ------------------------------ */ 25374 .balign 64 25375 .L_ALT_OP_UNUSED_DBFF: /* 0x1db */ 25376 /* File: armv5te/alt_stub.S */ 25377 /* 25378 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25379 * any interesting requests and then jump to the real instruction 25380 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25381 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25382 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25383 * bail to the real handler if breakFlags==0. 25384 */ 25385 ldrb r3, [rSELF, #offThread_breakFlags] 25386 adrl lr, dvmAsmInstructionStart + (475 * 64) 25387 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25388 cmp r3, #0 25389 bxeq lr @ nothing to do - jump to real handler 25390 EXPORT_PC() 25391 mov r0, rPC @ arg0 25392 mov r1, rFP @ arg1 25393 mov r2, rSELF @ arg2 25394 b dvmCheckBefore @ (dPC,dFP,self) tail call 25395 25396 /* ------------------------------ */ 25397 .balign 64 25398 .L_ALT_OP_UNUSED_DCFF: /* 0x1dc */ 25399 /* File: armv5te/alt_stub.S */ 25400 /* 25401 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25402 * any interesting requests and then jump to the real instruction 25403 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25404 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25405 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25406 * bail to the real handler if breakFlags==0. 25407 */ 25408 ldrb r3, [rSELF, #offThread_breakFlags] 25409 adrl lr, dvmAsmInstructionStart + (476 * 64) 25410 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25411 cmp r3, #0 25412 bxeq lr @ nothing to do - jump to real handler 25413 EXPORT_PC() 25414 mov r0, rPC @ arg0 25415 mov r1, rFP @ arg1 25416 mov r2, rSELF @ arg2 25417 b dvmCheckBefore @ (dPC,dFP,self) tail call 25418 25419 /* ------------------------------ */ 25420 .balign 64 25421 .L_ALT_OP_UNUSED_DDFF: /* 0x1dd */ 25422 /* File: armv5te/alt_stub.S */ 25423 /* 25424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25425 * any interesting requests and then jump to the real instruction 25426 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25427 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25429 * bail to the real handler if breakFlags==0. 25430 */ 25431 ldrb r3, [rSELF, #offThread_breakFlags] 25432 adrl lr, dvmAsmInstructionStart + (477 * 64) 25433 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25434 cmp r3, #0 25435 bxeq lr @ nothing to do - jump to real handler 25436 EXPORT_PC() 25437 mov r0, rPC @ arg0 25438 mov r1, rFP @ arg1 25439 mov r2, rSELF @ arg2 25440 b dvmCheckBefore @ (dPC,dFP,self) tail call 25441 25442 /* ------------------------------ */ 25443 .balign 64 25444 .L_ALT_OP_UNUSED_DEFF: /* 0x1de */ 25445 /* File: armv5te/alt_stub.S */ 25446 /* 25447 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25448 * any interesting requests and then jump to the real instruction 25449 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25450 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25451 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25452 * bail to the real handler if breakFlags==0. 25453 */ 25454 ldrb r3, [rSELF, #offThread_breakFlags] 25455 adrl lr, dvmAsmInstructionStart + (478 * 64) 25456 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25457 cmp r3, #0 25458 bxeq lr @ nothing to do - jump to real handler 25459 EXPORT_PC() 25460 mov r0, rPC @ arg0 25461 mov r1, rFP @ arg1 25462 mov r2, rSELF @ arg2 25463 b dvmCheckBefore @ (dPC,dFP,self) tail call 25464 25465 /* ------------------------------ */ 25466 .balign 64 25467 .L_ALT_OP_UNUSED_DFFF: /* 0x1df */ 25468 /* File: armv5te/alt_stub.S */ 25469 /* 25470 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25471 * any interesting requests and then jump to the real instruction 25472 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25473 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25474 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25475 * bail to the real handler if breakFlags==0. 25476 */ 25477 ldrb r3, [rSELF, #offThread_breakFlags] 25478 adrl lr, dvmAsmInstructionStart + (479 * 64) 25479 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25480 cmp r3, #0 25481 bxeq lr @ nothing to do - jump to real handler 25482 EXPORT_PC() 25483 mov r0, rPC @ arg0 25484 mov r1, rFP @ arg1 25485 mov r2, rSELF @ arg2 25486 b dvmCheckBefore @ (dPC,dFP,self) tail call 25487 25488 /* ------------------------------ */ 25489 .balign 64 25490 .L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */ 25491 /* File: armv5te/alt_stub.S */ 25492 /* 25493 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25494 * any interesting requests and then jump to the real instruction 25495 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25496 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25497 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25498 * bail to the real handler if breakFlags==0. 25499 */ 25500 ldrb r3, [rSELF, #offThread_breakFlags] 25501 adrl lr, dvmAsmInstructionStart + (480 * 64) 25502 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25503 cmp r3, #0 25504 bxeq lr @ nothing to do - jump to real handler 25505 EXPORT_PC() 25506 mov r0, rPC @ arg0 25507 mov r1, rFP @ arg1 25508 mov r2, rSELF @ arg2 25509 b dvmCheckBefore @ (dPC,dFP,self) tail call 25510 25511 /* ------------------------------ */ 25512 .balign 64 25513 .L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */ 25514 /* File: armv5te/alt_stub.S */ 25515 /* 25516 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25517 * any interesting requests and then jump to the real instruction 25518 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25519 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25520 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25521 * bail to the real handler if breakFlags==0. 25522 */ 25523 ldrb r3, [rSELF, #offThread_breakFlags] 25524 adrl lr, dvmAsmInstructionStart + (481 * 64) 25525 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25526 cmp r3, #0 25527 bxeq lr @ nothing to do - jump to real handler 25528 EXPORT_PC() 25529 mov r0, rPC @ arg0 25530 mov r1, rFP @ arg1 25531 mov r2, rSELF @ arg2 25532 b dvmCheckBefore @ (dPC,dFP,self) tail call 25533 25534 /* ------------------------------ */ 25535 .balign 64 25536 .L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */ 25537 /* File: armv5te/alt_stub.S */ 25538 /* 25539 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25540 * any interesting requests and then jump to the real instruction 25541 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25542 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25543 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25544 * bail to the real handler if breakFlags==0. 25545 */ 25546 ldrb r3, [rSELF, #offThread_breakFlags] 25547 adrl lr, dvmAsmInstructionStart + (482 * 64) 25548 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25549 cmp r3, #0 25550 bxeq lr @ nothing to do - jump to real handler 25551 EXPORT_PC() 25552 mov r0, rPC @ arg0 25553 mov r1, rFP @ arg1 25554 mov r2, rSELF @ arg2 25555 b dvmCheckBefore @ (dPC,dFP,self) tail call 25556 25557 /* ------------------------------ */ 25558 .balign 64 25559 .L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */ 25560 /* File: armv5te/alt_stub.S */ 25561 /* 25562 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25563 * any interesting requests and then jump to the real instruction 25564 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25565 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25566 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25567 * bail to the real handler if breakFlags==0. 25568 */ 25569 ldrb r3, [rSELF, #offThread_breakFlags] 25570 adrl lr, dvmAsmInstructionStart + (483 * 64) 25571 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25572 cmp r3, #0 25573 bxeq lr @ nothing to do - jump to real handler 25574 EXPORT_PC() 25575 mov r0, rPC @ arg0 25576 mov r1, rFP @ arg1 25577 mov r2, rSELF @ arg2 25578 b dvmCheckBefore @ (dPC,dFP,self) tail call 25579 25580 /* ------------------------------ */ 25581 .balign 64 25582 .L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */ 25583 /* File: armv5te/alt_stub.S */ 25584 /* 25585 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25586 * any interesting requests and then jump to the real instruction 25587 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25588 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25589 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25590 * bail to the real handler if breakFlags==0. 25591 */ 25592 ldrb r3, [rSELF, #offThread_breakFlags] 25593 adrl lr, dvmAsmInstructionStart + (484 * 64) 25594 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25595 cmp r3, #0 25596 bxeq lr @ nothing to do - jump to real handler 25597 EXPORT_PC() 25598 mov r0, rPC @ arg0 25599 mov r1, rFP @ arg1 25600 mov r2, rSELF @ arg2 25601 b dvmCheckBefore @ (dPC,dFP,self) tail call 25602 25603 /* ------------------------------ */ 25604 .balign 64 25605 .L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */ 25606 /* File: armv5te/alt_stub.S */ 25607 /* 25608 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25609 * any interesting requests and then jump to the real instruction 25610 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25611 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25612 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25613 * bail to the real handler if breakFlags==0. 25614 */ 25615 ldrb r3, [rSELF, #offThread_breakFlags] 25616 adrl lr, dvmAsmInstructionStart + (485 * 64) 25617 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25618 cmp r3, #0 25619 bxeq lr @ nothing to do - jump to real handler 25620 EXPORT_PC() 25621 mov r0, rPC @ arg0 25622 mov r1, rFP @ arg1 25623 mov r2, rSELF @ arg2 25624 b dvmCheckBefore @ (dPC,dFP,self) tail call 25625 25626 /* ------------------------------ */ 25627 .balign 64 25628 .L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */ 25629 /* File: armv5te/alt_stub.S */ 25630 /* 25631 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25632 * any interesting requests and then jump to the real instruction 25633 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25634 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25635 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25636 * bail to the real handler if breakFlags==0. 25637 */ 25638 ldrb r3, [rSELF, #offThread_breakFlags] 25639 adrl lr, dvmAsmInstructionStart + (486 * 64) 25640 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25641 cmp r3, #0 25642 bxeq lr @ nothing to do - jump to real handler 25643 EXPORT_PC() 25644 mov r0, rPC @ arg0 25645 mov r1, rFP @ arg1 25646 mov r2, rSELF @ arg2 25647 b dvmCheckBefore @ (dPC,dFP,self) tail call 25648 25649 /* ------------------------------ */ 25650 .balign 64 25651 .L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */ 25652 /* File: armv5te/alt_stub.S */ 25653 /* 25654 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25655 * any interesting requests and then jump to the real instruction 25656 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25657 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25658 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25659 * bail to the real handler if breakFlags==0. 25660 */ 25661 ldrb r3, [rSELF, #offThread_breakFlags] 25662 adrl lr, dvmAsmInstructionStart + (487 * 64) 25663 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25664 cmp r3, #0 25665 bxeq lr @ nothing to do - jump to real handler 25666 EXPORT_PC() 25667 mov r0, rPC @ arg0 25668 mov r1, rFP @ arg1 25669 mov r2, rSELF @ arg2 25670 b dvmCheckBefore @ (dPC,dFP,self) tail call 25671 25672 /* ------------------------------ */ 25673 .balign 64 25674 .L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */ 25675 /* File: armv5te/alt_stub.S */ 25676 /* 25677 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25678 * any interesting requests and then jump to the real instruction 25679 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25680 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25681 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25682 * bail to the real handler if breakFlags==0. 25683 */ 25684 ldrb r3, [rSELF, #offThread_breakFlags] 25685 adrl lr, dvmAsmInstructionStart + (488 * 64) 25686 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25687 cmp r3, #0 25688 bxeq lr @ nothing to do - jump to real handler 25689 EXPORT_PC() 25690 mov r0, rPC @ arg0 25691 mov r1, rFP @ arg1 25692 mov r2, rSELF @ arg2 25693 b dvmCheckBefore @ (dPC,dFP,self) tail call 25694 25695 /* ------------------------------ */ 25696 .balign 64 25697 .L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */ 25698 /* File: armv5te/alt_stub.S */ 25699 /* 25700 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25701 * any interesting requests and then jump to the real instruction 25702 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25703 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25704 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25705 * bail to the real handler if breakFlags==0. 25706 */ 25707 ldrb r3, [rSELF, #offThread_breakFlags] 25708 adrl lr, dvmAsmInstructionStart + (489 * 64) 25709 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25710 cmp r3, #0 25711 bxeq lr @ nothing to do - jump to real handler 25712 EXPORT_PC() 25713 mov r0, rPC @ arg0 25714 mov r1, rFP @ arg1 25715 mov r2, rSELF @ arg2 25716 b dvmCheckBefore @ (dPC,dFP,self) tail call 25717 25718 /* ------------------------------ */ 25719 .balign 64 25720 .L_ALT_OP_UNUSED_EAFF: /* 0x1ea */ 25721 /* File: armv5te/alt_stub.S */ 25722 /* 25723 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25724 * any interesting requests and then jump to the real instruction 25725 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25726 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25727 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25728 * bail to the real handler if breakFlags==0. 25729 */ 25730 ldrb r3, [rSELF, #offThread_breakFlags] 25731 adrl lr, dvmAsmInstructionStart + (490 * 64) 25732 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25733 cmp r3, #0 25734 bxeq lr @ nothing to do - jump to real handler 25735 EXPORT_PC() 25736 mov r0, rPC @ arg0 25737 mov r1, rFP @ arg1 25738 mov r2, rSELF @ arg2 25739 b dvmCheckBefore @ (dPC,dFP,self) tail call 25740 25741 /* ------------------------------ */ 25742 .balign 64 25743 .L_ALT_OP_UNUSED_EBFF: /* 0x1eb */ 25744 /* File: armv5te/alt_stub.S */ 25745 /* 25746 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25747 * any interesting requests and then jump to the real instruction 25748 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25749 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25750 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25751 * bail to the real handler if breakFlags==0. 25752 */ 25753 ldrb r3, [rSELF, #offThread_breakFlags] 25754 adrl lr, dvmAsmInstructionStart + (491 * 64) 25755 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25756 cmp r3, #0 25757 bxeq lr @ nothing to do - jump to real handler 25758 EXPORT_PC() 25759 mov r0, rPC @ arg0 25760 mov r1, rFP @ arg1 25761 mov r2, rSELF @ arg2 25762 b dvmCheckBefore @ (dPC,dFP,self) tail call 25763 25764 /* ------------------------------ */ 25765 .balign 64 25766 .L_ALT_OP_UNUSED_ECFF: /* 0x1ec */ 25767 /* File: armv5te/alt_stub.S */ 25768 /* 25769 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25770 * any interesting requests and then jump to the real instruction 25771 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25772 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25773 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25774 * bail to the real handler if breakFlags==0. 25775 */ 25776 ldrb r3, [rSELF, #offThread_breakFlags] 25777 adrl lr, dvmAsmInstructionStart + (492 * 64) 25778 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25779 cmp r3, #0 25780 bxeq lr @ nothing to do - jump to real handler 25781 EXPORT_PC() 25782 mov r0, rPC @ arg0 25783 mov r1, rFP @ arg1 25784 mov r2, rSELF @ arg2 25785 b dvmCheckBefore @ (dPC,dFP,self) tail call 25786 25787 /* ------------------------------ */ 25788 .balign 64 25789 .L_ALT_OP_UNUSED_EDFF: /* 0x1ed */ 25790 /* File: armv5te/alt_stub.S */ 25791 /* 25792 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25793 * any interesting requests and then jump to the real instruction 25794 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25795 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25796 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25797 * bail to the real handler if breakFlags==0. 25798 */ 25799 ldrb r3, [rSELF, #offThread_breakFlags] 25800 adrl lr, dvmAsmInstructionStart + (493 * 64) 25801 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25802 cmp r3, #0 25803 bxeq lr @ nothing to do - jump to real handler 25804 EXPORT_PC() 25805 mov r0, rPC @ arg0 25806 mov r1, rFP @ arg1 25807 mov r2, rSELF @ arg2 25808 b dvmCheckBefore @ (dPC,dFP,self) tail call 25809 25810 /* ------------------------------ */ 25811 .balign 64 25812 .L_ALT_OP_UNUSED_EEFF: /* 0x1ee */ 25813 /* File: armv5te/alt_stub.S */ 25814 /* 25815 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25816 * any interesting requests and then jump to the real instruction 25817 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25818 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25819 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25820 * bail to the real handler if breakFlags==0. 25821 */ 25822 ldrb r3, [rSELF, #offThread_breakFlags] 25823 adrl lr, dvmAsmInstructionStart + (494 * 64) 25824 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25825 cmp r3, #0 25826 bxeq lr @ nothing to do - jump to real handler 25827 EXPORT_PC() 25828 mov r0, rPC @ arg0 25829 mov r1, rFP @ arg1 25830 mov r2, rSELF @ arg2 25831 b dvmCheckBefore @ (dPC,dFP,self) tail call 25832 25833 /* ------------------------------ */ 25834 .balign 64 25835 .L_ALT_OP_UNUSED_EFFF: /* 0x1ef */ 25836 /* File: armv5te/alt_stub.S */ 25837 /* 25838 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25839 * any interesting requests and then jump to the real instruction 25840 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25841 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25842 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25843 * bail to the real handler if breakFlags==0. 25844 */ 25845 ldrb r3, [rSELF, #offThread_breakFlags] 25846 adrl lr, dvmAsmInstructionStart + (495 * 64) 25847 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25848 cmp r3, #0 25849 bxeq lr @ nothing to do - jump to real handler 25850 EXPORT_PC() 25851 mov r0, rPC @ arg0 25852 mov r1, rFP @ arg1 25853 mov r2, rSELF @ arg2 25854 b dvmCheckBefore @ (dPC,dFP,self) tail call 25855 25856 /* ------------------------------ */ 25857 .balign 64 25858 .L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */ 25859 /* File: armv5te/alt_stub.S */ 25860 /* 25861 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25862 * any interesting requests and then jump to the real instruction 25863 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25864 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25865 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25866 * bail to the real handler if breakFlags==0. 25867 */ 25868 ldrb r3, [rSELF, #offThread_breakFlags] 25869 adrl lr, dvmAsmInstructionStart + (496 * 64) 25870 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25871 cmp r3, #0 25872 bxeq lr @ nothing to do - jump to real handler 25873 EXPORT_PC() 25874 mov r0, rPC @ arg0 25875 mov r1, rFP @ arg1 25876 mov r2, rSELF @ arg2 25877 b dvmCheckBefore @ (dPC,dFP,self) tail call 25878 25879 /* ------------------------------ */ 25880 .balign 64 25881 .L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */ 25882 /* File: armv5te/alt_stub.S */ 25883 /* 25884 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25885 * any interesting requests and then jump to the real instruction 25886 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25887 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25888 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25889 * bail to the real handler if breakFlags==0. 25890 */ 25891 ldrb r3, [rSELF, #offThread_breakFlags] 25892 adrl lr, dvmAsmInstructionStart + (497 * 64) 25893 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25894 cmp r3, #0 25895 bxeq lr @ nothing to do - jump to real handler 25896 EXPORT_PC() 25897 mov r0, rPC @ arg0 25898 mov r1, rFP @ arg1 25899 mov r2, rSELF @ arg2 25900 b dvmCheckBefore @ (dPC,dFP,self) tail call 25901 25902 /* ------------------------------ */ 25903 .balign 64 25904 .L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */ 25905 /* File: armv5te/alt_stub.S */ 25906 /* 25907 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25908 * any interesting requests and then jump to the real instruction 25909 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25910 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25911 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25912 * bail to the real handler if breakFlags==0. 25913 */ 25914 ldrb r3, [rSELF, #offThread_breakFlags] 25915 adrl lr, dvmAsmInstructionStart + (498 * 64) 25916 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25917 cmp r3, #0 25918 bxeq lr @ nothing to do - jump to real handler 25919 EXPORT_PC() 25920 mov r0, rPC @ arg0 25921 mov r1, rFP @ arg1 25922 mov r2, rSELF @ arg2 25923 b dvmCheckBefore @ (dPC,dFP,self) tail call 25924 25925 /* ------------------------------ */ 25926 .balign 64 25927 .L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */ 25928 /* File: armv5te/alt_stub.S */ 25929 /* 25930 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25931 * any interesting requests and then jump to the real instruction 25932 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25933 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25934 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25935 * bail to the real handler if breakFlags==0. 25936 */ 25937 ldrb r3, [rSELF, #offThread_breakFlags] 25938 adrl lr, dvmAsmInstructionStart + (499 * 64) 25939 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25940 cmp r3, #0 25941 bxeq lr @ nothing to do - jump to real handler 25942 EXPORT_PC() 25943 mov r0, rPC @ arg0 25944 mov r1, rFP @ arg1 25945 mov r2, rSELF @ arg2 25946 b dvmCheckBefore @ (dPC,dFP,self) tail call 25947 25948 /* ------------------------------ */ 25949 .balign 64 25950 .L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */ 25951 /* File: armv5te/alt_stub.S */ 25952 /* 25953 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25954 * any interesting requests and then jump to the real instruction 25955 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25956 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25957 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25958 * bail to the real handler if breakFlags==0. 25959 */ 25960 ldrb r3, [rSELF, #offThread_breakFlags] 25961 adrl lr, dvmAsmInstructionStart + (500 * 64) 25962 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25963 cmp r3, #0 25964 bxeq lr @ nothing to do - jump to real handler 25965 EXPORT_PC() 25966 mov r0, rPC @ arg0 25967 mov r1, rFP @ arg1 25968 mov r2, rSELF @ arg2 25969 b dvmCheckBefore @ (dPC,dFP,self) tail call 25970 25971 /* ------------------------------ */ 25972 .balign 64 25973 .L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */ 25974 /* File: armv5te/alt_stub.S */ 25975 /* 25976 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 25977 * any interesting requests and then jump to the real instruction 25978 * handler. Note that the call to dvmCheckBefore is done as a tail call. 25979 * rIBASE updates won't be seen until a refresh, and we can tell we have a 25980 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 25981 * bail to the real handler if breakFlags==0. 25982 */ 25983 ldrb r3, [rSELF, #offThread_breakFlags] 25984 adrl lr, dvmAsmInstructionStart + (501 * 64) 25985 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 25986 cmp r3, #0 25987 bxeq lr @ nothing to do - jump to real handler 25988 EXPORT_PC() 25989 mov r0, rPC @ arg0 25990 mov r1, rFP @ arg1 25991 mov r2, rSELF @ arg2 25992 b dvmCheckBefore @ (dPC,dFP,self) tail call 25993 25994 /* ------------------------------ */ 25995 .balign 64 25996 .L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */ 25997 /* File: armv5te/alt_stub.S */ 25998 /* 25999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26000 * any interesting requests and then jump to the real instruction 26001 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26002 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26004 * bail to the real handler if breakFlags==0. 26005 */ 26006 ldrb r3, [rSELF, #offThread_breakFlags] 26007 adrl lr, dvmAsmInstructionStart + (502 * 64) 26008 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26009 cmp r3, #0 26010 bxeq lr @ nothing to do - jump to real handler 26011 EXPORT_PC() 26012 mov r0, rPC @ arg0 26013 mov r1, rFP @ arg1 26014 mov r2, rSELF @ arg2 26015 b dvmCheckBefore @ (dPC,dFP,self) tail call 26016 26017 /* ------------------------------ */ 26018 .balign 64 26019 .L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */ 26020 /* File: armv5te/alt_stub.S */ 26021 /* 26022 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26023 * any interesting requests and then jump to the real instruction 26024 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26025 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26026 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26027 * bail to the real handler if breakFlags==0. 26028 */ 26029 ldrb r3, [rSELF, #offThread_breakFlags] 26030 adrl lr, dvmAsmInstructionStart + (503 * 64) 26031 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26032 cmp r3, #0 26033 bxeq lr @ nothing to do - jump to real handler 26034 EXPORT_PC() 26035 mov r0, rPC @ arg0 26036 mov r1, rFP @ arg1 26037 mov r2, rSELF @ arg2 26038 b dvmCheckBefore @ (dPC,dFP,self) tail call 26039 26040 /* ------------------------------ */ 26041 .balign 64 26042 .L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */ 26043 /* File: armv5te/alt_stub.S */ 26044 /* 26045 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26046 * any interesting requests and then jump to the real instruction 26047 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26048 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26049 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26050 * bail to the real handler if breakFlags==0. 26051 */ 26052 ldrb r3, [rSELF, #offThread_breakFlags] 26053 adrl lr, dvmAsmInstructionStart + (504 * 64) 26054 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26055 cmp r3, #0 26056 bxeq lr @ nothing to do - jump to real handler 26057 EXPORT_PC() 26058 mov r0, rPC @ arg0 26059 mov r1, rFP @ arg1 26060 mov r2, rSELF @ arg2 26061 b dvmCheckBefore @ (dPC,dFP,self) tail call 26062 26063 /* ------------------------------ */ 26064 .balign 64 26065 .L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */ 26066 /* File: armv5te/alt_stub.S */ 26067 /* 26068 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26069 * any interesting requests and then jump to the real instruction 26070 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26071 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26072 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26073 * bail to the real handler if breakFlags==0. 26074 */ 26075 ldrb r3, [rSELF, #offThread_breakFlags] 26076 adrl lr, dvmAsmInstructionStart + (505 * 64) 26077 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26078 cmp r3, #0 26079 bxeq lr @ nothing to do - jump to real handler 26080 EXPORT_PC() 26081 mov r0, rPC @ arg0 26082 mov r1, rFP @ arg1 26083 mov r2, rSELF @ arg2 26084 b dvmCheckBefore @ (dPC,dFP,self) tail call 26085 26086 /* ------------------------------ */ 26087 .balign 64 26088 .L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */ 26089 /* File: armv5te/alt_stub.S */ 26090 /* 26091 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26092 * any interesting requests and then jump to the real instruction 26093 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26094 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26095 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26096 * bail to the real handler if breakFlags==0. 26097 */ 26098 ldrb r3, [rSELF, #offThread_breakFlags] 26099 adrl lr, dvmAsmInstructionStart + (506 * 64) 26100 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26101 cmp r3, #0 26102 bxeq lr @ nothing to do - jump to real handler 26103 EXPORT_PC() 26104 mov r0, rPC @ arg0 26105 mov r1, rFP @ arg1 26106 mov r2, rSELF @ arg2 26107 b dvmCheckBefore @ (dPC,dFP,self) tail call 26108 26109 /* ------------------------------ */ 26110 .balign 64 26111 .L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */ 26112 /* File: armv5te/alt_stub.S */ 26113 /* 26114 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26115 * any interesting requests and then jump to the real instruction 26116 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26117 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26118 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26119 * bail to the real handler if breakFlags==0. 26120 */ 26121 ldrb r3, [rSELF, #offThread_breakFlags] 26122 adrl lr, dvmAsmInstructionStart + (507 * 64) 26123 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26124 cmp r3, #0 26125 bxeq lr @ nothing to do - jump to real handler 26126 EXPORT_PC() 26127 mov r0, rPC @ arg0 26128 mov r1, rFP @ arg1 26129 mov r2, rSELF @ arg2 26130 b dvmCheckBefore @ (dPC,dFP,self) tail call 26131 26132 /* ------------------------------ */ 26133 .balign 64 26134 .L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */ 26135 /* File: armv5te/alt_stub.S */ 26136 /* 26137 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26138 * any interesting requests and then jump to the real instruction 26139 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26140 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26141 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26142 * bail to the real handler if breakFlags==0. 26143 */ 26144 ldrb r3, [rSELF, #offThread_breakFlags] 26145 adrl lr, dvmAsmInstructionStart + (508 * 64) 26146 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26147 cmp r3, #0 26148 bxeq lr @ nothing to do - jump to real handler 26149 EXPORT_PC() 26150 mov r0, rPC @ arg0 26151 mov r1, rFP @ arg1 26152 mov r2, rSELF @ arg2 26153 b dvmCheckBefore @ (dPC,dFP,self) tail call 26154 26155 /* ------------------------------ */ 26156 .balign 64 26157 .L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */ 26158 /* File: armv5te/alt_stub.S */ 26159 /* 26160 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26161 * any interesting requests and then jump to the real instruction 26162 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26163 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26164 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26165 * bail to the real handler if breakFlags==0. 26166 */ 26167 ldrb r3, [rSELF, #offThread_breakFlags] 26168 adrl lr, dvmAsmInstructionStart + (509 * 64) 26169 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26170 cmp r3, #0 26171 bxeq lr @ nothing to do - jump to real handler 26172 EXPORT_PC() 26173 mov r0, rPC @ arg0 26174 mov r1, rFP @ arg1 26175 mov r2, rSELF @ arg2 26176 b dvmCheckBefore @ (dPC,dFP,self) tail call 26177 26178 /* ------------------------------ */ 26179 .balign 64 26180 .L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */ 26181 /* File: armv5te/alt_stub.S */ 26182 /* 26183 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26184 * any interesting requests and then jump to the real instruction 26185 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26186 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26187 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26188 * bail to the real handler if breakFlags==0. 26189 */ 26190 ldrb r3, [rSELF, #offThread_breakFlags] 26191 adrl lr, dvmAsmInstructionStart + (510 * 64) 26192 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26193 cmp r3, #0 26194 bxeq lr @ nothing to do - jump to real handler 26195 EXPORT_PC() 26196 mov r0, rPC @ arg0 26197 mov r1, rFP @ arg1 26198 mov r2, rSELF @ arg2 26199 b dvmCheckBefore @ (dPC,dFP,self) tail call 26200 26201 /* ------------------------------ */ 26202 .balign 64 26203 .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */ 26204 /* File: armv5te/alt_stub.S */ 26205 /* 26206 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle 26207 * any interesting requests and then jump to the real instruction 26208 * handler. Note that the call to dvmCheckBefore is done as a tail call. 26209 * rIBASE updates won't be seen until a refresh, and we can tell we have a 26210 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then 26211 * bail to the real handler if breakFlags==0. 26212 */ 26213 ldrb r3, [rSELF, #offThread_breakFlags] 26214 adrl lr, dvmAsmInstructionStart + (511 * 64) 26215 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26216 cmp r3, #0 26217 bxeq lr @ nothing to do - jump to real handler 26218 EXPORT_PC() 26219 mov r0, rPC @ arg0 26220 mov r1, rFP @ arg1 26221 mov r2, rSELF @ arg2 26222 b dvmCheckBefore @ (dPC,dFP,self) tail call 26223 26224 .balign 64 26225 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart 26226 .global dvmAsmAltInstructionEnd 26227 dvmAsmAltInstructionEnd: 26228 /* File: armv5te/footer.S */ 26229 /* 26230 * =========================================================================== 26231 * Common subroutines and data 26232 * =========================================================================== 26233 */ 26234 26235 .text 26236 .align 2 26237 26238 #if defined(WITH_JIT) 26239 26240 #if defined(WITH_SELF_VERIFICATION) 26241 /* 26242 * "longjmp" to a translation after single-stepping. Before returning 26243 * to translation, must save state for self-verification. 26244 */ 26245 .global dvmJitResumeTranslation @ (Thread* self, u4* dFP) 26246 dvmJitResumeTranslation: 26247 mov rSELF, r0 @ restore self 26248 mov rPC, r1 @ restore Dalvik pc 26249 mov rFP, r2 @ restore Dalvik fp 26250 ldr r10, [rSELF,#offThread_jitResumeNPC] @ resume address 26251 mov r2, #0 26252 str r2, [rSELF,#offThread_jitResumeNPC] @ reset resume address 26253 ldr sp, [rSELF,#offThread_jitResumeNSP] @ cut back native stack 26254 b jitSVShadowRunStart @ resume as if cache hit 26255 @ expects resume addr in r10 26256 26257 .global dvmJitToInterpPunt 26258 dvmJitToInterpPunt: 26259 mov r2,#kSVSPunt @ r2<- interpreter entry point 26260 mov r3, #0 26261 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26262 b jitSVShadowRunEnd @ doesn't return 26263 26264 .global dvmJitToInterpSingleStep 26265 dvmJitToInterpSingleStep: 26266 mov rPC, r0 @ set up dalvik pc 26267 EXPORT_PC() 26268 str lr, [rSELF,#offThread_jitResumeNPC] 26269 str sp, [rSELF,#offThread_jitResumeNSP] 26270 str r1, [rSELF,#offThread_jitResumeDPC] 26271 mov r2,#kSVSSingleStep @ r2<- interpreter entry point 26272 b jitSVShadowRunEnd @ doesn't return 26273 26274 26275 .global dvmJitToInterpNoChainNoProfile 26276 dvmJitToInterpNoChainNoProfile: 26277 mov r0,rPC @ pass our target PC 26278 mov r2,#kSVSNoProfile @ r2<- interpreter entry point 26279 mov r3, #0 @ 0 means !inJitCodeCache 26280 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 26281 b jitSVShadowRunEnd @ doesn't return 26282 26283 .global dvmJitToInterpTraceSelectNoChain 26284 dvmJitToInterpTraceSelectNoChain: 26285 mov r0,rPC @ pass our target PC 26286 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 26287 mov r3, #0 @ 0 means !inJitCodeCache 26288 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26289 b jitSVShadowRunEnd @ doesn't return 26290 26291 .global dvmJitToInterpTraceSelect 26292 dvmJitToInterpTraceSelect: 26293 ldr r0,[lr, #-1] @ pass our target PC 26294 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 26295 mov r3, #0 @ 0 means !inJitCodeCache 26296 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26297 b jitSVShadowRunEnd @ doesn't return 26298 26299 .global dvmJitToInterpBackwardBranch 26300 dvmJitToInterpBackwardBranch: 26301 ldr r0,[lr, #-1] @ pass our target PC 26302 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 26303 mov r3, #0 @ 0 means !inJitCodeCache 26304 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26305 b jitSVShadowRunEnd @ doesn't return 26306 26307 .global dvmJitToInterpNormal 26308 dvmJitToInterpNormal: 26309 ldr r0,[lr, #-1] @ pass our target PC 26310 mov r2,#kSVSNormal @ r2<- interpreter entry point 26311 mov r3, #0 @ 0 means !inJitCodeCache 26312 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26313 b jitSVShadowRunEnd @ doesn't return 26314 26315 .global dvmJitToInterpNoChain 26316 dvmJitToInterpNoChain: 26317 mov r0,rPC @ pass our target PC 26318 mov r2,#kSVSNoChain @ r2<- interpreter entry point 26319 mov r3, #0 @ 0 means !inJitCodeCache 26320 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26321 b jitSVShadowRunEnd @ doesn't return 26322 #else 26323 26324 /* 26325 * "longjmp" to a translation after single-stepping. 26326 */ 26327 .global dvmJitResumeTranslation @ (Thread* self, u4* dFP) 26328 dvmJitResumeTranslation: 26329 mov rSELF, r0 @ restore self 26330 mov rPC, r1 @ restore Dalvik pc 26331 mov rFP, r2 @ restore Dalvik fp 26332 ldr r0, [rSELF,#offThread_jitResumeNPC] 26333 mov r2, #0 26334 str r2, [rSELF,#offThread_jitResumeNPC] @ reset resume address 26335 ldr sp, [rSELF,#offThread_jitResumeNSP] @ cut back native stack 26336 bx r0 @ resume translation 26337 26338 /* 26339 * Return from the translation cache to the interpreter when the compiler is 26340 * having issues translating/executing a Dalvik instruction. We have to skip 26341 * the code cache lookup otherwise it is possible to indefinitely bouce 26342 * between the interpreter and the code cache if the instruction that fails 26343 * to be compiled happens to be at a trace start. 26344 */ 26345 .global dvmJitToInterpPunt 26346 dvmJitToInterpPunt: 26347 mov rPC, r0 26348 #if defined(WITH_JIT_TUNING) 26349 mov r0,lr 26350 bl dvmBumpPunt; 26351 #endif 26352 EXPORT_PC() 26353 mov r0, #0 26354 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land 26355 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26356 FETCH_INST() 26357 GET_INST_OPCODE(ip) 26358 GOTO_OPCODE(ip) 26359 26360 /* 26361 * Return to the interpreter to handle a single instruction. 26362 * We'll use the normal single-stepping mechanism via interpBreak, 26363 * but also save the native pc of the resume point in the translation 26364 * and the native sp so that we can later do the equivalent of a 26365 * longjmp() to resume. 26366 * On entry: 26367 * dPC <= Dalvik PC of instrucion to interpret 26368 * lr <= resume point in translation 26369 * r1 <= Dalvik PC of next instruction 26370 */ 26371 .global dvmJitToInterpSingleStep 26372 dvmJitToInterpSingleStep: 26373 mov rPC, r0 @ set up dalvik pc 26374 EXPORT_PC() 26375 str lr, [rSELF,#offThread_jitResumeNPC] 26376 str sp, [rSELF,#offThread_jitResumeNSP] 26377 str r1, [rSELF,#offThread_jitResumeDPC] 26378 mov r1, #1 26379 str r1, [rSELF,#offThread_singleStepCount] @ just step once 26380 mov r0, rSELF 26381 mov r1, #kSubModeCountedStep 26382 bl dvmEnableSubMode @ (self, newMode) 26383 ldr rIBASE, [rSELF,#offThread_curHandlerTable] 26384 FETCH_INST() 26385 GET_INST_OPCODE(ip) 26386 GOTO_OPCODE(ip) 26387 26388 /* 26389 * Return from the translation cache and immediately request 26390 * a translation for the exit target. Commonly used for callees. 26391 */ 26392 .global dvmJitToInterpTraceSelectNoChain 26393 dvmJitToInterpTraceSelectNoChain: 26394 #if defined(WITH_JIT_TUNING) 26395 bl dvmBumpNoChain 26396 #endif 26397 mov r0,rPC 26398 mov r1,rSELF 26399 bl dvmJitGetTraceAddrThread @ (pc, self) 26400 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 26401 mov r1, rPC @ arg1 of translation may need this 26402 mov lr, #0 @ in case target is HANDLER_INTERPRET 26403 cmp r0,#0 @ !0 means translation exists 26404 bxne r0 @ continue native execution if so 26405 b 2f @ branch over to use the interpreter 26406 26407 /* 26408 * Return from the translation cache and immediately request 26409 * a translation for the exit target. Commonly used following 26410 * invokes. 26411 */ 26412 .global dvmJitToInterpTraceSelect 26413 dvmJitToInterpTraceSelect: 26414 ldr rPC,[lr, #-1] @ get our target PC 26415 add rINST,lr,#-5 @ save start of chain branch 26416 add rINST, #-4 @ .. which is 9 bytes back 26417 mov r0,rPC 26418 mov r1,rSELF 26419 bl dvmJitGetTraceAddrThread @ (pc, self) 26420 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 26421 cmp r0,#0 26422 beq 2f 26423 mov r1,rINST 26424 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 26425 mov r1, rPC @ arg1 of translation may need this 26426 mov lr, #0 @ in case target is HANDLER_INTERPRET 26427 cmp r0,#0 @ successful chain? 26428 bxne r0 @ continue native execution 26429 b toInterpreter @ didn't chain - resume with interpreter 26430 26431 /* No translation, so request one if profiling isn't disabled*/ 26432 2: 26433 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26434 ldr r0, [rSELF, #offThread_pJitProfTable] 26435 FETCH_INST() 26436 cmp r0, #0 26437 movne r2,#kJitTSelectRequestHot @ ask for trace selection 26438 bne common_selectTrace 26439 GET_INST_OPCODE(ip) 26440 GOTO_OPCODE(ip) 26441 26442 /* 26443 * Return from the translation cache to the interpreter. 26444 * The return was done with a BLX from thumb mode, and 26445 * the following 32-bit word contains the target rPC value. 26446 * Note that lr (r14) will have its low-order bit set to denote 26447 * its thumb-mode origin. 26448 * 26449 * We'll need to stash our lr origin away, recover the new 26450 * target and then check to see if there is a translation available 26451 * for our new target. If so, we do a translation chain and 26452 * go back to native execution. Otherwise, it's back to the 26453 * interpreter (after treating this entry as a potential 26454 * trace start). 26455 */ 26456 .global dvmJitToInterpNormal 26457 dvmJitToInterpNormal: 26458 ldr rPC,[lr, #-1] @ get our target PC 26459 add rINST,lr,#-5 @ save start of chain branch 26460 add rINST,#-4 @ .. which is 9 bytes back 26461 #if defined(WITH_JIT_TUNING) 26462 bl dvmBumpNormal 26463 #endif 26464 mov r0,rPC 26465 mov r1,rSELF 26466 bl dvmJitGetTraceAddrThread @ (pc, self) 26467 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 26468 cmp r0,#0 26469 beq toInterpreter @ go if not, otherwise do chain 26470 mov r1,rINST 26471 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 26472 mov r1, rPC @ arg1 of translation may need this 26473 mov lr, #0 @ in case target is HANDLER_INTERPRET 26474 cmp r0,#0 @ successful chain? 26475 bxne r0 @ continue native execution 26476 b toInterpreter @ didn't chain - resume with interpreter 26477 26478 /* 26479 * Return from the translation cache to the interpreter to do method invocation. 26480 * Check if translation exists for the callee, but don't chain to it. 26481 */ 26482 .global dvmJitToInterpNoChainNoProfile 26483 dvmJitToInterpNoChainNoProfile: 26484 #if defined(WITH_JIT_TUNING) 26485 bl dvmBumpNoChain 26486 #endif 26487 mov r0,rPC 26488 mov r1,rSELF 26489 bl dvmJitGetTraceAddrThread @ (pc, self) 26490 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 26491 mov r1, rPC @ arg1 of translation may need this 26492 mov lr, #0 @ in case target is HANDLER_INTERPRET 26493 cmp r0,#0 26494 bxne r0 @ continue native execution if so 26495 EXPORT_PC() 26496 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26497 FETCH_INST() 26498 GET_INST_OPCODE(ip) @ extract opcode from rINST 26499 GOTO_OPCODE(ip) @ jump to next instruction 26500 26501 /* 26502 * Return from the translation cache to the interpreter to do method invocation. 26503 * Check if translation exists for the callee, but don't chain to it. 26504 */ 26505 .global dvmJitToInterpNoChain 26506 dvmJitToInterpNoChain: 26507 #if defined(WITH_JIT_TUNING) 26508 bl dvmBumpNoChain 26509 #endif 26510 mov r0,rPC 26511 mov r1,rSELF 26512 bl dvmJitGetTraceAddrThread @ (pc, self) 26513 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 26514 mov r1, rPC @ arg1 of translation may need this 26515 mov lr, #0 @ in case target is HANDLER_INTERPRET 26516 cmp r0,#0 26517 bxne r0 @ continue native execution if so 26518 #endif 26519 26520 /* 26521 * No translation, restore interpreter regs and start interpreting. 26522 * rSELF & rFP were preserved in the translated code, and rPC has 26523 * already been restored by the time we get here. We'll need to set 26524 * up rIBASE & rINST, and load the address of the JitTable into r0. 26525 */ 26526 toInterpreter: 26527 EXPORT_PC() 26528 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26529 FETCH_INST() 26530 ldr r0, [rSELF, #offThread_pJitProfTable] 26531 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26532 @ NOTE: intended fallthrough 26533 26534 /* 26535 * Similar to common_updateProfile, but tests for null pJitProfTable 26536 * r0 holds pJifProfTAble, rINST is loaded, rPC is current and 26537 * rIBASE has been recently refreshed. 26538 */ 26539 common_testUpdateProfile: 26540 cmp r0, #0 @ JIT switched off? 26541 beq 4f @ return to interp if so 26542 26543 /* 26544 * Common code to update potential trace start counter, and initiate 26545 * a trace-build if appropriate. 26546 * On entry here: 26547 * r0 <= pJitProfTable (verified non-NULL) 26548 * rPC <= Dalvik PC 26549 * rINST <= next instruction 26550 */ 26551 common_updateProfile: 26552 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 26553 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 26554 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 26555 GET_INST_OPCODE(ip) 26556 subs r1,r1,#1 @ decrement counter 26557 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 26558 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 26559 26560 /* Looks good, reset the counter */ 26561 ldr r1, [rSELF, #offThread_jitThreshold] 26562 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 26563 EXPORT_PC() 26564 mov r0,rPC 26565 mov r1,rSELF 26566 bl dvmJitGetTraceAddrThread @ (pc, self) 26567 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 26568 mov r1, rPC @ arg1 of translation may need this 26569 mov lr, #0 @ in case target is HANDLER_INTERPRET 26570 cmp r0,#0 26571 #if !defined(WITH_SELF_VERIFICATION) 26572 bxne r0 @ jump to the translation 26573 mov r2,#kJitTSelectRequest @ ask for trace selection 26574 @ fall-through to common_selectTrace 26575 #else 26576 moveq r2,#kJitTSelectRequest @ ask for trace selection 26577 beq common_selectTrace 26578 /* 26579 * At this point, we have a target translation. However, if 26580 * that translation is actually the interpret-only pseudo-translation 26581 * we want to treat it the same as no translation. 26582 */ 26583 mov r10, r0 @ save target 26584 bl dvmCompilerGetInterpretTemplate 26585 cmp r0, r10 @ special case? 26586 bne jitSVShadowRunStart @ set up self verification shadow space 26587 @ Need to clear the inJitCodeCache flag 26588 mov r3, #0 @ 0 means not in the JIT code cache 26589 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land 26590 GET_INST_OPCODE(ip) 26591 GOTO_OPCODE(ip) 26592 /* no return */ 26593 #endif 26594 26595 /* 26596 * On entry: 26597 * r2 is jit state. 26598 */ 26599 common_selectTrace: 26600 ldrh r0,[rSELF,#offThread_subMode] 26601 ands r0, #(kSubModeJitTraceBuild | kSubModeJitSV) 26602 bne 3f @ already doing JIT work, continue 26603 str r2,[rSELF,#offThread_jitState] 26604 mov r0, rSELF 26605 /* 26606 * Call out to validate trace-building request. If successful, 26607 * rIBASE will be swapped to to send us into single-stepping trace 26608 * building mode, so we need to refresh before we continue. 26609 */ 26610 EXPORT_PC() 26611 SAVE_PC_FP_TO_SELF() @ copy of pc/fp to Thread 26612 bl dvmJitCheckTraceRequest 26613 3: 26614 FETCH_INST() 26615 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26616 4: 26617 GET_INST_OPCODE(ip) @ extract opcode from rINST 26618 GOTO_OPCODE(ip) 26619 /* no return */ 26620 #endif 26621 26622 #if defined(WITH_SELF_VERIFICATION) 26623 /* 26624 * Save PC and registers to shadow memory for self verification mode 26625 * before jumping to native translation. 26626 * On entry: 26627 * rPC, rFP, rSELF: the values that they should contain 26628 * r10: the address of the target translation. 26629 */ 26630 jitSVShadowRunStart: 26631 mov r0,rPC @ r0<- program counter 26632 mov r1,rFP @ r1<- frame pointer 26633 mov r2,rSELF @ r2<- self (Thread) pointer 26634 mov r3,r10 @ r3<- target translation 26635 bl dvmSelfVerificationSaveState @ save registers to shadow space 26636 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 26637 bx r10 @ jump to the translation 26638 26639 /* 26640 * Restore PC, registers, and interpreter state to original values 26641 * before jumping back to the interpreter. 26642 * On entry: 26643 * r0: dPC 26644 * r2: self verification state 26645 */ 26646 jitSVShadowRunEnd: 26647 mov r1,rFP @ pass ending fp 26648 mov r3,rSELF @ pass self ptr for convenience 26649 bl dvmSelfVerificationRestoreState @ restore pc and fp values 26650 LOAD_PC_FP_FROM_SELF() @ restore pc, fp 26651 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 26652 cmp r1,#0 @ check for punt condition 26653 beq 1f 26654 @ Set up SV single-stepping 26655 mov r0, rSELF 26656 mov r1, #kSubModeJitSV 26657 bl dvmEnableSubMode @ (self, subMode) 26658 mov r2,#kJitSelfVerification @ ask for self verification 26659 str r2,[rSELF,#offThread_jitState] 26660 @ intentional fallthrough 26661 1: @ exit to interpreter without check 26662 EXPORT_PC() 26663 ldr rIBASE, [rSELF, #offThread_curHandlerTable] 26664 FETCH_INST() 26665 GET_INST_OPCODE(ip) 26666 GOTO_OPCODE(ip) 26667 #endif 26668 26669 /* 26670 * The equivalent of "goto bail", this calls through the "bail handler". 26671 * It will end this interpreter activation, and return to the caller 26672 * of dvmMterpStdRun. 26673 * 26674 * State registers will be saved to the "thread" area before bailing 26675 * debugging purposes 26676 */ 26677 common_gotoBail: 26678 SAVE_PC_FP_TO_SELF() @ export state to "thread" 26679 mov r0, rSELF @ r0<- self ptr 26680 b dvmMterpStdBail @ call(self, changeInterp) 26681 26682 /* 26683 * The JIT's invoke method needs to remember the callsite class and 26684 * target pair. Save them here so that they are available to 26685 * dvmCheckJit following the interpretation of this invoke. 26686 */ 26687 #if defined(WITH_JIT) 26688 save_callsiteinfo: 26689 cmp r9, #0 26690 ldrne r9, [r9, #offObject_clazz] 26691 str r0, [rSELF, #offThread_methodToCall] 26692 str r9, [rSELF, #offThread_callsiteClass] 26693 bx lr 26694 #endif 26695 26696 /* 26697 * Common code for jumbo method invocation. 26698 * NOTE: this adjusts rPC to account for the difference in instruction width. 26699 * As a result, the savedPc in the stack frame will not be wholly accurate. So 26700 * long as that is only used for source file line number calculations, we're 26701 * okay. 26702 */ 26703 common_invokeMethodJumboNoThis: 26704 #if defined(WITH_JIT) 26705 /* On entry: r0 is "Method* methodToCall */ 26706 mov r9, #0 @ clear "this" 26707 #endif 26708 common_invokeMethodJumbo: 26709 /* On entry: r0 is "Method* methodToCall, r9 is "this" */ 26710 .LinvokeNewJumbo: 26711 #if defined(WITH_JIT) 26712 ldrh r1, [rSELF, #offThread_subMode] 26713 ands r1, #kSubModeJitTraceBuild 26714 blne save_callsiteinfo 26715 #endif 26716 @ prepare to copy args to "outs" area of current frame 26717 add rPC, rPC, #4 @ adjust pc to make return consistent 26718 FETCH(r2, 1) @ r2<- BBBB (arg count) 26719 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 26720 cmp r2, #0 @ no args? 26721 beq .LinvokeArgsDone @ if no args, skip the rest 26722 FETCH(r1, 2) @ r1<- CCCC 26723 b .LinvokeRangeArgs @ handle args like invoke range 26724 26725 /* 26726 * Common code for method invocation with range. 26727 * 26728 * On entry: 26729 * r0 is "Method* methodToCall", r9 is "this" 26730 */ 26731 common_invokeMethodRange: 26732 .LinvokeNewRange: 26733 #if defined(WITH_JIT) 26734 ldrh r1, [rSELF, #offThread_subMode] 26735 ands r1, #kSubModeJitTraceBuild 26736 blne save_callsiteinfo 26737 #endif 26738 @ prepare to copy args to "outs" area of current frame 26739 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 26740 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 26741 beq .LinvokeArgsDone @ if no args, skip the rest 26742 FETCH(r1, 2) @ r1<- CCCC 26743 26744 .LinvokeRangeArgs: 26745 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 26746 @ (very few methods have > 10 args; could unroll for common cases) 26747 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 26748 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 26749 1: ldr r1, [r3], #4 @ val = *fp++ 26750 subs r2, r2, #1 @ count-- 26751 str r1, [r10], #4 @ *outs++ = val 26752 bne 1b @ ...while count != 0 26753 b .LinvokeArgsDone 26754 26755 /* 26756 * Common code for method invocation without range. 26757 * 26758 * On entry: 26759 * r0 is "Method* methodToCall", r9 is "this" 26760 */ 26761 common_invokeMethodNoRange: 26762 .LinvokeNewNoRange: 26763 #if defined(WITH_JIT) 26764 ldrh r1, [rSELF, #offThread_subMode] 26765 ands r1, #kSubModeJitTraceBuild 26766 blne save_callsiteinfo 26767 #endif 26768 @ prepare to copy args to "outs" area of current frame 26769 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 26770 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 26771 FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 26772 beq .LinvokeArgsDone 26773 26774 @ r0=methodToCall, r1=GFED, r2=count, r10=outs 26775 .LinvokeNonRange: 26776 rsb r2, r2, #5 @ r2<- 5-r2 26777 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 26778 bl common_abort @ (skipped due to ARM prefetch) 26779 5: and ip, rINST, #0x0f00 @ isolate A 26780 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 26781 mov r0, r0 @ nop 26782 str r2, [r10, #-4]! @ *--outs = vA 26783 4: and ip, r1, #0xf000 @ isolate G 26784 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 26785 mov r0, r0 @ nop 26786 str r2, [r10, #-4]! @ *--outs = vG 26787 3: and ip, r1, #0x0f00 @ isolate F 26788 ldr r2, [rFP, ip, lsr #6] @ r2<- vF 26789 mov r0, r0 @ nop 26790 str r2, [r10, #-4]! @ *--outs = vF 26791 2: and ip, r1, #0x00f0 @ isolate E 26792 ldr r2, [rFP, ip, lsr #2] @ r2<- vE 26793 mov r0, r0 @ nop 26794 str r2, [r10, #-4]! @ *--outs = vE 26795 1: and ip, r1, #0x000f @ isolate D 26796 ldr r2, [rFP, ip, lsl #2] @ r2<- vD 26797 mov r0, r0 @ nop 26798 str r2, [r10, #-4]! @ *--outs = vD 26799 0: @ fall through to .LinvokeArgsDone 26800 26801 .LinvokeArgsDone: @ r0=methodToCall 26802 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 26803 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 26804 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 26805 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 26806 @ find space for the new stack frame, check for overflow 26807 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 26808 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 26809 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 26810 @ bl common_dumpRegs 26811 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd 26812 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 26813 cmp r3, r9 @ bottom < interpStackEnd? 26814 ldrh lr, [rSELF, #offThread_subMode] 26815 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 26816 blo .LstackOverflow @ yes, this frame will overflow stack 26817 26818 @ set up newSaveArea 26819 #ifdef EASY_GDB 26820 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 26821 str ip, [r10, #offStackSaveArea_prevSave] 26822 #endif 26823 str rFP, [r10, #offStackSaveArea_prevFrame] 26824 str rPC, [r10, #offStackSaveArea_savedPc] 26825 #if defined(WITH_JIT) 26826 mov r9, #0 26827 str r9, [r10, #offStackSaveArea_returnAddr] 26828 #endif 26829 str r0, [r10, #offStackSaveArea_method] 26830 26831 @ Profiling? 26832 cmp lr, #0 @ any special modes happening? 26833 bne 2f @ go if so 26834 1: 26835 tst r3, #ACC_NATIVE 26836 bne .LinvokeNative 26837 26838 /* 26839 stmfd sp!, {r0-r3} 26840 bl common_printNewline 26841 mov r0, rFP 26842 mov r1, #0 26843 bl dvmDumpFp 26844 ldmfd sp!, {r0-r3} 26845 stmfd sp!, {r0-r3} 26846 mov r0, r1 26847 mov r1, r10 26848 bl dvmDumpFp 26849 bl common_printNewline 26850 ldmfd sp!, {r0-r3} 26851 */ 26852 26853 ldrh r9, [r2] @ r9 <- load INST from new PC 26854 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 26855 mov rPC, r2 @ publish new rPC 26856 26857 @ Update state values for the new method 26858 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST 26859 str r0, [rSELF, #offThread_method] @ self->method = methodToCall 26860 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ... 26861 mov r2, #1 26862 str r2, [rSELF, #offThread_debugIsMethodEntry] 26863 #if defined(WITH_JIT) 26864 ldr r0, [rSELF, #offThread_pJitProfTable] 26865 mov rFP, r1 @ fp = newFp 26866 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 26867 mov rINST, r9 @ publish new rINST 26868 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp 26869 cmp r0,#0 26870 bne common_updateProfile 26871 GOTO_OPCODE(ip) @ jump to next instruction 26872 #else 26873 mov rFP, r1 @ fp = newFp 26874 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 26875 mov rINST, r9 @ publish new rINST 26876 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp 26877 GOTO_OPCODE(ip) @ jump to next instruction 26878 #endif 26879 26880 2: 26881 @ Profiling - record method entry. r0: methodToCall 26882 stmfd sp!, {r0-r3} @ preserve r0-r3 26883 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc 26884 mov r1, r0 26885 mov r0, rSELF 26886 bl dvmReportInvoke @ (self, method) 26887 ldmfd sp!, {r0-r3} @ restore r0-r3 26888 b 1b 26889 26890 .LinvokeNative: 26891 @ Prep for the native call 26892 @ r0=methodToCall, r1=newFp, r10=newSaveArea 26893 ldrh lr, [rSELF, #offThread_subMode] 26894 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->... 26895 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp 26896 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 26897 mov r2, r0 @ r2<- methodToCall 26898 mov r0, r1 @ r0<- newFp (points to args) 26899 add r1, rSELF, #offThread_retval @ r1<- &retval 26900 mov r3, rSELF @ arg3<- self 26901 26902 #ifdef ASSIST_DEBUGGER 26903 /* insert fake function header to help gdb find the stack frame */ 26904 b .Lskip 26905 .type dalvik_mterp, %function 26906 dalvik_mterp: 26907 .fnstart 26908 MTERP_ENTRY1 26909 MTERP_ENTRY2 26910 .Lskip: 26911 #endif 26912 26913 cmp lr, #0 @ any special SubModes active? 26914 bne 11f @ go handle them if so 26915 mov lr, pc @ set return addr 26916 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 26917 7: 26918 26919 @ native return; r10=newSaveArea 26920 @ equivalent to dvmPopJniLocals 26921 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 26922 ldr r1, [rSELF, #offThread_exception] @ check for exception 26923 str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp 26924 cmp r1, #0 @ null? 26925 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top 26926 bne common_exceptionThrown @ no, handle exception 26927 26928 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 26929 GET_INST_OPCODE(ip) @ extract opcode from rINST 26930 GOTO_OPCODE(ip) @ jump to next instruction 26931 26932 11: 26933 @ r0=newFp, r1=&retval, r2=methodToCall, r3=self, lr=subModes 26934 stmfd sp!, {r0-r3} @ save all but subModes 26935 mov r0, r2 @ r0<- methodToCall 26936 mov r1, rSELF 26937 mov r2, rFP 26938 bl dvmReportPreNativeInvoke @ (methodToCall, self, fp) 26939 ldmfd sp, {r0-r3} @ refresh. NOTE: no sp autoincrement 26940 26941 @ Call the native method 26942 mov lr, pc @ set return addr 26943 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 26944 26945 @ Restore the pre-call arguments 26946 ldmfd sp!, {r0-r3} @ r2<- methodToCall (others unneeded) 26947 26948 @ Finish up any post-invoke subMode requirements 26949 mov r0, r2 @ r0<- methodToCall 26950 mov r1, rSELF 26951 mov r2, rFP 26952 bl dvmReportPostNativeInvoke @ (methodToCall, self, fp) 26953 b 7b @ resume 26954 26955 .LstackOverflow: @ r0=methodToCall 26956 mov r1, r0 @ r1<- methodToCall 26957 mov r0, rSELF @ r0<- self 26958 bl dvmHandleStackOverflow 26959 b common_exceptionThrown 26960 #ifdef ASSIST_DEBUGGER 26961 .fnend 26962 .size dalvik_mterp, .-dalvik_mterp 26963 #endif 26964 26965 26966 /* 26967 * Common code for method invocation, calling through "glue code". 26968 * 26969 * TODO: now that we have range and non-range invoke handlers, this 26970 * needs to be split into two. Maybe just create entry points 26971 * that set r9 and jump here? 26972 * 26973 * On entry: 26974 * r0 is "Method* methodToCall", the method we're trying to call 26975 * r9 is "bool methodCallRange", indicating if this is a /range variant 26976 */ 26977 .if 0 26978 .LinvokeOld: 26979 sub sp, sp, #8 @ space for args + pad 26980 FETCH(ip, 2) @ ip<- FEDC or CCCC 26981 mov r2, r0 @ A2<- methodToCall 26982 mov r0, rSELF @ A0<- self 26983 SAVE_PC_FP_TO_SELF() @ export state to "self" 26984 mov r1, r9 @ A1<- methodCallRange 26985 mov r3, rINST, lsr #8 @ A3<- AA 26986 str ip, [sp, #0] @ A4<- ip 26987 bl dvmMterp_invokeMethod @ call the C invokeMethod 26988 add sp, sp, #8 @ remove arg area 26989 b common_resumeAfterGlueCall @ continue to next instruction 26990 .endif 26991 26992 26993 26994 /* 26995 * Common code for handling a return instruction. 26996 * 26997 * This does not return. 26998 */ 26999 common_returnFromMethod: 27000 .LreturnNew: 27001 ldrh lr, [rSELF, #offThread_subMode] 27002 SAVEAREA_FROM_FP(r0, rFP) 27003 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 27004 cmp lr, #0 @ any special subMode handling needed? 27005 bne 19f 27006 14: 27007 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 27008 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 27009 @ r2<- method we're returning to 27010 cmp r2, #0 @ is this a break frame? 27011 #if defined(WORKAROUND_CORTEX_A9_745320) 27012 /* Don't use conditional loads if the HW defect exists */ 27013 beq 15f 27014 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz 27015 15: 27016 #else 27017 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 27018 #endif 27019 beq common_gotoBail @ break frame, bail out completely 27020 27021 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 27022 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 27023 str r2, [rSELF, #offThread_method]@ self->method = newSave->method 27024 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 27025 str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp 27026 #if defined(WITH_JIT) 27027 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 27028 mov rPC, r9 @ publish new rPC 27029 str r1, [rSELF, #offThread_methodClassDex] 27030 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land 27031 cmp r10, #0 @ caller is compiled code 27032 blxne r10 27033 GET_INST_OPCODE(ip) @ extract opcode from rINST 27034 GOTO_OPCODE(ip) @ jump to next instruction 27035 #else 27036 GET_INST_OPCODE(ip) @ extract opcode from rINST 27037 mov rPC, r9 @ publish new rPC 27038 str r1, [rSELF, #offThread_methodClassDex] 27039 GOTO_OPCODE(ip) @ jump to next instruction 27040 #endif 27041 27042 19: 27043 @ Handle special actions 27044 @ On entry, r0: StackSaveArea 27045 ldr r1, [r0, #offStackSaveArea_prevFrame] @ r2<- prevFP 27046 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc 27047 str r1, [rSELF, #offThread_curFrame] @ update interpSave.curFrame 27048 mov r0, rSELF 27049 bl dvmReportReturn @ (self) 27050 SAVEAREA_FROM_FP(r0, rFP) @ restore StackSaveArea 27051 b 14b @ continue 27052 27053 /* 27054 * Return handling, calls through "glue code". 27055 */ 27056 .if 0 27057 .LreturnOld: 27058 SAVE_PC_FP_TO_SELF() @ export state 27059 mov r0, rSELF @ arg to function 27060 bl dvmMterp_returnFromMethod 27061 b common_resumeAfterGlueCall 27062 .endif 27063 27064 27065 /* 27066 * Somebody has thrown an exception. Handle it. 27067 * 27068 * If the exception processing code returns to us (instead of falling 27069 * out of the interpreter), continue with whatever the next instruction 27070 * now happens to be. 27071 * 27072 * This does not return. 27073 */ 27074 .global dvmMterpCommonExceptionThrown 27075 dvmMterpCommonExceptionThrown: 27076 common_exceptionThrown: 27077 .LexceptionNew: 27078 27079 EXPORT_PC() 27080 27081 mov r0, rSELF 27082 bl dvmCheckSuspendPending 27083 27084 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception 27085 mov r1, rSELF @ r1<- self 27086 mov r0, r9 @ r0<- exception 27087 bl dvmAddTrackedAlloc @ don't let the exception be GCed 27088 ldrh r2, [rSELF, #offThread_subMode] @ get subMode flags 27089 mov r3, #0 @ r3<- NULL 27090 str r3, [rSELF, #offThread_exception] @ self->exception = NULL 27091 27092 @ Special subMode? 27093 cmp r2, #0 @ any special subMode handling needed? 27094 bne 7f @ go if so 27095 8: 27096 /* set up args and a local for "&fp" */ 27097 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 27098 str rFP, [sp, #-4]! @ *--sp = fp 27099 mov ip, sp @ ip<- &fp 27100 mov r3, #0 @ r3<- false 27101 str ip, [sp, #-4]! @ *--sp = &fp 27102 ldr r1, [rSELF, #offThread_method] @ r1<- self->method 27103 mov r0, rSELF @ r0<- self 27104 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 27105 ldrh lr, [rSELF, #offThread_subMode] @ lr<- subMode flags 27106 mov r2, r9 @ r2<- exception 27107 sub r1, rPC, r1 @ r1<- pc - method->insns 27108 mov r1, r1, asr #1 @ r1<- offset in code units 27109 27110 /* call, r0 gets catchRelPc (a code-unit offset) */ 27111 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 27112 27113 /* fix earlier stack overflow if necessary; may trash rFP */ 27114 ldrb r1, [rSELF, #offThread_stackOverflowed] 27115 cmp r1, #0 @ did we overflow earlier? 27116 beq 1f @ no, skip ahead 27117 mov rFP, r0 @ save relPc result in rFP 27118 mov r0, rSELF @ r0<- self 27119 mov r1, r9 @ r1<- exception 27120 bl dvmCleanupStackOverflow @ call(self) 27121 mov r0, rFP @ restore result 27122 1: 27123 27124 /* update frame pointer and check result from dvmFindCatchBlock */ 27125 ldr rFP, [sp, #4] @ retrieve the updated rFP 27126 cmp r0, #0 @ is catchRelPc < 0? 27127 add sp, sp, #8 @ restore stack 27128 bmi .LnotCaughtLocally 27129 27130 /* adjust locals to match self->interpSave.curFrame and updated PC */ 27131 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 27132 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 27133 str r1, [rSELF, #offThread_method] @ self->method = new method 27134 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 27135 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 27136 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 27137 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 27138 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth... 27139 27140 /* release the tracked alloc on the exception */ 27141 mov r0, r9 @ r0<- exception 27142 mov r1, rSELF @ r1<- self 27143 bl dvmReleaseTrackedAlloc @ release the exception 27144 27145 /* restore the exception if the handler wants it */ 27146 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE 27147 FETCH_INST() @ load rINST from rPC 27148 GET_INST_OPCODE(ip) @ extract opcode from rINST 27149 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 27150 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception 27151 GOTO_OPCODE(ip) @ jump to next instruction 27152 27153 @ Manage debugger bookkeeping 27154 7: 27155 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc 27156 str rFP, [rSELF, #offThread_curFrame] @ update interpSave.curFrame 27157 mov r0, rSELF @ arg0<- self 27158 mov r1, r9 @ arg1<- exception 27159 bl dvmReportExceptionThrow @ (self, exception) 27160 b 8b @ resume with normal handling 27161 27162 .LnotCaughtLocally: @ r9=exception 27163 /* fix stack overflow if necessary */ 27164 ldrb r1, [rSELF, #offThread_stackOverflowed] 27165 cmp r1, #0 @ did we overflow earlier? 27166 movne r0, rSELF @ if yes: r0<- self 27167 movne r1, r9 @ if yes: r1<- exception 27168 blne dvmCleanupStackOverflow @ if yes: call(self) 27169 27170 @ may want to show "not caught locally" debug messages here 27171 #if DVM_SHOW_EXCEPTION >= 2 27172 /* call __android_log_print(prio, tag, format, ...) */ 27173 /* "Exception %s from %s:%d not caught locally" */ 27174 @ dvmLineNumFromPC(method, pc - method->insns) 27175 ldr r0, [rSELF, #offThread_method] 27176 ldr r1, [r0, #offMethod_insns] 27177 sub r1, rPC, r1 27178 asr r1, r1, #1 27179 bl dvmLineNumFromPC 27180 str r0, [sp, #-4]! 27181 @ dvmGetMethodSourceFile(method) 27182 ldr r0, [rSELF, #offThread_method] 27183 bl dvmGetMethodSourceFile 27184 str r0, [sp, #-4]! 27185 @ exception->clazz->descriptor 27186 ldr r3, [r9, #offObject_clazz] 27187 ldr r3, [r3, #offClassObject_descriptor] 27188 @ 27189 ldr r2, strExceptionNotCaughtLocally 27190 ldr r1, strLogTag 27191 mov r0, #3 @ LOG_DEBUG 27192 bl __android_log_print 27193 #endif 27194 str r9, [rSELF, #offThread_exception] @ restore exception 27195 mov r0, r9 @ r0<- exception 27196 mov r1, rSELF @ r1<- self 27197 bl dvmReleaseTrackedAlloc @ release the exception 27198 b common_gotoBail @ bail out 27199 27200 27201 /* 27202 * Exception handling, calls through "glue code". 27203 */ 27204 .if 0 27205 .LexceptionOld: 27206 SAVE_PC_FP_TO_SELF() @ export state 27207 mov r0, rSELF @ arg to function 27208 bl dvmMterp_exceptionThrown 27209 b common_resumeAfterGlueCall 27210 .endif 27211 27212 #if defined(WITH_JIT) 27213 /* 27214 * If the JIT is actively building a trace we need to make sure 27215 * that the field is fully resolved before including the current 27216 * instruction. 27217 * 27218 * On entry: 27219 * r10: &dvmDex->pResFields[field] 27220 * r0: field pointer (must preserve) 27221 */ 27222 common_verifyField: 27223 ldrh r3, [rSELF, #offThread_subMode] @ r3 <- submode byte 27224 ands r3, #kSubModeJitTraceBuild 27225 bxeq lr @ Not building trace, continue 27226 ldr r1, [r10] @ r1<- reload resolved StaticField ptr 27227 cmp r1, #0 @ resolution complete? 27228 bxne lr @ yes, continue 27229 stmfd sp!, {r0-r2,lr} @ save regs 27230 mov r0, rSELF 27231 mov r1, rPC 27232 bl dvmJitEndTraceSelect @ (self,pc) end trace before this inst 27233 ldmfd sp!, {r0-r2, lr} 27234 bx lr @ return 27235 #endif 27236 27237 /* 27238 * After returning from a "glued" function, pull out the updated 27239 * values and start executing at the next instruction. 27240 */ 27241 common_resumeAfterGlueCall: 27242 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread 27243 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh 27244 FETCH_INST() @ load rINST from rPC 27245 GET_INST_OPCODE(ip) @ extract opcode from rINST 27246 GOTO_OPCODE(ip) @ jump to next instruction 27247 27248 /* 27249 * Invalid array index. Note that our calling convention is strange; we use r1 27250 * and r3 because those just happen to be the registers all our callers are 27251 * using. We move r3 before calling the C function, but r1 happens to match. 27252 * r1: index 27253 * r3: size 27254 */ 27255 common_errArrayIndex: 27256 EXPORT_PC() 27257 mov r0, r3 27258 bl dvmThrowArrayIndexOutOfBoundsException 27259 b common_exceptionThrown 27260 27261 /* 27262 * Integer divide or mod by zero. 27263 */ 27264 common_errDivideByZero: 27265 EXPORT_PC() 27266 ldr r0, strDivideByZero 27267 bl dvmThrowArithmeticException 27268 b common_exceptionThrown 27269 27270 /* 27271 * Attempt to allocate an array with a negative size. 27272 * On entry: length in r1 27273 */ 27274 common_errNegativeArraySize: 27275 EXPORT_PC() 27276 mov r0, r1 @ arg0 <- len 27277 bl dvmThrowNegativeArraySizeException @ (len) 27278 b common_exceptionThrown 27279 27280 /* 27281 * Invocation of a non-existent method. 27282 * On entry: method name in r1 27283 */ 27284 common_errNoSuchMethod: 27285 EXPORT_PC() 27286 mov r0, r1 27287 bl dvmThrowNoSuchMethodError 27288 b common_exceptionThrown 27289 27290 /* 27291 * We encountered a null object when we weren't expecting one. We 27292 * export the PC, throw a NullPointerException, and goto the exception 27293 * processing code. 27294 */ 27295 common_errNullObject: 27296 EXPORT_PC() 27297 mov r0, #0 27298 bl dvmThrowNullPointerException 27299 b common_exceptionThrown 27300 27301 /* 27302 * For debugging, cause an immediate fault. The source address will 27303 * be in lr (use a bl instruction to jump here). 27304 */ 27305 common_abort: 27306 ldr pc, .LdeadFood 27307 .LdeadFood: 27308 .word 0xdeadf00d 27309 27310 /* 27311 * Spit out a "we were here", preserving all registers. (The attempt 27312 * to save ip won't work, but we need to save an even number of 27313 * registers for EABI 64-bit stack alignment.) 27314 */ 27315 .macro SQUEAK num 27316 common_squeak\num: 27317 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27318 ldr r0, strSqueak 27319 mov r1, #\num 27320 bl printf 27321 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27322 bx lr 27323 .endm 27324 27325 SQUEAK 0 27326 SQUEAK 1 27327 SQUEAK 2 27328 SQUEAK 3 27329 SQUEAK 4 27330 SQUEAK 5 27331 27332 /* 27333 * Spit out the number in r0, preserving registers. 27334 */ 27335 common_printNum: 27336 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27337 mov r1, r0 27338 ldr r0, strSqueak 27339 bl printf 27340 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27341 bx lr 27342 27343 /* 27344 * Print a newline, preserving registers. 27345 */ 27346 common_printNewline: 27347 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27348 ldr r0, strNewline 27349 bl printf 27350 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27351 bx lr 27352 27353 /* 27354 * Print the 32-bit quantity in r0 as a hex value, preserving registers. 27355 */ 27356 common_printHex: 27357 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27358 mov r1, r0 27359 ldr r0, strPrintHex 27360 bl printf 27361 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27362 bx lr 27363 27364 /* 27365 * Print the 64-bit quantity in r0-r1, preserving registers. 27366 */ 27367 common_printLong: 27368 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27369 mov r3, r1 27370 mov r2, r0 27371 ldr r0, strPrintLong 27372 bl printf 27373 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27374 bx lr 27375 27376 /* 27377 * Print full method info. Pass the Method* in r0. Preserves regs. 27378 */ 27379 common_printMethod: 27380 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27381 bl dvmMterpPrintMethod 27382 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27383 bx lr 27384 27385 /* 27386 * Call a C helper function that dumps regs and possibly some 27387 * additional info. Requires the C function to be compiled in. 27388 */ 27389 .if 0 27390 common_dumpRegs: 27391 stmfd sp!, {r0, r1, r2, r3, ip, lr} 27392 bl dvmMterpDumpArmRegs 27393 ldmfd sp!, {r0, r1, r2, r3, ip, lr} 27394 bx lr 27395 .endif 27396 27397 #if 0 27398 /* 27399 * Experiment on VFP mode. 27400 * 27401 * uint32_t setFPSCR(uint32_t val, uint32_t mask) 27402 * 27403 * Updates the bits specified by "mask", setting them to the values in "val". 27404 */ 27405 setFPSCR: 27406 and r0, r0, r1 @ make sure no stray bits are set 27407 fmrx r2, fpscr @ get VFP reg 27408 mvn r1, r1 @ bit-invert mask 27409 and r2, r2, r1 @ clear masked bits 27410 orr r2, r2, r0 @ set specified bits 27411 fmxr fpscr, r2 @ set VFP reg 27412 mov r0, r2 @ return new value 27413 bx lr 27414 27415 .align 2 27416 .global dvmConfigureFP 27417 .type dvmConfigureFP, %function 27418 dvmConfigureFP: 27419 stmfd sp!, {ip, lr} 27420 /* 0x03000000 sets DN/FZ */ 27421 /* 0x00009f00 clears the six exception enable flags */ 27422 bl common_squeak0 27423 mov r0, #0x03000000 @ r0<- 0x03000000 27424 add r1, r0, #0x9f00 @ r1<- 0x03009f00 27425 bl setFPSCR 27426 ldmfd sp!, {ip, pc} 27427 #endif 27428 27429 27430 /* 27431 * String references, must be close to the code that uses them. 27432 */ 27433 .align 2 27434 strDivideByZero: 27435 .word .LstrDivideByZero 27436 strLogTag: 27437 .word .LstrLogTag 27438 strExceptionNotCaughtLocally: 27439 .word .LstrExceptionNotCaughtLocally 27440 27441 strNewline: 27442 .word .LstrNewline 27443 strSqueak: 27444 .word .LstrSqueak 27445 strPrintHex: 27446 .word .LstrPrintHex 27447 strPrintLong: 27448 .word .LstrPrintLong 27449 27450 /* 27451 * Zero-terminated ASCII string data. 27452 * 27453 * On ARM we have two choices: do like gcc does, and LDR from a .word 27454 * with the address, or use an ADR pseudo-op to get the address 27455 * directly. ADR saves 4 bytes and an indirection, but it's using a 27456 * PC-relative addressing mode and hence has a limited range, which 27457 * makes it not work well with mergeable string sections. 27458 */ 27459 .section .rodata.str1.4,"aMS",%progbits,1 27460 27461 .LstrBadEntryPoint: 27462 .asciz "Bad entry point %d\n" 27463 .LstrFilledNewArrayNotImpl: 27464 .asciz "filled-new-array only implemented for objects and 'int'" 27465 .LstrDivideByZero: 27466 .asciz "divide by zero" 27467 .LstrLogTag: 27468 .asciz "mterp" 27469 .LstrExceptionNotCaughtLocally: 27470 .asciz "Exception %s from %s:%d not caught locally\n" 27471 27472 .LstrNewline: 27473 .asciz "\n" 27474 .LstrSqueak: 27475 .asciz "<%d>" 27476 .LstrPrintHex: 27477 .asciz "<%#x>" 27478 .LstrPrintLong: 27479 .asciz "<%lld>" 27480 27481