1 //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Type profiles and SelectionDAG nodes used by CellSPU 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Type profile for a call sequence 15 def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; 16 17 // SPU_GenControl: Type profile for generating control words for insertions 18 def SPU_GenControl : SDTypeProfile<1, 1, []>; 19 def SPUshufmask : SDNode<"SPUISD::SHUFFLE_MASK", SPU_GenControl, []>; 20 21 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq, 22 [SDNPHasChain, SDNPOutGlue]>; 23 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq, 24 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 25 //===----------------------------------------------------------------------===// 26 // Operand constraints: 27 //===----------------------------------------------------------------------===// 28 29 def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 30 def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall, 31 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 32 SDNPVariadic]>; 33 34 // Operand type constraints for vector shuffle/permute operations 35 def SDT_SPUshuffle : SDTypeProfile<1, 3, [ 36 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 37 ]>; 38 39 // Vector binary operator type constraints (needs a further constraint to 40 // ensure that operand 0 is a vector...): 41 42 def SPUVecBinop: SDTypeProfile<1, 2, [ 43 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 44 ]>; 45 46 // Trinary operators, e.g., addx, carry generate 47 def SPUIntTrinaryOp : SDTypeProfile<1, 3, [ 48 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0> 49 ]>; 50 51 // SELECT_MASK type constraints: There are several variations for the various 52 // vector types (this avoids having to bit_convert all over the place.) 53 def SPUselmask_type: SDTypeProfile<1, 1, [ 54 SDTCisInt<1> 55 ]>; 56 57 // SELB type constraints: 58 def SPUselb_type: SDTypeProfile<1, 3, [ 59 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<0, 3> ]>; 60 61 // SPU Vector shift pseudo-instruction type constraints 62 def SPUvecshift_type: SDTypeProfile<1, 2, [ 63 SDTCisSameAs<0, 1>, SDTCisInt<2>]>; 64 65 // "marker" type for i64 operators that need a shuffle mask 66 // (i.e., uses cg or bg or another instruction that needs to 67 // use shufb to get things in the right place.) 68 // Op0: The result 69 // Op1, 2: LHS, RHS 70 // Op3: Carry-generate shuffle mask 71 72 def SPUmarker_type : SDTypeProfile<1, 3, [ 73 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> ]>; 74 75 //===----------------------------------------------------------------------===// 76 // Synthetic/pseudo-instructions 77 //===----------------------------------------------------------------------===// 78 79 // SPU CNTB: 80 def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>; 81 82 // SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see 83 // SPUISelLowering.h): 84 def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>; 85 86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only): 87 def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>; 88 def SPUvec_srl: SDNode<"ISD::SRL", SPUvecshift_type, []>; 89 def SPUvec_sra: SDNode<"ISD::SRA", SPUvecshift_type, []>; 90 91 def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>; 92 def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>; 93 94 // Vector rotate left, bits shifted out of the left are rotated in on the right 95 def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT", 96 SPUvecshift_type, []>; 97 98 // Vector rotate left by bytes, but the count is given in bits and the SPU 99 // internally converts it to bytes (saves an instruction to mask off lower 100 // three bits) 101 def SPUrotbytes_left_bits : SDNode<"SPUISD::ROTBYTES_LEFT_BITS", 102 SPUvecshift_type>; 103 104 // Shift entire quad left by bytes/bits. Zeros are shifted in on the right 105 // SHL_BITS the same as SHL for i128, but ISD::SHL is not implemented for i128 106 def SPUshlquad_l_bytes: SDNode<"SPUISD::SHL_BYTES", SPUvecshift_type, []>; 107 def SPUshlquad_l_bits: SDNode<"SPUISD::SHL_BITS", SPUvecshift_type, []>; 108 def SPUsrl_bytes: SDNode<"SPUISD::SRL_BYTES", SPUvecshift_type, []>; 109 110 // SPU form select mask for bytes, immediate 111 def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>; 112 113 // SPU select bits instruction 114 def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>; 115 116 def SDTprefslot2vec: SDTypeProfile<1, 1, []>; 117 def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>; 118 119 def SPU_vec_demote : SDTypeProfile<1, 1, []>; 120 def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>; 121 122 // Address high and low components, used for [r+r] type addressing 123 def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>; 124 def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>; 125 126 // PC-relative address 127 def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>; 128 129 // A-Form local store addresses 130 def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>; 131 132 // Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses 133 def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>; 134 135 // i64 markers: supplies extra operands used to generate the i64 operator 136 // instruction sequences 137 def SPUadd64 : SDNode<"SPUISD::ADD64_MARKER", SPUmarker_type, []>; 138 def SPUsub64 : SDNode<"SPUISD::SUB64_MARKER", SPUmarker_type, []>; 139 def SPUmul64 : SDNode<"SPUISD::MUL64_MARKER", SPUmarker_type, []>; 140 141 //===----------------------------------------------------------------------===// 142 // Constraints: (taken from PPCInstrInfo.td) 143 //===----------------------------------------------------------------------===// 144 145 class RegConstraint<string C> { 146 string Constraints = C; 147 } 148 149 class NoEncode<string E> { 150 string DisableEncoding = E; 151 } 152 153 //===----------------------------------------------------------------------===// 154 // Return (flag isn't quite what it means: the operations are flagged so that 155 // instruction scheduling doesn't disassociate them.) 156 //===----------------------------------------------------------------------===// 157 158 def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone, 159 [SDNPHasChain, SDNPOptInGlue]>; 160
