1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the X86 specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86SUBTARGET_H 15 #define X86SUBTARGET_H 16 17 #include "llvm/CallingConv.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Target/TargetSubtargetInfo.h" 20 #include <string> 21 22 #define GET_SUBTARGETINFO_HEADER 23 #include "X86GenSubtargetInfo.inc" 24 25 namespace llvm { 26 class GlobalValue; 27 class StringRef; 28 class TargetMachine; 29 30 /// PICStyles - The X86 backend supports a number of different styles of PIC. 31 /// 32 namespace PICStyles { 33 enum Style { 34 StubPIC, // Used on i386-darwin in -fPIC mode. 35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode. 36 GOT, // Used on many 32-bit unices in -fPIC mode. 37 RIPRel, // Used on X86-64 when not in -static mode. 38 None // Set when in -static mode (not PIC or DynamicNoPIC mode). 39 }; 40 } 41 42 class X86Subtarget : public X86GenSubtargetInfo { 43 protected: 44 enum X86SSEEnum { 45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 46 }; 47 48 enum X863DNowEnum { 49 NoThreeDNow, ThreeDNow, ThreeDNowA 50 }; 51 52 enum X86ProcFamilyEnum { 53 Others, IntelAtom 54 }; 55 56 /// X86ProcFamily - X86 processor family: Intel Atom, and others 57 X86ProcFamilyEnum X86ProcFamily; 58 59 /// PICStyle - Which PIC style to use 60 /// 61 PICStyles::Style PICStyle; 62 63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or 64 /// none supported. 65 X86SSEEnum X86SSELevel; 66 67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported. 68 /// 69 X863DNowEnum X863DNowLevel; 70 71 /// HasCMov - True if this processor has conditional move instructions 72 /// (generally pentium pro+). 73 bool HasCMov; 74 75 /// HasX86_64 - True if the processor supports X86-64 instructions. 76 /// 77 bool HasX86_64; 78 79 /// HasPOPCNT - True if the processor supports POPCNT. 80 bool HasPOPCNT; 81 82 /// HasSSE4A - True if the processor supports SSE4A instructions. 83 bool HasSSE4A; 84 85 /// HasAES - Target has AES instructions 86 bool HasAES; 87 88 /// HasCLMUL - Target has carry-less multiplication 89 bool HasCLMUL; 90 91 /// HasFMA3 - Target has 3-operand fused multiply-add 92 bool HasFMA3; 93 94 /// HasFMA4 - Target has 4-operand fused multiply-add 95 bool HasFMA4; 96 97 /// HasXOP - Target has XOP instructions 98 bool HasXOP; 99 100 /// HasMOVBE - True if the processor has the MOVBE instruction. 101 bool HasMOVBE; 102 103 /// HasRDRAND - True if the processor has the RDRAND instruction. 104 bool HasRDRAND; 105 106 /// HasF16C - Processor has 16-bit floating point conversion instructions. 107 bool HasF16C; 108 109 /// HasFSGSBase - Processor has FS/GS base insturctions. 110 bool HasFSGSBase; 111 112 /// HasLZCNT - Processor has LZCNT instruction. 113 bool HasLZCNT; 114 115 /// HasBMI - Processor has BMI1 instructions. 116 bool HasBMI; 117 118 /// HasBMI2 - Processor has BMI2 instructions. 119 bool HasBMI2; 120 121 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. 122 bool IsBTMemSlow; 123 124 /// IsUAMemFast - True if unaligned memory access is fast. 125 bool IsUAMemFast; 126 127 /// HasVectorUAMem - True if SIMD operations can have unaligned memory 128 /// operands. This may require setting a feature bit in the processor. 129 bool HasVectorUAMem; 130 131 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction; 132 /// this is true for most x86-64 chips, but not the first AMD chips. 133 bool HasCmpxchg16b; 134 135 /// UseLeaForSP - True if the LEA instruction should be used for adjusting 136 /// the stack pointer. This is an optimization for Intel Atom processors. 137 bool UseLeaForSP; 138 139 /// PostRAScheduler - True if using post-register-allocation scheduler. 140 bool PostRAScheduler; 141 142 /// stackAlignment - The minimum alignment known to hold of the stack frame on 143 /// entry to the function and which must be maintained by every function. 144 unsigned stackAlignment; 145 146 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 147 /// 148 unsigned MaxInlineSizeThreshold; 149 150 /// TargetTriple - What processor and OS we're targeting. 151 Triple TargetTriple; 152 153 /// Instruction itineraries for scheduling 154 InstrItineraryData InstrItins; 155 156 private: 157 /// In64BitMode - True if compiling for 64-bit, false for 32-bit. 158 bool In64BitMode; 159 160 public: 161 162 /// This constructor initializes the data members to match that 163 /// of the specified triple. 164 /// 165 X86Subtarget(const std::string &TT, const std::string &CPU, 166 const std::string &FS, 167 unsigned StackAlignOverride, bool is64Bit); 168 169 /// getStackAlignment - Returns the minimum alignment known to hold of the 170 /// stack frame on entry to the function and which must be maintained by every 171 /// function for this subtarget. 172 unsigned getStackAlignment() const { return stackAlignment; } 173 174 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 175 /// that still makes it profitable to inline the call. 176 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 177 178 /// ParseSubtargetFeatures - Parses features string setting specified 179 /// subtarget options. Definition of function is auto generated by tblgen. 180 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 181 182 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID 183 /// instruction. 184 void AutoDetectSubtargetFeatures(); 185 186 bool is64Bit() const { return In64BitMode; } 187 188 PICStyles::Style getPICStyle() const { return PICStyle; } 189 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 190 191 bool hasCMov() const { return HasCMov; } 192 bool hasMMX() const { return X86SSELevel >= MMX; } 193 bool hasSSE1() const { return X86SSELevel >= SSE1; } 194 bool hasSSE2() const { return X86SSELevel >= SSE2; } 195 bool hasSSE3() const { return X86SSELevel >= SSE3; } 196 bool hasSSSE3() const { return X86SSELevel >= SSSE3; } 197 bool hasSSE41() const { return X86SSELevel >= SSE41; } 198 bool hasSSE42() const { return X86SSELevel >= SSE42; } 199 bool hasAVX() const { return X86SSELevel >= AVX; } 200 bool hasAVX2() const { return X86SSELevel >= AVX2; } 201 bool hasSSE4A() const { return HasSSE4A; } 202 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } 203 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } 204 bool hasPOPCNT() const { return HasPOPCNT; } 205 bool hasAES() const { return HasAES; } 206 bool hasCLMUL() const { return HasCLMUL; } 207 bool hasFMA3() const { return HasFMA3; } 208 bool hasFMA4() const { return HasFMA4; } 209 bool hasXOP() const { return HasXOP; } 210 bool hasMOVBE() const { return HasMOVBE; } 211 bool hasRDRAND() const { return HasRDRAND; } 212 bool hasF16C() const { return HasF16C; } 213 bool hasFSGSBase() const { return HasFSGSBase; } 214 bool hasLZCNT() const { return HasLZCNT; } 215 bool hasBMI() const { return HasBMI; } 216 bool hasBMI2() const { return HasBMI2; } 217 bool isBTMemSlow() const { return IsBTMemSlow; } 218 bool isUnalignedMemAccessFast() const { return IsUAMemFast; } 219 bool hasVectorUAMem() const { return HasVectorUAMem; } 220 bool hasCmpxchg16b() const { return HasCmpxchg16b; } 221 bool useLeaForSP() const { return UseLeaForSP; } 222 223 bool isAtom() const { return X86ProcFamily == IntelAtom; } 224 225 const Triple &getTargetTriple() const { return TargetTriple; } 226 227 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 228 bool isTargetFreeBSD() const { 229 return TargetTriple.getOS() == Triple::FreeBSD; 230 } 231 bool isTargetSolaris() const { 232 return TargetTriple.getOS() == Triple::Solaris; 233 } 234 235 // ELF is a reasonably sane default and the only other X86 targets we 236 // support are Darwin and Windows. Just use "not those". 237 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 238 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; } 239 bool isTargetNaCl() const { 240 return TargetTriple.getOS() == Triple::NativeClient; 241 } 242 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } 243 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } 244 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; } 245 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; } 246 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; } 247 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 248 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 249 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); } 250 251 bool isTargetWin64() const { 252 // FIXME: x86_64-cygwin has not been released yet. 253 return In64BitMode && TargetTriple.isOSWindows(); 254 } 255 256 bool isTargetWin32() const { 257 // FIXME: Cygwin is included for isTargetWin64 -- should it be included 258 // here too? 259 return !In64BitMode && (isTargetMingw() || isTargetWindows()); 260 } 261 262 bool isPICStyleSet() const { return PICStyle != PICStyles::None; } 263 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; } 264 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; } 265 266 bool isPICStyleStubPIC() const { 267 return PICStyle == PICStyles::StubPIC; 268 } 269 270 bool isPICStyleStubNoDynamic() const { 271 return PICStyle == PICStyles::StubDynamicNoPIC; 272 } 273 bool isPICStyleStubAny() const { 274 return PICStyle == PICStyles::StubDynamicNoPIC || 275 PICStyle == PICStyles::StubPIC; } 276 277 /// ClassifyGlobalReference - Classify a global variable reference for the 278 /// current subtarget according to how we should reference it in a non-pcrel 279 /// context. 280 unsigned char ClassifyGlobalReference(const GlobalValue *GV, 281 const TargetMachine &TM)const; 282 283 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the 284 /// current subtarget according to how we should reference it in a non-pcrel 285 /// context. 286 unsigned char ClassifyBlockAddressReference() const; 287 288 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls 289 /// to immediate address. 290 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const; 291 292 /// This function returns the name of a function which has an interface 293 /// like the non-standard bzero function, if such a function exists on 294 /// the current subtarget and it is considered prefereable over 295 /// memset with zero passed as the second argument. Otherwise it 296 /// returns null. 297 const char *getBZeroEntry() const; 298 299 /// getSpecialAddressLatency - For targets where it is beneficial to 300 /// backschedule instructions that compute addresses, return a value 301 /// indicating the number of scheduling cycles of backscheduling that 302 /// should be attempted. 303 unsigned getSpecialAddressLatency() const; 304 305 /// enablePostRAScheduler - run for Atom optimization. 306 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 307 TargetSubtargetInfo::AntiDepBreakMode& Mode, 308 RegClassVector& CriticalPathRCs) const; 309 310 /// getInstrItins = Return the instruction itineraries based on the 311 /// subtarget selection. 312 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 313 }; 314 315 } // End llvm namespace 316 317 #endif 318
