| /external/llvm/lib/Target/CellSPU/ |
| SPUSubtarget.h | 42 InstrItineraryData InstrItins;
75 return InstrItins;
|
| SPUTargetMachine.h | 36 InstrItineraryData InstrItins;
78 return &InstrItins;
|
| SPUSubtarget.cpp | 40 InstrItins = getInstrItineraryForCPU(default_cpu);
|
| SPUTargetMachine.cpp | 46 InstrItins(Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 53 InstrItins = getInstrItineraryForCPU(CPUString);
56 InstrItins.IssueWidth = 4;
|
| HexagonSubtarget.h | 39 InstrItineraryData InstrItins;
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| HexagonTargetMachine.h | 36 const InstrItineraryData* InstrItins;
55 return InstrItins;
|
| HexagonTargetMachine.cpp | 62 InstrItins(&Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeSubtarget.cpp | 45 InstrItins = getInstrItineraryForCPU(CPUName);
52 InstrItins.IssueWidth = 1;
|
| MBlazeSubtarget.h | 39 InstrItineraryData InstrItins;
62 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| MBlazeTargetMachine.h | 41 InstrItineraryData InstrItins;
54 { return &InstrItins; }
|
| MBlazeTargetMachine.cpp | 45 InstrItins(Subtarget.getInstrItineraryData()) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMSubtarget.cpp | 100 InstrItins = getInstrItineraryForCPU(CPUString);
197 for (const InstrItinerary *itin = InstrItins.Itineraries;
199 const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
202 InstrItins.IssueWidth = 0;
204 ++InstrItins.IssueWidth;
208 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
|
| ARMSubtarget.h | 159 InstrItineraryData InstrItins;
263 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| ARMTargetMachine.h | 39 InstrItineraryData InstrItins;
51 return &InstrItins;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.h | 58 InstrItineraryData InstrItins;
104 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| PPCTargetMachine.h | 38 InstrItineraryData InstrItins;
64 return &InstrItins;
|
| /external/llvm/lib/CodeGen/ |
| DFAPacketizer.cpp | 36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
|
| ScheduleDAGInstrs.cpp | 41 InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
302 unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
419 unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
739 if (!InstrItins || InstrItins->isEmpty()) {
747 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
753 if (!InstrItins || InstrItins->isEmpty())
792 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
798 if (!InstrItins || InstrItins->isEmpty()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetMachine.h | 37 InstrItineraryData InstrItins;
69 return &InstrItins;
|
| X86Subtarget.h | 154 InstrItineraryData InstrItins;
312 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
| /external/llvm/include/llvm/CodeGen/ |
| DFAPacketizer.h | 45 const InstrItineraryData *InstrItins;
|
| ResourcePriorityQueue.h | 63 const InstrItineraryData* InstrItins;
|
| /external/llvm/lib/Target/Mips/ |
| MipsSubtarget.cpp | 43 InstrItins = getInstrItineraryForCPU(CPUName);
|
| MipsSubtarget.h | 89 InstrItineraryData InstrItins;
|
