/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 52 // AssertSext, AssertZext - These nodes record if a register contains a 57 AssertSext, AssertZext, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 80 case ISD::AssertZext: return "AssertZext";
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LegalizeIntegerTypes.cpp | 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, 381 return DAG.getNode(ISD::AssertZext, dl, [all...] |
SelectionDAG.cpp | [all...] |
SelectionDAGBuilder.cpp | 95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 214 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 694 // now, just use the tightest assertzext/assertsext possible. 718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, [all...] |
SelectionDAGISel.cpp | [all...] |
TargetLowering.cpp | [all...] |
LegalizeDAG.cpp | [all...] |
DAGCombiner.cpp | 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 345 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |